JPH01307829A - Information processor - Google Patents

Abstract

PURPOSE:To branch the control to a processing routine corresponding to a data type by storing the operation result of the tag field of an operand in a condition register and determining the branch routine based on the result. CONSTITUTION:An instruction controller 1 reads out an instruction from a storage controller 2 and decodes it and transfers the operation code or the like to an arithmetic unit 3. The unit 3 performs the operation of transferred information to update contents of a main storage device omitted in the figure through various registers and statuses or the controller 2. A computing element 37 stores upper two bits of the operation result or the operand in a condition register 39 together with another carry output or the like at the time of operation or operand loading. A branch discriminating circuit 42 determines the branch routine based on decode information inputted from a decode information queue 19 of the controller 1 through a decode information register 31 or the like and data stored in the register 39.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an information processing device, and in particular includes a condition register whose contents change in response to an operation result or the loading of an operand, and a tag indicating the data type of an argument. The present invention relates to an information processing apparatus that adds a tag field to data itself or a pointer indicating the data, and determines a processing routine according to the value of the tag field added.

[Conventional technology]

Conventionally, this type of information processing apparatus has performed software processing in which the values of predetermined fields of operands are compared using a comparison instruction and branching is performed based on the result.

In addition, Information Processing Society of Japan Research Report CA has a dedicated instruction that branches directly depending on the value of a specified field.
63-5), and those that similarly branch at the microinstruction level depending on field values (Information Processing Soku Gakkai Vol. 3).
There are 4 national conventions (6P-5).

[Problem to be solved by the invention]

In the field of software, there is an idea called functional functions. In conventional function processing, different functions are used depending on the data type of the operand.

For example, in FORTRAN, the data type of the argument is an integer,
Assuming there are three types: floating point numbers and high-precision floating point numbers,
Correspondingly, the ABS function is also IΔBS.

The function names were different, such as ABS and DABS.

In other words, it was sufficient to have different entry addresses for function processing and to perform processing dedicated to that data type. The idea of this functional is that the same function can be used regardless of the data type of the argument, and the functional processing routine must separate processing by determining the type of data passed as an argument. First, information for determining the data type is attached to such arguments. There are several ways to add this data type information, one of which is to add a data type called a tag to the data itself or to a pointer pointing to the data. This method of adding tags is often used in LISP processing systems, and as shown in Figure 3 (a), the tag of the argument added at the beginning of function processing is determined and the data type of the argument is determined. Processing such as branching to a processing routine corresponding to (FIG. 3(b)) is required. In conventional information processing devices, this processing is performed by software, but mask processing, comparison processing, and branch processing other than the tag part appear many times, the number of instructions increases, and efficiency decreases. The information processing device shown in Information Processing Society of Japan Research Report CA 63,-5 is
Although it is possible to separate data types by providing an instruction to branch using a tag as an index, an additional branch instruction is required when branching to each processing routine. In this way, branch instructions are processed continuously, and the overhead of branch instruction processing is large, reducing throughput, especially in an information processing apparatus that employs a pipeline processing method. The information processing device shown in Information Processing Society of Japan's National Conference 6P-5 branches at the microinstruction level, so there is no branch instruction processing overhead, but it is said that user-defined functions other than built-in functions cannot be processed with microinstructions. There are drawbacks.

[Means to solve the problem]

The information processing device of the present invention includes a branch determination means in which a calculation result or the content of a predetermined tag field of an operand to be loaded is stored in a condition register, and a branch direction is determined according to the data stored in the condition register. have.

[Effect]

The operation result or the content of the predetermined tag field of the loaded operand is stored in the condition register, and the processing routine is determined based on that data. Mask processing, comparison processing, and branch processing for information other than the added tag part are no longer necessary.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a main part configuration of an embodiment of an information processing apparatus of the present invention, and FIG. 2 is a diagram showing an example of a functional program.

The information processing device of this embodiment includes an instruction-based m device 1, a storage control device 2, and an arithmetic unit @3, and the arguments include tags, that is, data type information, as shown in FIG. is added.

The instruction control unit @1 reads the instruction from the storage control bag @2, decodes it, calculates an address to obtain a logical address if necessary, and transfers the operation code, operand, operation information, etc. to the arithmetic unit 3. The arithmetic device 3 performs arithmetic operations based on the information transferred from the instruction control device @1, and updates various registers and statuses, or a main storage device (not shown) through the storage control device 2. The arithmetic unit 3 includes an arithmetic unit 37, a condition register 39, and a branch determination circuit 42. When performing an operation or loading an operand, the arithmetic unit 37 calculates the operation result or the upper two operands to be loaded.
The bit is stored in the condition register 39 along with other carry outputs, etc. The branch determination circuit 42 executes a branch routine based on the decode information input from the decode information queue 19 of the instruction control device 1 via the decode information register 31 and registers 40.41 and the data stored in the condition register 39. Determine.

Next, the operation of this embodiment will be explained.

In the instruction control device 1, data is read from the general-purpose register file 13 using the bit field of the instruction register 11. At this time, if the contents of the instruction register 11 are RX type instructions, the index value and base value are read from the general-purpose register file 13 in order to generate the execution address of the operand. The index value and base value are set in the index register 15, base register 16, and displacement register 14, respectively, along with the displacement value directly specified by the instruction. Then, the address adder 17 generates an operand address based on these three values and transfers it to the storage control device 2. This operand address is register 2
1 to the address conversion unit 22, and the address is converted by the address conversion mechanism 221. Further, along with the directory information read from the address array 222, an operand is read from the data array 24 by being sent to the data array 24 via the register 23 and serving as a read address of the data array 24. will be forwarded to. On the other hand, the first RX type instruction
The register numbers of the registers storing the operands and the first and second operands in the case of RR type instructions are the register 18 of the instruction control bag @1 and the decode information queue 19.
The data is then transferred to the arithmetic unit 3. The arithmetic device 3 that has received the operand and register number reads the operand from the general-purpose register file 32 based on the register number sent from the instruction control device 1 prior to the operation. One of the read operands is stored in the calculation register 35 as the first operand, and the other operand is the selection input to the selector 33 together with the operand transferred directly from the storage control device 2 or via the data buffer 34. and stored in the arithmetic register 36 as the second operand. A desired operation is performed on the operands stored in the operation registers 35 and 36 by the operation unit 37, and the result of the operation is sent to the general-purpose register 13.
32. Furthermore, this calculation result is also reflected in three condition registers. Further, if the instruction is a load instruction, the operand is read from the storage controller 2, and the operand is sent to the 'e4 calculator 37 and the result register 3.
8 and is similarly stored in general-purpose register 13.32,
Condition register 39 also changes. At this time, the upper two bits of the output of the arithmetic unit 37 are stored in the condition register 39 along with other carry outputs, etc., and are sent to the branch judgment circuit 42 along with the decode information sent from the decode information register 31 via registers 40 and 41. ,
Then, the branch direction is determined based on this information.

Note that the upper two bits of the output of the arithmetic unit 37 indicate a part of the tag as described above, so determining the branch direction based on these two bits of data means that the processing routine according to the tag is used as in the past. It will branch to.

Next, the branch direction determination process will be explained with reference to the program shown in FIG.

Address $ADD1 is the entry address of the functional, and the argument specified by 'ARGUHENT' is loaded into RO by the load instruction.At this time, the upper two bits of the argument are stored in the condition register 39.

The next BRAO instruction is a branch instruction that branches when the value of 2 bits in the condition register 39 is "00". 2
If the bit value is "00", it is determined that the argument is an integer, and the program branches to an integer processing routine ($INTEGER). Similarly, the BRA1 instruction
A branch instruction that branches when the 2-bit value of
If the value of the bit is "01", it is determined that the argument is a floating point number, and the floating point number processing routine ($ FLOA
Branch to T). Similarly, the BRA2 instruction branches to $DELOAT when the value of 2 bits is 10''. Therefore, immediately after loading the argument into the register, the branch instruction can be used to branch to the processing routine for each data type.

Note that in this embodiment, the upper two bits of the output of the arithmetic unit 37 are stored in three condition registers, but the field stored in the condition register 39 can be any number of bits from any bit position, and the length is limited to 2 bits. do not have. Furthermore, branch routines can be added depending on the bit length.

〔Effect of the invention〕

As explained above, the present invention stores a predetermined tag field of an operation result or an operand to be loaded in a condition register, and determines a branch routine based on the result. , it is possible to branch to a processing routine according to the data type, which is particularly effective in reducing the overhead of argument processing in programs such as LISP where functionals appear frequently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of an embodiment of the information processing apparatus of the present invention, FIG. 2 is a diagram showing an example of a functional program, and FIG. 3 is an example of specifying data type by tag. FIG. 1... Command control device, 2... Storage control device, 3
...Arithmetic unit, 11...Instruction register, 1
2... Decoder, 13.32... General purpose register file, 14... Displacement register, 15... Index register, 16... Pace register, 17... Address adder, 18.21. 23,40.41...Register, 19
. . . decode information queue, 22 . . . address conversion unit, 24 . . . data array,
31... Decode information register, 33... Selector, 34... Data buffer, 35.36... Arithmetic register, 37... Arithmetic unit, 38... Result register,
39...Condition register, 42...Branch judgment circuit. $ADD1: LD RO, ARGIJME
NTBRAO$ t NTEGER BRAI $ FLOAT BRA 2 $ DFLOAT Figure 2 10-DFLOAT

Claims (1)

[Claims] 1. A condition register whose contents change in response to the load of an operation result or an operand is provided, a tag indicating the data type of the argument is added to the data itself or a pointer indicating the data, and the added tag is provided. In an information processing device that determines a processing routine according to a value of a tag field, the condition register stores an operation result or the contents of a predetermined tag field of an operand to be loaded, and 1. An information processing device comprising: a branch determination unit that determines a branch direction according to content.