JPH01310534A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01310534A
JPH01310534A JP14139188A JP14139188A JPH01310534A JP H01310534 A JPH01310534 A JP H01310534A JP 14139188 A JP14139188 A JP 14139188A JP 14139188 A JP14139188 A JP 14139188A JP H01310534 A JPH01310534 A JP H01310534A
Authority
JP
Japan
Prior art keywords
film
mask
semiconductor device
conductivity
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14139188A
Other languages
Japanese (ja)
Inventor
Hiroshi Takagi
洋 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14139188A priority Critical patent/JPH01310534A/en
Publication of JPH01310534A publication Critical patent/JPH01310534A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the occurrence of electrostatic breakdown as well as to contrive improvement in reliability by a method wherein a multilayer film, consisting of at least two or more kinds of layers consisting of different materials including at least a conductive film, is used as a mask in a impurity implanting process. CONSTITUTION:An insulating film 2 for isolation, thin insulating films 3a and 3b, and a polysilicon gate 4 are formed on the desired place on an Si substrate 1, and an oxide film 6, which is a first layer mask, is formed on the whole surface. Then, a conductivity film 7 is coated on the whole upper surface as a second layer mask, a photoresist 5 is coated on the whole upper surface of the conductivity film 7, a desired pattern is formed, and an aperture is provided. Then, using the photoresist 5 as a mask, the conductivity film 7, the oxide film 6 and the thin oxide film 3b are removed successively, the photoresist 5 is removed, and impurity ions 8 are implanted in the state wherein the conductivity film 7 is exposed to the top surface. At this time, the positive electric charge implanted in the conductivity film 7 is discharged along the film 7, after the implanting work has been finished, the conductivity film 7 and the oxide film 6 are removed. As a result, the occurrence of electrostatic reliability and the yield of production can be achieved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置の製造方法に関し、特に不純物イ
オンを所定の領域に注入するイオン注入工程において半
導体装置がチャージアップし半導体装置内の絶縁薄膜が
静電破壊することのない半導体装置の製造方法に関する
ものである。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular, during an ion implantation process in which impurity ions are implanted into a predetermined region, the semiconductor device is charged up and an insulating thin film within the semiconductor device is damaged. The present invention relates to a method of manufacturing a semiconductor device that is free from electrostatic damage.

〔従来の技術〕[Conventional technology]

第2図は従来の半導体装置の製造方法を示す断面工程図
であり、図において、1はSi基板、2は素子分離用の
絶縁膜(一般には5io2)、3a及び3bは薄い絶縁
膜であり、4はポリシリコンゲートである。また5は所
望のSi基板中に不純物イオンを打ち込むためのフォト
マスクである。
FIG. 2 is a cross-sectional process diagram showing a conventional method for manufacturing a semiconductor device. In the figure, 1 is a Si substrate, 2 is an insulating film for element isolation (generally 5io2), and 3a and 3b are thin insulating films. , 4 is a polysilicon gate. Further, 5 is a photomask for implanting impurity ions into a desired Si substrate.

次に製造工程について説明する。まず、第2図(a)に
示すように、フォトマスク5をエツチングマスクとして
薄い絶縁膜3bを除去し、続いて第2図tb+に示すよ
うにイオン注入器を用いて不純物イオン8を半導体装置
全面に注入する。このとき、前記フォトマスク5は正に
帯電し、その帯電量が増加し、Si基板1が接地した瞬
間に第2図(C1に示すように最も弱い薄い酸化膜3a
を破壊して短絡する。その結果、半導体装置が正常な機
能を失う。
Next, the manufacturing process will be explained. First, as shown in FIG. 2(a), the thin insulating film 3b is removed using the photomask 5 as an etching mask, and then impurity ions 8 are implanted into the semiconductor device using an ion implanter as shown in FIG. Inject all over. At this time, the photomask 5 is positively charged, the amount of charge increases, and the moment the Si substrate 1 is grounded, the weakest thin oxide film 3a is shown in FIG. 2 (C1).
Destroy and short circuit. As a result, the semiconductor device loses its normal function.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体装置の製造方法は以上のように構成されて
いるので、そのイオン注入工程において静電破壊が生じ
、半導体装置がその機能を失うという問題点があった。
Since the conventional method for manufacturing a semiconductor device is configured as described above, there is a problem in that electrostatic discharge damage occurs in the ion implantation process and the semiconductor device loses its function.

現在この静電破壊を防止する方法としては注入電流値を
極端に低下させる方法があるが、生産性が落ちる。又、
イオン注入器に帯電防止対策を施す手段があるが、高価
でかつ不完全である。
Currently, there is a method for preventing this electrostatic damage by drastically reducing the injection current value, but this reduces productivity. or,
There are means to provide antistatic measures to ion implanters, but they are expensive and incomplete.

この発明は上記のような問題点を解消するためになされ
たもので、イオン注入工程において静電破壊の生じない
信頼性が高くかつ高歩留の半導体装置の製造方法を得る
ことを目的とする。
This invention was made to solve the above-mentioned problems, and its purpose is to provide a highly reliable and high-yield method for manufacturing semiconductor devices that does not cause electrostatic damage during the ion implantation process. .

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は不純物注入工程
において少なくとも1種類の導電性膜を含む2種以上の
異なった材料からなる2層以上の多層構造の膜をマスク
として用いて不純物注入を行うようにしたものである。
A method for manufacturing a semiconductor device according to the present invention includes implanting impurities using a film having a multilayer structure of two or more layers made of two or more different materials including at least one type of conductive film as a mask in the impurity implantation step. This is what I did.

〔作用〕[Effect]

この発明においては導電性のマスクを用いて不純物注入
を行うようにしたから、イオン注入工程における静電破
壊を防止できる。
In this invention, since impurity implantation is performed using a conductive mask, electrostatic damage during the ion implantation process can be prevented.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図は本発明の一実施例による半導体装置の製造方法を示
す断面工程図であり、図において、1はSi基板1.2
は素子分離用の絶縁膜(一般には5tou)、3a、3
bは薄い絶縁膜、4はポリシリコンゲート、5はフォト
レジスト、6は第1N目のマスクとしての酸化膜、7は
第2層目のマスクとしての導電性膜(例えばAN)、8
はイオン注入される不純物イオンである。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional process diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a Si substrate 1.2
is an insulating film for element isolation (generally 5tou), 3a, 3
b is a thin insulating film, 4 is a polysilicon gate, 5 is a photoresist, 6 is an oxide film as a first Nth mask, 7 is a conductive film (for example, AN) as a second layer mask, 8
is the impurity ion to be implanted.

次に製造工程について説明する。Next, the manufacturing process will be explained.

まず、第1図(alに示すように、Si基板l上の所望
の箇所に分離用絶縁膜2.薄い絶縁膜3a。
First, as shown in FIG. 1 (al), an isolation insulating film 2 and a thin insulating film 3a are deposited on desired locations on a Si substrate l.

3b、ポリシリコンゲート4を形成した後に、半導体装
置全面に第1層目のマスクである酸化膜6を形成する。
3b, after forming the polysilicon gate 4, an oxide film 6 serving as a first layer mask is formed over the entire surface of the semiconductor device.

この形成方法としては低温CVDや塗布方法等がある。Examples of this forming method include low-temperature CVD and coating methods.

次に第1図(b)に示すように、第2層目のマスクとし
て導電性膜7を前記酸化膜6上全面にわたって被覆する
。さらに第1図(C)に示すように、フォトレジスト5
を導電性膜7上全面にわたって塗布し、所望のパターン
を形成して開口部を設ける。引き続いて第1図(d)に
示すように、フォトレジスト5をマスクとして導電性膜
7゜酸化膜6そして薄い酸化If!3bを順に除去する
Next, as shown in FIG. 1(b), a conductive film 7 is coated over the entire surface of the oxide film 6 as a second layer mask. Furthermore, as shown in FIG. 1(C), a photoresist 5
is applied over the entire surface of the conductive film 7 to form a desired pattern and provide openings. Subsequently, as shown in FIG. 1(d), using the photoresist 5 as a mask, conductive film 7° oxide film 6 and thin oxide If! 3b are removed in order.

そして、第1図(e)に示すように、フォトレジスト5
を除去して導電性膜7が最表面に露出した状態で、イオ
ン注入器を用いて不純物イオン8を注入する。この時、
導電性膜7上に注入された正の電荷は導電性膜7を伝わ
って放電し、第1図if)に示すように半導体装置は帯
電することはない。注入完了後第1図(g)に示すよう
に、導電性膜7及び酸化膜6を除去して注入工程を完了
とする。
Then, as shown in FIG. 1(e), the photoresist 5
With the conductive film 7 exposed at the outermost surface by removing the conductive film 7, impurity ions 8 are implanted using an ion implanter. At this time,
The positive charges injected onto the conductive film 7 are discharged through the conductive film 7, and the semiconductor device is not charged as shown in FIG. 1 if). After the implantation is completed, as shown in FIG. 1(g), the conductive film 7 and the oxide film 6 are removed to complete the implantation process.

このように、本実施例ではイオン注入工程に用いるマス
クを酸化膜とgl、電性膜の2層構造とし、イオン注入
時に注入される正の電荷を上記導電性膜を介して放電す
るようにしたから、マスクの帯電による半導体装置の静
電破壊を防止できる。
As described above, in this example, the mask used in the ion implantation process has a two-layer structure consisting of an oxide film, GL, and a conductive film, so that the positive charges injected during ion implantation are discharged through the conductive film. Therefore, electrostatic damage to the semiconductor device due to charging of the mask can be prevented.

(発明の効果〕 以上のように、この発明によれば導電性膜を含んだ多層
構造のマスクによって不純物イオン注入を行うようにし
たから、帯電による半導体装置の静電破壊のない信頼性
が高く、かつ高歩留の半導体装置の製造方法を実現でき
る効果がある。
(Effects of the Invention) As described above, according to the present invention, since impurity ion implantation is performed using a mask with a multilayer structure including a conductive film, the semiconductor device is highly reliable without electrostatic damage due to charging. , and has the effect of realizing a high-yield semiconductor device manufacturing method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体装置の製造方
法を示す断面工程図、第2図は従来の半導体装置の製造
方法を示す断面工程図である。 1はSi基板、2は分離用絶縁膜、3は薄い牟色縁膜、
4はポリシリコンゲート、5はフォトレジスト、6は第
1層目のマスク(酸化膜)、7は第2層目のマスク(導
電性膜)、8は不純物イオン。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a cross-sectional process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional process diagram showing a conventional method for manufacturing a semiconductor device. 1 is a Si substrate, 2 is an isolation insulating film, 3 is a thin gray border film,
4 is a polysilicon gate, 5 is a photoresist, 6 is a first layer mask (oxide film), 7 is a second layer mask (conductive film), and 8 is an impurity ion. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体装置の製造方法において、 不純物イオンを所定領域に注入するイオン注入工程にお
いて少なくとも1種類の導電性膜を含む2種以上の異な
った材料からなる2層以上の多層構造の膜をマスクとし
て用いることを特徴とする半導体装置の製造方法。
(1) In a method for manufacturing a semiconductor device, in an ion implantation step in which impurity ions are implanted into a predetermined region, a film having a multilayer structure of two or more layers made of two or more different materials including at least one type of conductive film is masked. 1. A method for manufacturing a semiconductor device, characterized in that the method is used as a semiconductor device.
JP14139188A 1988-06-08 1988-06-08 Manufacture of semiconductor device Pending JPH01310534A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14139188A JPH01310534A (en) 1988-06-08 1988-06-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14139188A JPH01310534A (en) 1988-06-08 1988-06-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01310534A true JPH01310534A (en) 1989-12-14

Family

ID=15290902

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14139188A Pending JPH01310534A (en) 1988-06-08 1988-06-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01310534A (en)

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