JPH01311638A - Frame synchronization device - Google Patents

Abstract

PURPOSE:To shorten a frame synchronization recovering time by providing plural timing indication circuits to indicate the re trieval of frame synchronization data at a specific bit position. CONSTITUTION:A decision circuit 3, when receiving the detecting signal of the frame synchronization data from a coincidence detection circuit 1, sends out reset signals sequentially to the timing indication circuits (41-4N), and the timing indication circuits (41-4N) send out trigger signals to the decision circuit 3 after the interval of three subframes. The decision circuit 3 detects the trigger signal from which timing indication circuit 4 it is sent, and decides whether or not the frame synchronization data with a bit pattern different from that of stored frame synchronization data related to the previous detection by the output signal of the coincidence detection circuit 1. In such a way, it is possible to perform the retrieval of the frame synchronization data at plural bit positions, and to shorten the frame synchronization recovering time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame synchronization device used for data transmission using a frame synchronization method.

[Conventional technology]

The fifth order group of digital hierarchy (DS) in our country
-5-397,200 kbps), the tL;S data structure used in
It has a multiframe configuration consisting of six subframes each having a length of 6 bits.

Among the first to sixth subframes, 4-bit frame synchronization data Fl and F2 are arranged at the beginning positions of the first subframe and the fourth subframe, respectively.

Here, the frame synchronization data F1 has a bit pattern rllQOJ, and the frame synchronization data F2 has a bit pattern rllQOJ.
The bit pattern is ollJ.

A frame synchronization device as shown in FIG. 5 is known as a device that achieves synchronization using data having such a configuration. The input signal (data) is given to a 4-bit shift register 51, and its 4-bit parallel output signal is sent to a coincidence detection circuit 5.
Sent to 2. In the match detection circuit 52, the shift register 5
It is detected whether the output signal of 1 matches the frame synchronization data Fl, F2, and if they match, an active reset signal is given to the counter 53. The counter 53 is incremented in synchronization with the arrival of each bit of the input signal, and is incremented from 0 to 76.
7 (256x3-1), and when it reaches 767, the bird gives a signal to the coincidence detection circuit 52. When the coincidence detection circuit 52 is given the tri-power signal, it detects whether or not frame synchronization data with a bit pattern different from the previously detected frame synchronization data has arrived, and when the arrival of the frame synchronization data is detected, synchronization is performed. Since this is a synchronization establishment signal, a synchronization establishment signal (not shown) is activated to indicate standards for data extraction, etc.

[Problem to be solved by the invention]

However, in this frame synchronization device, when the data in the register 51 matches the frame synchronization data F1 at the timing when the bit indicated by fl arrives as shown in FIG. 6, the reset signal becomes active. Even if true frame synchronization data has not arrived at the bit timing, the search for frame synchronization data is not performed until after the next 768 bits (indicated by F2). Then, at the bit timing of F2, for example, F2
is not detected, the match detection circuit 52 starts searching for frame synchronization data at each bit position.

Here, assuming that the bit positions indicated by Fl and F2 in the figure are the timing at which true frame synchronization data arrives, if frame synchronization data is not detected up to the position indicated by Fl for the first time after restarting the above search, However, for example, if frame synchronization data F2 is detected at the timing of the F3 bit, frame synchronization data is not searched until an out-of-synchronization is detected 768 bits later at the timing of the F4 bit, and frame synchronization is not established. There was a problem with the time delay.

Here, the frame length F (
256X6) using a first-order approximation, the frame synchronization recovery time - F/4 + 1 (256X6) / (4X 8) IX F/2 - (24 + 1/4) F ... (1)
becomes.

The above frame synchronization method actually requires frame synchronization data to be detected at the same bit position in each frame several times in succession until frame synchronization is established.
In ITT, it has been standardized as a forward protection stage. However, 7. Since there is no standard for how many forward protection stages are required for the DS-5 rate in our country, here, frame synchronization data Fl is used.

When F2 is detected continuously, it is treated as frame synchronization established.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a frame synchronization device that can shorten the frame synchronization recovery time and perform accurate data transmission.

[Means to solve the problem]

A frame synchronization device according to the present invention includes a coincidence detection circuit that searches for frame synchronization data consisting of at least one type of predetermined bit pattern at each bit position of incoming data;
A plurality of timing instruction circuits instructing to search for frame synchronous data at bit positions spaced by a predetermined frame interval from the timing at which the frame synchronous data is detected by the coincidence detection circuit, and the timing of the search instruction by the plurality of timing instruction circuits. and a determination circuit that determines frame synchronization based on whether or not the search result of the match detection circuit indicates detection of predetermined frame synchronization data.

[Effect]

Since the frame synchronization device according to the present invention is configured as described above, it is possible to search for frame synchronization data at a plurality of bit positions within a predetermined frame interval. Since there is a high possibility that frame synchronization will be established in this case, the frame synchronization recovery time can be shortened.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 to 4 of the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

FIG. 1 shows a frame synchronization device according to an embodiment of the present invention. In the same figure, reference numeral 1 indicates a coincidence detection circuit, which detects r at each bit position of digital data coming from line 2.
Frame synchronization data F1 having a bit pattern of llooJ and frame synchronization data F2 having a bit pattern of rollJ are searched, and when one of these frame synchronization data is detected, the corresponding detection signal is made active and output to the determination circuit 3. Judgment circuit 3 is match detection circuit 1
When receiving an active detection signal from , it sequentially sends a reset signal as active to the timing instruction circuits 4 to 4N which are in an empty state.

In this case, the determination circuit 3 determines that the detection signal is the frame synchronization signal F.
It is stored which signal indicates whether l or F2 was detected. Specifically, if the search for frame synchronization data is started from time point A shown in FIG. 2 and the same bit pattern as frame synchronization data F1 is detected at the bit position indicated by fl, then the detection of F1 is stored. At the same time, the timing instruction circuit 4 outputs the heliset signal as active. Further, if the same bit pattern as the frame synchronization data F2 is detected at the bit position indicated by F2, the detection of F2 is stored and the timing instruction circuit 4□ heliset signal is sent out as active. Other timing instruction circuits 4 are used in the same manner.

When the timing instruction circuits 4 to 4N are given a reset signal, the birds send the signal to the determination circuit 3 after an interval of 3 subframes (256×3 bits). Judgment circuit 3
When the trigger signal is received, it detects from which timing instruction circuit 4 the trigger signal is sent, and determines whether frame synchronization data with a bit pattern different from the stored frame synchronization data related to the previous detection is detected. , the determination is made based on the output signal of the coincidence detection circuit 1. Here, Fl.

When determining that frame synchronization data is detected consecutively with F2 (or F2.Fl), the determination circuit 3 outputs a synchronization establishment signal (not shown) as active, indicating the cutting timing of the incoming framed data, etc. . If the timing instruction circuit 4 is not reset after outputting the trigger signal, it will continue to output the trigger signal and will indicate an empty state.

FIG. 3 is a diagram specifically showing one embodiment of the present invention.

As shown in the figure, a coincidence detection circuit 1 receives a 4-bit shift register 1 and frame synchronization data Fl.

EX-OR gates 12 to 124 degrees 13 to 134, each with the F2 bit pattern preset to one terminal.
is provided. EX-OR ■ The outputs of the gates 12 to 124 are wired-OR connected and the output is given to the judgment circuit 3, and the EX-OR gate 1
Outputs 3 to 134 are wired-OR connected and the outputs are given to the determination circuit 3. Reference numerals 41 to 41N are counters which are timing instruction circuits 4 to 4N, respectively, and output a trigger signal (pulse) which increments from 0 to 767. Note that the shifting of the shift register 1 and the incrementing of the counter 41 occur every time each bit arrives by a clock generated from the bits of incoming data. Furthermore, the incoming data has the DS-5 data format shown in FIG.

In the frame synchronization device configured as described above, the search for frame synchronization data is started from the point A when 4 bits of data are aligned in shift register 1 (FIG. 2). fl
At the bit position indicated by , the same bit pattern as the frame synchronization data F1 is detected, and the counter 411 is reset. Furthermore, the same bit pattern as the frame synchronization data F2 is detected at the bit position indicated by F2, and the counter 411 is reset. Counter 411 is 76
7, a trigger signal is output, and the judgment circuit 3
It is detected whether the output signal (2) of the OR gates 13 to 134 is active (L). This F3
EX-OR gates 13 to 134 at the bit positions indicated by
The reason why the output signal of F1 is detected is that the window circuit 3 stores F1 detection at the bit position indicated by fl.

At this time, unless the (1) output signals of the EX-OR gates 13 to 134 become active, the determination circuit 3 does not reset the counter 41. Similarly, the operation of detecting whether the output signals of EX-OR gates 12 to 124 are active at the bit position indicated by F4 is performed based on the trigger signal output from counter 412. In this example, Fl,
Since the bit position indicated by F2 is the position at which the true frame synchronization data arrives, the output signals of the EX-OR gates 12 to 124 are not active at the bit position indicated by F4. Do not reset.

On the other hand, since the outputs of the EX-OR gates 13 to 134 become active at the position where the frame synchronization data F2 first arrives, the determination circuit 3 resets the counter 4N and stores the detection of F2. After 3 subframes (256 x 3 bits) from this, a trigger signal is output from the counter 41N, and the determination circuit 3 uses the EX
-Detect whether the output signals of the OR gates 12 to 124 become active. In this case, frame synchronization data F1
Since F1 is detected, the determination circuit 3 resets the counter 4N again, stores the F1 detection, and outputs the frame synchronization establishment signal as active. In this way,
Frame synchronization data can be detected more quickly by using the plurality of counters 41, and the frame synchronization recovery time can be shortened.

Note that when the number of counters 41 is small, efficiency can be further improved by changing the configuration of the determination circuit 3 as follows. In the bit position that is repeated corresponding to the bit position where no frame synchronization data was detected from the initial state until all counters are reset, even if frame synchronization data is detected from the second time onwards, it will be ignored. Configure. That is, even if frame synchronization data F2 is detected at the bit position indicated by F5 in FIG. 2, the counter 41 is not reset. In other words, since F5 and F1 of frame synchronization were not detected at the bit position indicated by -1 one cycle before the bit position indicated by F5, this is the bit position where true frame synchronization is established. I don't.

The frame synchronization return time achieved by the frame synchronization device of this embodiment is calculated by first-order approximation, where the number of counters 41 is N: frame synchronization return time=F/4+ (24/N)F (2)
It can be seen that when the number N of counters 41 increases compared to equation (1), the frame synchronization recovery time can be shortened.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, in this embodiment, the frame synchronization establishment signal is made active at the bit position where frame synchronization data is detected consecutively for the first time, but the frame synchronization establishment signal is made active by performing several stages of forward protection. This allows for more reliable synchronization. Moreover, although the timing instruction circuits are used randomly, the ones in the vacant state may be used, but the ratio may be determined for each frame synchronization data of a predetermined bit pattern. In this way, there is no need to remember what the bit pattern of the frame synchronization data related to the previous detection was. Furthermore, although the present embodiment shows processing for data having a multi-frame structure, the present invention is applicable even to data not having a multi-frame structure.

〔Effect of the invention〕

As described above in detail, in the present invention, a plurality of timing instruction circuits are provided that instruct a search for frame synchronous data at bit positions spaced apart by a predetermined frame interval from the timing at which frame synchronous data is detected. This means that there are multiple candidate bit positions for establishing synchronization, which has the effect of shortening the time it takes to detect the bit position for establishing true frame synchronization and improving the efficiency of data transmission. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frame synchronization device according to an embodiment of the present invention, FIG. 2 is a diagram showing the operation of the embodiment shown in FIG. 1, and FIG. 3 is a diagram showing the operation of the embodiment shown in FIG. 4 is a diagram showing the data format of the digital hierarchy DS-5, FIG. 5 is a diagram showing the configuration of a conventional frame synchronization device, and FIG. It is a figure which shows the operation|movement of the conventional example shown. 1... Coincidence detection circuit, 3... Judgment circuit, 4, ~4N
...Timing instruction circuit, 11...Shift register, 12-12.13-134...EX-OR gate, 41-41N...Counter. ■ Figure 3

Claims (1)

[Claims] A coincidence detection circuit that searches for frame synchronization data consisting of at least one kind of predetermined bit pattern at each bit position of incoming data; a plurality of timing instruction circuits that instruct a search for frame synchronous data at bit positions spaced apart from each other; and a search result of the coincidence detection circuit detects the detection of predetermined frame synchronous data at the timing of the search instruction by the plurality of timing instruction circuits. A frame synchronization device comprising: a determination circuit that determines frame synchronization based on whether or not a frame is synchronized.