JPH01311706A - Multiplication circuit - Google Patents

Abstract

PURPOSE:To obtain a multiplication output with excellent linearity by converting 1st and 2nd input voltages into a current by a current voltage conversion circuit, converting one current into a voltage subject to logarithmic compression and applying the current and voltage signals in pairs to a differential amplifier. CONSTITUTION:A voltage current conversion circuit 5 comprising current mirror circuits 3, 4 converts the 1st input signal voltage e1 into currents I+i1, I-i1. Moreover, a voltage current conversion circuit 50 and transistors (TRs) Q56, Q59 convert the 2nd input signal voltage e2 into currents 1+i2, 1-i2. Current voltage conversion circuits 10, 20 convert the said currents I+i2, 1-i2 into voltages V+v2, V-v2 subject to logarithmic compression and they are applied to bases of differential amplifiers 1, 2 in pairs. As a result, currents 1+i3, I-i3 being a multiple of currents I+ or -i1, I+ or -i2, that is, signals multiplied with the 1st and 2nd input voltages e1, e2 are outputted to the collector of the differential amplifiers 1, 2.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a multiplication circuit.

[Summary of the invention]

This invention is a multiplication circuit in which two input signals are used as current inputs, and one input signal is logarithmically compressed and multiplied, thereby making it possible to obtain a multiplication output with good linearity at a low power supply voltage. It is.

[Conventional technology]

There are circuits shown in FIGS. 4 to 6 as multiplier circuits that can be used for frequency conversion, stereo reconstruction, etc.

In each of these multiplier circuits, a balanced input signal voltage e1+82 is supplied, and a balanced multiplier output current i3 is extracted.

[Problem to be solved by the invention]

However, in general, although the base voltage vs. collector current characteristic of a transistor is an exponential characteristic,
In the multiplication circuit shown in the figure, the signal voltages 131 and e2 are supplied as they are to the bases of the transistors. Therefore, in this multiplication circuit, the signal voltage 61 + 8
2 exceeds several mV to several tens of meters, linearity deteriorates.

In this regard, in the multiplication circuit shown in FIG. 5, negative feedback is applied to the input terminal e1 by the resistor R to improve linearity, and the rectangular wave is applied to the input terminal e2. Since the transistor to which the voltage e2 is supplied is completely controlled to turn on and off, the linearity of the output current i3 is improved.

However, in this multiplier circuit, since the input voltage e2 is a rectangular wave and contains many harmonic components, the output type fRI 3 also contains many high m-wave components, and the harmonic components are In order to remove this, a low-pass filter with good cutoff characteristics is required.

Furthermore, the multiplier circuit of FIG. 6 has improved linearity with respect to the input voltage e1 through negative feedback, and the input voltage e2 is logarithmically compressed before being supplied to the base of the transistor, so the output current The linearity of I3 is improved.

However, in this multiplication circuit, as shown by the broken line,
Since two transistors between the base and emitter and one between the collector and emitter are connected in series between the power supply line and the ground, the power supply voltage +Vcc is at least Vcc≧0.7 V x It must be 2 +0.2 v-1,6V. Therefore, this multiplication circuit cannot be used, for example, in a radio IC that operates on a single AA battery.

This invention attempts to solve the above problems.

[XII! [Failure to solve the problem]

Therefore, in the present invention, two input signals are used as current inputs, and one input signal is logarithmically compressed and multiplied.

[Effect]

Even if the dL source voltage is low, a multiplication output with good linearity can be obtained.

〔Example〕

In FIG. 1, transistor Q1. A differential amplifier (1) is configured by connecting the collector and emitter of a constant current source transistor Qc between the emitter of Q2 and the ground, and a transistor Q3.

A differential amplifier (2) is configured by connecting the collector and emitter of a constant current source transistor Q9 between the emitter of Q4 and the ground.

Further, the collectors of transistors Ql and Q3 are connected to each other, and the collectors of transistors Q2 and Q are connected to each other.

The collectors of the two are connected to each other to form a pair of output terminals.

Furthermore, current mirror circuits (31, (4)) are configured by transistors Qe and Qs, respectively, and
These current mirror circuits (3) and (4) constitute a voltage-current conversion circuit (5).

In other words, the base of transistor Qε is
The emitter of this transistor Q5 is grounded, and a common-mode amplifier (6) is connected between its collector and base to form a current mirror circuit (3) with the ground as a reference potential point. configured. and,
A resistor R1 is connected between the signal S1 of the first input signal voltage e1 and the collector of the transistor Q5, and a constant current source (8) is connected to the collector of the transistor Q5. A current I is output.

Also, the base of transistor Q9 is connected to transistor Q11.
The emitter of this transistor Q8 is grounded, and a common-mode amplifier (7) is connected between its collector and base to form a current mirror circuit (4) with the ground as a reference potential point. be done.

Then, a transistor Q7 is connected to the base of the transistor Qe.
The base of the transistor Q7 is connected to the collector of the transistor Q8, and its emitter is grounded.A constant current source (9) is connected to the collectors of the transistors Qv and Qs, and from this a current of 2 is connected.
I is output.

Further, the amplifier (11) and the transistor Qtt constitute a current-voltage conversion circuit (10) with logarithmic compression characteristics. That is, the output terminal of the amplifier (11) is connected to the base of the transistor ctti, the collector thereof is connected to the power supply terminal 'l'1, the emitter is connected to the inverting input terminal of the amplifier (11), and the amplifier (11) A bias voltage fi of several tens of mV is applied between the non-inverting input terminal of the
Vr is connected.

Further, the amplifier (21) and the transistor Q21 similarly constitute a current-voltage conversion circuit (20) with logarithmic compression characteristics.

Further, a voltage-current conversion circuit (50) is connected to the signal source S2 of the second input signal voltage e2. This conversion circuit (50
) has the same configuration as the conversion circuit (5), and the transistors Q 5g and Q ss correspond to the transistors Qe and Qs. The collectors and emitters of these transistors Q 6s and Q ss are respectively connected between the emitters of transistors Q 11 and Q 21 and ground.

Also, the base of transistor Q11 is connected to transistor Q1.
．． Q4 is connected to the base of transistor Q4.
The base of 2L is connected to the bases of transistors Q2 and Q3.

Note that the corresponding transistors have the same or similar characteristics.

FIG. 2 shows an example of the conversion circuit (10). That is, the emitter of transistor QLI is connected to the base of transistor QL2, the emitter of this transistor Q12 is connected to terminal 1'1, and between its collector and ground,
A constant current source Q14 is connected. Furthermore, transistor Q
The collector of transistor Q13 is connected to the base of transistor Q13, the collector of which is grounded, and its emitter is connected to terminal 'I'1 through resistor R11 and to the base of transistor Q11. Note that the terminal voltage of the resistor RLt is the voltage Vr. In addition, the conversion circuit (20) is also the conversion circuit (10)
It is configured in the same way as .

According to this configuration, since 100% voltage negative feedback is applied to the transistor Q5 by the amplifier (6), the output impedance of the transistor Q5 when looking at the transistor Q5 from the resistor R is sufficiently high. small,
It can be ignored compared to the value of resistor R1. Therefore, resistor R1 has iz = et /Rz ” (i)
A signal current 15 shown by flows, and the voltage e1 is linearly converted into a current 11.

And transistor Qs + Qc and amplifier (6)
constitutes a current mirror circuit (3) with the transistor Q5 as the input terminal, and the signal current 11 flowing through the resistor R1 and the direct current '11si from the constant current source (8).
Since the current (1) flows through the transistor Q6, a current (1+ir) flows through the collector of the transistor Q6.

Also, at this time, transistor Q7 is also transistor Qε
Since the bias condition is the same as that of , a current (1+i1) also flows from the constant current source (9) to the collector of the transistor Q7.

The output current of the constant current source (9) is a current of 2■, and since the transistors Q8, Q9 and the amplifier (9) constitute a current mirror circuit (4), a current of 2I is applied to the collector of the transistor Q8. A current (1-11), which is the difference between the current and the current (1+41), flows, and as a result, a current (l iz) flows through the collector of the transistor Q9.

That is, the differential amplifier (11, +21 constant current source transistors Qs, Qs have currents (1+kt), (1-tl) having a signal current ±11 linearly proportional to the input signal voltage e1 and a DC current l. ) flows.

Similarly, in the conversion circuit (50), the input signal voltage θ2 is applied to the transistors Qss and Q59.
Currents (1+12) and (1-12) having a signal current ±12 and a direct current 1 linearly proportional to flow.

Since this current (1+12) + (112) is also the emitter current of each transistor Q 111 Q 21, the current between the base and emitter of the transistor Q u + Q 21 is (1++2), (I i2),
A pair of voltages (V + V2) + (V-vt) which are logarithmically compressed are obtained as well as current-voltage conversion is performed. However, at this time, the transistor Q 11 ,
100% voltage negative feedback is applied to Q21 by the amplifiers (11,) and (12), and the amplifier (11).

Since voltage (Vcc-Vr) is supplied to (12), V = V cc -V r V2- <k'r/q)in ((1+i)/I)...
...(ii) becomes.

And this logarithmically compressed voltage (V+V2).

(V V2) is transistor Ql, Q4 and Q2
.

Q3 is supplied to each base of transistor Ql,
The collector currents of Q4, Q2, and Q3 are current (1+t
2) + (1'2).

At this time, transistors Ql, Q4 and Q2
, Q3's collector currents are equal to their emitter currents (1
+iz) and (l il), so the transistors Qx, Q3 and Q2, Q:
Each collector of l has a pair of balanced multiplier outputs f
R(1+i3) and (1-13) are obtained.

The currents (lfil) and (1±it) are obtained by linearly converting the input signal voltages e1 and e2 into voltage and current in the conversion circuits (51, (50)), as shown in equation (i). , the output current (signal portion) ±13 is the product output of the input signal voltage el, 62, and has excellent linearity compared to the input signal voltage θ1.e2.

In this case, if the amplitude of the current 12 is equal to the current I, the signal voltage v2 in equation (ii) is equal to the current 12
For the instantaneous value of, when 12=l...v2ζ18m Vi2=0
When...vt-O When L2-1...vt-〇〇This is a logarithmically compressed value, but this is an ideal value, and in reality, it depends on the circuit configuration. Above, when 12=-1, ""v# becomes 700mV, resulting in the characteristics shown in FIG. Therefore, the input signal voltage e2
In contrast, the signal current 12 can have a dynamic range in which its amplitude is approximately equal to the current I.

Also, the signal voltage v2 is larger than l1 when 12=1 compared to when there is no signal (when e2=Q, that is, when 12=0).
Since the voltage only increases to 3 mV, which is a high Hk value, the voltage Vr may be several tens of mV as described above. A voltage Vr is connected between the terminal 1'1 and the ground, and between the base and emitter of the transistor Q11 and the transistor Q
Since the 5G collector and emitter are simply connected in series, the power supply voltage Vcc is Vcc≧several tens of mV +o, 'y V +0.2 V''=
0.9V. Therefore, if this multiplier circuit is used in an IG that operates with one AA battery, even if the battery is exhausted and the voltage drops to about 60% of the rated voltage of 1.5V, This multiplication circuit can operate almost like a perch.

〔Effect of the invention〕

As described above, in the present invention, the first input signal voltage e1 is linearly converted into the signal current 11, and this current 11
is supplied as the emitter current of the differential amplifier (lb, (21), and the second input signal voltage e2 is supplied as the signal current i2
This current 12 is converted and logarithmically compressed into a voltage v2, and this voltage v2 is applied to a differential amplifier (11, (21
Since the differential amplifier 11 is supplied as the base voltage,
), (2), the multiplication output current i3 of the input signal voltage el+'32 can be obtained, and the output current i
3 has good linearity.

Moreover, when converting and logarithmically compressing the signal current i2 to the signal voltage v2, the conversion circuits (10) and (20) are
Transistor Qs, Q12 and negative feedback amplifier (1
1) and (12), the power supply voltage Vcc can be lowered.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram of an example of this invention, FIG. 2 is a connection diagram of a part of it, and FIGS. 3 to 6 are diagrams for explaining the same. (L), [2+ is a differential amplifier, (5), (50)
is a voltage-current conversion circuit, and (10) and (20) are current-voltage conversion circuits.

Claims (1)

[Claims] First and second differential amplifiers, a first voltage-current conversion circuit that linearly converts a first input signal voltage into a pair of first signal currents, and a second input signal current. It has a second voltage-current conversion circuit that linearly converts a signal voltage into a pair of second signal currents, a pair of transistors, and a pair of amplifiers that respectively provide negative feedback to the pair of transistors. , the bases of the first and second transistors constituting the first differential amplifier and the bases of the second and first transistors constituting the second differential amplifier are respectively connected to each other, Collectors of the first and second transistors of the first differential amplifier and collectors of the first and second transistors of the second differential amplifier are connected to each other, and The pair of first signal currents from the voltage-current conversion circuit are respectively supplied to the first and second differential amplifiers as currents of their constant current sources, and from the second voltage-current conversion circuit. The pair of second signal currents are respectively supplied to the emitters of the pair of transistors and converted into a pair of logarithmically compressed signal voltages, and the pair of signal voltages converted into current and voltage are converted into a pair of logarithmically compressed signal voltages. are respectively supplied to mutually connected bases of each of the first and second transistors of the first and second differential amplifiers, and A multiplication circuit in which an output current multiplied by the first and second input signal voltages is taken out from mutually connected collectors of the transistors.