JPH01311773A - Video signal processor - Google Patents

Abstract

PURPOSE:To superimpose the video signal of real time by constituting respective video signal data stored in a first memory and a second memory transmittable to a same bus at same speed by a bus driving device. CONSTITUTION:A continuous-inputted video signal VI is stored in a first memory 102 at real time after it is digitized with an A/D converter 3. On the other hand, when a video signal DI to superimpose is inputted to a controller 103, an applying signal is stored in a second memory 105 at a frame or field unit. A bus driving device 104 reads the data of the first memory 102 and the data of the second memory 105 at the same scanning timing to a same bus 106. Thus, not only the independent display of the video signal DI which is formed separately and has moving but also the superimposing to the video signal VI of real time can be executed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a video signal processing device that superimposes another image signal onto a continuous image signal such as a television signal and outputs the superimposed image signal.

[Conventional technology]

FIG. 4 shows a conventional video signal processing device, in which 1 is a line leading to a video signal (video signal) Vl including horizontal and vertical synchronizing signals and encoded color signals;
is a decoder that separates this video signal Vl into color signals R, G, and B; 3 is an analog-to-digital (hereinafter referred to as A/D) converter that converts the color signals R2B and G into digital signal format; and 4 is a digitizer. The color signals R', B',
A frame memory that stores G' in units of frames;
5 is an ink face for transferring data D of the frame memory 4 by direct memory access (hereinafter referred to as DMA), 6 is a computer (hereinafter referred to as CPU), and 7 is C
A (main) memory for storing programs and data of the PU 6, 8 a disk controller for storing data for the CPU 6, 9 a disk for storing data for the CPU 6, an IO
is a data input/output device for the CPU 6, 11 is a bus that connects the ink face 5 to disk 9, 12 is a program control channel that connects the interface 5 to disk 9, and 13 is a digital/analog ( D/A to be converted (hereinafter referred to as D/A)
A converter 14 is an encoder for the output of the D/A converter 13. Next, the operation will be explained with reference to the conceptual diagram in FIG. 5. First, the video signal 1 corresponding to the screen a in FIG.
, G, and B. Next, the color signals R, G, and B are A/D.
The converter 3 converts it into digital color signals R'', B', and G' 7, which are manually input to the frame memory 4 and displayed on one screen (
1 field or 1 frame) is stored. next,
Image signal data (E
EE) is sent to the frame memory 4 via the interface 5 and rewritten. Subsequently, the data (superimposed data) rewritten as described above according to instructions from the CPU 6 is outputted as an output video signal 0 via the D/A converter 13 and the encoder 14, as shown in the figure. An image as shown in screen C in FIG. 5 is displayed on a monitor that is not connected.

[Problem to be solved by the invention]

Since the conventional video signal processing device is configured as described above, it is possible to superimpose a still image stored in the memory 7 onto a video signal, but it is not possible to superimpose a real-time video. There was a problem in that it took about 11 seconds to transfer image signal data using the lotus 11 in the order of memory 7 → lotus 11 → interface 5 → frame memory 4. Incidentally, as an approximation technique, there is one shown in Japanese Patent Application No. 58-251834. This invention was made to solve the above-mentioned problems, and it superimposes a separately generated image signal on top of the input video signal in a moving state without impairing the real-time nature of the input video signal. An object of the present invention is to obtain a video signal processing device that can be image-imposed.

[Means to solve the problem]

The video signal processing device according to the present invention stores video signal data in a first memory in field units or frame units, while storing video signal data generated in a predetermined procedure in a second memory in field units or frame units. The data of the image signal from the second memory is sent to the same bus by a bus drive circuit at the same speed as the data of the image signal from the first memory.

[For use]

The bus drive circuit according to the present invention sends image data for superimposing onto the same bus at the same speed as data of a continuously inputted video signal, and controls the first memory and the second memory. A command is output to superimpose moving image data onto the video signal so that it can be displayed, or it can be displayed alone.

【Example】

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, ▪ is a line leading the video signal Vl, 2 is a decoder, and 3 is an A/D converter, which are the same as those shown in FIG. 101 is a thinning circuit that thins out A/D conversion output data; 102 is a first memory such as a frame memory that stores the thinned data in frame units or field units; 109 is a command for controlling the video signal Vl; A line leading the image signal DI for superimposing onto the video signal Vl, 103 a control device which receives this image signal DI and generates control commands and image signal data, 104 a control command and data of the image signal. bus 1
06 is the bus drive device, 105 is the bus drive device 1
A second memory such as a frame memory stores the image signal data from 04 in frame units or field units; 107 is a frame memory for transmitting data from the first memory 102 and the second memory 105; 108 is a frame memory; 'S1
The data on 07 is D/A converted and the analog video signal V
It is an output device that encodes into O. Next, the operation will be explained with reference to the conceptual diagrams and operational model diagrams of FIGS. 2 and 3. First, the continuously input video signal VI is decoded by the decoder 2 and separated into color signals R, G, and B, and then converted into digital signals by the A/D converter 3. Next, this digital signal is thinned out at regular intervals in a thinning circuit 101 and then stored in the first memory 102 . That is, a video signal as shown in screen d of FIG. 2 is stored in the first memory 102 in real time. On the other hand, when an image signal DI as shown in screen e in FIG.
It is sent to the lotus 106 along with the control signal. Further, the data of the image signal sent out in this way is stored in the second memory 1.
05 in frame units or field units. The first memory 102 and the second memory 105 output each data at the same scanning timing (speed), and as shown in the operation model diagram of FIG. 3, the second memory IJ1
The determining unit 113 determines whether or not there is a transparent color portion P on the screen e of the image data output by
5 is output to the bus 107. That is, during scanning, if the image signal data in the second memory 105 includes the transparent color portion P, the output of this image signal data is cut and the video signal data from the first memory 102 is transmitted. If the transparent color portion P is not included in the data of the image signal, the first memory 1
02 is cut, and the image signal data in the second memory 105 is output to the bus 107. As a result, the video signal 0 corresponding to the screen f shown in FIG. 2 is outputted through the output device 108, and as a result of this output, a video as shown in the screen r is displayed on a monitor (not shown). In this case, in order to superimpose the image signal DI on the video signal Vl as moving image data, the image data in the second memory 105 is transferred to the bus drive circuit 104.
This allows updates to be made 60 times per second (for one frame). Note that if a multiplexed command for processing the video signal data by the thinning circuit 101 is sent to the bus 106, the first frame memory 102 can store the reduced or inverted video signal data. Wear.

【Effect of the invention】

As described above, according to the present invention, the video signal stored in the first memory and the video signal stored in the second memory are transferred to the same bus at the same speed by the bus driving device. Since it is configured to transmit data, it is possible not only to display the data of the above-mentioned moving video signal created separately, but also to perform superimposition on the real-time video signal together with high-speed transfer of that data. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a video signal processing device according to an embodiment of the present invention, FIG. 2 is a conceptual diagram explaining the superimpose operation based on FIG. 1, and FIG. FIG. 4 is a block connection diagram showing a conventional video signal processing apparatus, and FIG. 5 is a conceptual diagram illustrating the superimpose operation based on FIG. 4. Vl is a video signal, DI is an image signal, 102 is a first memory, 104 is a bus driver, 105 is a second memory, 1
06 is a bus. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation No. 22
Figure 3 Figure 5 - Car U

Claims (1)

[Claims] In a video signal processing device that processes continuous video signal data and image signal data generated according to a predetermined procedure into one video signal and outputs the same, the video signal data is divided into fields or frames. a first memory that stores the image signal data in units of fields or frames, and a second memory that stores the data of the image signal in units of fields or frames; A video signal processing device comprising a bus drive device that sends image signal data stored in the memory of the bus to a bus.