JPH01312838A - Formation of insulating film - Google Patents

Formation of insulating film

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Publication number
JPH01312838A
JPH01312838A JP14432788A JP14432788A JPH01312838A JP H01312838 A JPH01312838 A JP H01312838A JP 14432788 A JP14432788 A JP 14432788A JP 14432788 A JP14432788 A JP 14432788A JP H01312838 A JPH01312838 A JP H01312838A
Authority
JP
Japan
Prior art keywords
oxide film
film
silicon
insulating film
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14432788A
Other languages
Japanese (ja)
Inventor
Kiyoteru Kobayashi
清輝 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14432788A priority Critical patent/JPH01312838A/en
Publication of JPH01312838A publication Critical patent/JPH01312838A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To decrease density of generated trap level and to improve durability of an insulating film by forming an oxide film on a nitride film by CVD method. CONSTITUTION:After a silicon oxide film 2 is grown on a main surface of a single crystalline silicon substrate 1, a silicon nitride film 3 is selectively formed on the silicon oxide film 2 and an isolated oxide film is selectively formed. After the silicon oxide film 2 and the silicon nitride film 3 are eliminated, the silicon nitride film 3 is formed by vacuum CVD method. A natural oxide film 6 is also formed at the same time. Then a top oxide film 9 which consists of a silicon oxide film is formed on a silicon nitride 5 by vacuum CVD method. Accordingly to this constitution, density of trap level generated during the process is extremely small and does not have a detrimental effect on a multilayer insulating film, thus forming a durable multilayer insulating film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体基板上に窒化膜と酸化膜とからなる多
層絶縁膜を形成する絶縁膜形成方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulating film forming method for forming a multilayer insulating film consisting of a nitride film and an oxide film on a semiconductor substrate.

〔従来の技術〕[Conventional technology]

第3図(a)〜(e)は各々窒化膜と酸化膜とからなる
多層絶縁膜を有する従来のMISキャパシタの製造方法
を示す断面図である。以下、同図を参照しつつ製造方法
を説明する。
FIGS. 3(a) to 3(e) are cross-sectional views showing a method of manufacturing a conventional MIS capacitor having a multilayer insulating film made of a nitride film and an oxide film, respectively. The manufacturing method will be described below with reference to the same figure.

まず、単結晶シリコン基板1の主面上にパッド酸化膜と
なるシリコン酸化膜2を成長させた後、このシリコン酸
化膜2上にシリコン窒化膜3を同図(a)に示すように
、選択的に形成する。
First, a silicon oxide film 2 that will become a pad oxide film is grown on the main surface of a single-crystal silicon substrate 1, and then a silicon nitride film 3 is selectively grown on this silicon oxide film 2, as shown in FIG. to form.

次に、シリコン基板1を熱酸化することにより、同図(
b)に示すように、分m酸化膜4を選択的に形成する。
Next, by thermally oxidizing the silicon substrate 1, the silicon substrate 1 is thermally oxidized (
As shown in b), an oxide film 4 is selectively formed.

そして、シリコン酸化膜2とシリコン窒化膜3を除去し
た後、例えば減圧CVD法により膜厚100人のシリコ
ン窒化g!!5を形成する。このとき、シリコン酸化膜
2除去後シリコン窒化膜5堆積までの間に空気中の酸素
がシリコン基板1−[に付着しているため、同図(C)
に示すように、自然酸化FJ6が同時に形成される。
After removing the silicon oxide film 2 and the silicon nitride film 3, for example, the silicon nitride film 3 is formed into a film with a thickness of 100 g! by low pressure CVD method. ! form 5. At this time, since oxygen in the air adheres to the silicon substrate 1-[ after the removal of the silicon oxide film 2 and before the deposition of the silicon nitride film 5, as shown in FIG.
As shown in , naturally oxidized FJ6 is formed at the same time.

次に、シリコン窒化膜5を、900℃程度の温度による
熱酸化法により酸化し、30人程度のシリコン酸化膜で
あるトップ酸化膜7を、同図(d)に示すように形成す
る。
Next, the silicon nitride film 5 is oxidized by a thermal oxidation method at a temperature of about 900° C. to form a top oxide film 7, which is a silicon oxide film of about 30% thickness, as shown in FIG. 3(d).

次に、トップ酸化膜7上にリンをドープしたポリシリコ
ン膜を成長させ、パターン形成することで゛、同図(c
lに示すように、ゲート電極8を形成する。このように
して、トップ酸化膜7.シリコン窒化膜5および自然酸
化膜6からなる多層絶縁膜を有するMISキセバシタを
製造できる。このように絶縁膜を多層にすることで、絶
縁膜の耐久性が良くなり、MIS型半導体装冒の信頼性
が向上覆る。
Next, a polysilicon film doped with phosphorus is grown on the top oxide film 7 and patterned.
A gate electrode 8 is formed as shown in FIG. In this way, the top oxide film 7. A MIS transistor having a multilayer insulating film consisting of a silicon nitride film 5 and a natural oxide film 6 can be manufactured. By forming the insulating film into multiple layers in this manner, the durability of the insulating film is improved, and the reliability of the MIS type semiconductor device is improved.

(発明が解決しようとする課題) 窒化膜と酸化膜による多層絶縁膜の形成は、従来、以上
のように行われており、シリコン窒化膜5を熱酸化する
ことで、シリコン窒化膜5上にトップ酸化膜7を形成し
でいた。このため、トップ酸化膜7形成中にトップ酸化
膜7とシリコン窒化膜5との界面に、密度の大きいトラ
ップ単位が発生する。その結梁、このトラップ単位にt
yr獲された電荷によりトップ酸化膜7またはシリコン
窒化膜5内に電界が生じ、多層絶縁膜としての耐久性に
支障を来たし、この多層絶縁膜により構成されるMIS
キャパシタ等のMIS型半導体装置の寿命に悪影響を与
えるという問題点があった。
(Problem to be Solved by the Invention) Formation of a multilayer insulating film using a nitride film and an oxide film has conventionally been performed as described above. The top oxide film 7 has been formed. Therefore, during the formation of the top oxide film 7, trap units with a high density are generated at the interface between the top oxide film 7 and the silicon nitride film 5. The connecting beam is t for this trap unit.
The captured charge generates an electric field in the top oxide film 7 or silicon nitride film 5, which impedes the durability of the multilayer insulating film.
There is a problem in that it adversely affects the lifespan of MIS type semiconductor devices such as capacitors.

この発明は−1−記のJ、うな問題点を解決するために
なされたもので、窒化膜と酸化膜とからなり、かつ耐久
性が高い多層絶縁膜の形成方法を促供することを目的と
する。
This invention was made in order to solve the problems mentioned in J of -1-, and its purpose is to promote a method for forming a highly durable multilayer insulating film consisting of a nitride film and an oxide film. do.

〔課題を解決するための手段〕[Means to solve the problem]

この発明にかかる絶縁膜の形成方法は、窒化膜と酸化膜
とにより構成される多層絶縁膜を形成する方法であって
、半導体基板上に前記窒化膜を形成する工程と、前記窒
化膜上にCVD法により前記酸化膜を形成する工程とを
含んでいる。
The method for forming an insulating film according to the present invention is a method for forming a multilayer insulating film composed of a nitride film and an oxide film, and includes a step of forming the nitride film on a semiconductor substrate, and a step of forming the nitride film on the nitride film. The method includes a step of forming the oxide film by a CVD method.

〔作用〕[Effect]

この発明においては窒化膜上にCVD法により酸化膜を
形成するため、この工程により発生するトラップ準位の
密度は小さい。
In this invention, since the oxide film is formed on the nitride film by the CVD method, the density of trap levels generated by this process is small.

〔実1M 1A) 第1図(a)〜(e)は各々この発明の一実施例である
窒化膜、酸化膜からなる多層絶縁膜を有するMISキャ
パシタの製造方法を示す断面図である。
[Real 1M 1A] FIGS. 1A to 1E are cross-sectional views showing a method of manufacturing an MIS capacitor having a multilayer insulating film made of a nitride film and an oxide film, which is an embodiment of the present invention.

以下、同図を参照しつつ、製造方法を説明する。Hereinafter, the manufacturing method will be explained with reference to the same figure.

まず、単結晶シリコン基板1の主面上にパッド酸化膜と
なるシリコン酸化膜2を成長させた後、このシリコン酸
化膜2上にシリコン窒化膜3を同図(a)に示ゴように
、選択的に形成する。
First, a silicon oxide film 2 that will become a pad oxide film is grown on the main surface of a single crystal silicon substrate 1, and then a silicon nitride film 3 is grown on this silicon oxide film 2 as shown in FIG. Form selectively.

次に、シリコン基板1を熱酸化することにより、同図(
b)に示すように、分1i11F!化膜4を選択的に形
成する。
Next, by thermally oxidizing the silicon substrate 1, the silicon substrate 1 is thermally oxidized (
As shown in b), minute 1i11F! A chemical film 4 is selectively formed.

そして、シリコン酸化膜2とシリコン窒化膜3を除去し
た後、例えば減圧CV D法により膜厚100人のシリ
コン窒化膜5を形成する。このとき、シリコン酸化g!
2除去後シリコン窒化膜5堆積までの間に空気中の酸素
がシリコン基板1上に付着しているため、同図(C)に
示すように、自然酸化膜6が同時に形成される。
Then, after removing the silicon oxide film 2 and the silicon nitride film 3, a silicon nitride film 5 with a thickness of 100 mm is formed by, for example, a low pressure CVD method. At this time, silicon oxidation g!
Since oxygen in the air adheres to the silicon substrate 1 after the removal of the silicon nitride film 2 and before the deposition of the silicon nitride film 5, a natural oxide film 6 is simultaneously formed as shown in FIG.

次に、シリコン窒化膜5上に減圧CVD法により約30
人のシリコン酸化膜からなるトップ酸化膜9を形成する
。30人程度の薄さのi−ツブ酸化膜9も技術の遊歩に
伴い、減圧CVD法により充分正確に形成することがで
きる。
Next, about 30% of
A top oxide film 9 made of a silicon oxide film is formed. With advances in technology, the i-tube oxide film 9 with a thickness of about 30 mm can be formed with sufficient accuracy by low pressure CVD.

次に、トップ酸化膜9上にリンをドープしたポリシリコ
ン膜を成長させ、バクーン形成することで、同図(e)
に示すように、ゲート電極8を形成する。このようにし
て、トップ酸化膜9.シリコン窒化F!5.自然酸化模
6とによる多層絶縁膜を有するMISキt1バシタを製
造できる。
Next, a polysilicon film doped with phosphorus is grown on the top oxide film 9, and by forming a vacuum, as shown in FIG.
A gate electrode 8 is formed as shown in FIG. In this way, the top oxide film 9. Silicon nitride F! 5. It is possible to manufacture a MIS kit t1 vacitor having a multilayer insulating film made of natural oxide pattern 6.

このように、トップ酸化l119を減圧CVD法により
形成することで、トップ酸化膜9形成時にトップ酸化膜
9とシリコン窒化膜7との界面に生じる1〜ラップ密度
はかなり小さくなる。従ってトラップ準位によりトップ
酸化膜9およびシリコン窒化膜5中に捕獲される電荷量
は非常に少ない。このため、トップ酸化F!9あるいは
シリコン窒化膜5中に発生する電界により多層絶縁膜に
支障を来たすことがなく、この多層絶縁膜により構成さ
れるMrSキャパシタ等のMIS型半導体装置の寿命に
悪影響を与えない。
By forming the top oxide l119 by the low pressure CVD method in this manner, the 1-wrap density generated at the interface between the top oxide film 9 and the silicon nitride film 7 when the top oxide film 9 is formed becomes considerably small. Therefore, the amount of charge trapped in top oxide film 9 and silicon nitride film 5 by trap levels is very small. For this reason, top oxidation F! The electric field generated in 9 or the silicon nitride film 5 does not affect the multilayer insulating film, and does not adversely affect the life of MIS type semiconductor devices such as MrS capacitors formed of this multilayer insulating film.

第2図は、この発明の実施例である第1図で示した製造
方法で製造されたMISキャパシタと従来例である第3
図で示した製造方法で製造されたMISキャパシタの寿
命をT OD B (Time Dependent 
Dielcctic Breakdown)法によッテ
測定した実験結果を示したグラフである。なお、このと
きの双方のMISキャパシタの活性領域面積は400μ
m2であり、実験は双方の〜118キャパシタのシリコ
ン基板1を接地電位に保ら、ゲート電極8を負または正
の電位とすることで、これらの間に負の高電界(−8〜
−10M V / cjI)あるいは正の高電界(12
−14MV/I:Jl)を生じさせ、絶縁破壊に至るま
での時間を測定覆ることで行った。
FIG. 2 shows an MIS capacitor manufactured by the manufacturing method shown in FIG. 1, which is an embodiment of the present invention, and a third MIS capacitor, which is a conventional example.
The lifespan of the MIS capacitor manufactured using the manufacturing method shown in the figure is TOD B (Time Dependent
1 is a graph showing experimental results measured using the Dielcctic Breakdown method. Note that the active region area of both MIS capacitors at this time is 400μ.
m2, and the experiment was conducted by keeping the silicon substrates 1 of both ~118 capacitors at ground potential and setting the gate electrodes 8 at negative or positive potential, thereby creating a negative high electric field (-8 ~
-10M V/cjI) or positive high electric field (12
-14MV/I:Jl) and measured the time until dielectric breakdown occurred.

第2図において、実線e示した!1.12が従来の絶縁
膜形成方法で製造されたM I S t=ヤバシタの寿
命を示し、11が負の高電界、12が正の高電界が基板
1とゲート111i極8との間に生成された場合である
。一方、破線で示した13.14がこの発明の実施例で
示した絶縁膜形成方法で製造されたMrSキャパシタの
寿命を示し、I3が負の高電界、i4が正の高電界が基
板1とゲート電極8との間に生成された場合である。な
J3、Eaf、はゲート電極8に印加した電圧を示し、
寿命は規格化値である。
In Figure 2, the solid line e! 1.12 indicates the life of M I S t = Yabashita manufactured by the conventional insulating film forming method, 11 indicates a negative high electric field, and 12 indicates a positive high electric field between the substrate 1 and the gate 111i electrode 8. This is the case when it is generated. On the other hand, 13.14 shown by the broken line indicates the life of the MrS capacitor manufactured by the insulating film forming method shown in the example of the present invention, where I3 is a negative high electric field and i4 is a positive high electric field. This is a case in which it is generated between the gate electrode 8 and the gate electrode 8. J3 and Eaf indicate the voltage applied to the gate electrode 8,
Lifespan is a normalized value.

同図に示すように、ゲート電極8に印加される−を界の
1.0にかかわらず、本実施例Cは従来例よりも寿命が
延び、信頼性が向上1./ Tいることがわかる。
As shown in the figure, regardless of the - field applied to the gate electrode 8, which is 1.0, the life of this embodiment C is longer than that of the conventional example, and the reliability is improved.1. / I can see that there is a T.

なお、この実施例では、シリコン窒化膜5上に形成され
るトップ酸化膜9を減圧CVD法で・行った場合を示し
たが、常圧CVD法簀の他のCVD法であっても、この
発明を適用することができ、同様の効果を秦ケる。
Although this example shows the case where the top oxide film 9 formed on the silicon nitride film 5 is formed by low pressure CVD, this method may also be applied to other CVD methods such as atmospheric pressure CVD. The invention can be applied to achieve similar effects.

〔発明の効果〕〔Effect of the invention〕

以F説明したように、この発明によれば、窒化膜上にC
V D法で酸化膜を形成することで多層絶縁膜を形成す
るIζめ、この工程中に発生するトラップ準位の密度は
非常に小さく、多層絶縁膜に悪影響を与えイ【い。従っ
て、より耐久性のある多層絶縁膜を形成でさる効果があ
る。
As explained below, according to the present invention, carbon is deposited on the nitride film.
Since a multilayer insulating film is formed by forming an oxide film using the VD method, the density of trap levels generated during this process is very small and does not adversely affect the multilayer insulating film. Therefore, it is possible to form a more durable multilayer insulating film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は各々この発明の一実施例によっ
て窒化膜と酸化膜とからなる多層絶縁膜をイj−するM
ISキャパシタを製造する方法を示す断面図、第2図は
第1図と第3図で示した製造方法で製造されたM I 
S−#セパシタの丁DDB測定結果を示すグラフ、第3
図(a)〜(e)は各々窒化膜と酸化膜とからなる多層
絶縁膜を有するMISキャパシタの従来の製造方法を示
す断面図である。 図において、1はシリコン基板、5はシリコン窒化膜、
9は減圧CVD法により形成されたシリコン酸化膜であ
る。 なお、各図中同一符号は同一または相当部分を示す。 代理人    大  岩  増  雄 第1図 (a))、 1              1.1=ニーr 一−−−−−−−、ノーーゝ−−−−−1−−−1−−
−−−−−−−帆−−−1−や−−24第1図 q 二一一一一一一一」 1 : >1ノコ〉基、27に 5:シリコ〉窒化m詔 9−ヌ人ノモCVD士2文°l二エリY′/ρXコ4T
ニシリコンn2イこ縦笛 2 図 Eeff  (MV/cm) 第30 :1″ 2〜       −−−−一一一−リ1 −−   
  、−一一一一〜−一」層−一−−−−−−〜へヘー
−−−−−一一一ニ第3図 手続補正書(自発) 昭和  年  月  日
FIGS. 1(a) to 1(e) each illustrate a multilayer insulating film made of a nitride film and an oxide film according to an embodiment of the present invention.
A cross-sectional view showing a method of manufacturing an IS capacitor, FIG.
Graph showing the DDB measurement results of S-# separator, 3rd
Figures (a) to (e) are cross-sectional views showing a conventional manufacturing method of a MIS capacitor having a multilayer insulating film made of a nitride film and an oxide film, respectively. In the figure, 1 is a silicon substrate, 5 is a silicon nitride film,
9 is a silicon oxide film formed by a low pressure CVD method. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo OiwaFigure 1 (a))
----------Sail---1-Ya--24 Figure 1 q 2111111''1:>1> group, 27 to 5:silico>nitriding m edict 9-nu Hitinomo CVD engineer 2 sentences °l 2 Eli Y'/ρXko 4T
Nisilicon n2 Iko vertical flute 2 Figure Eeff (MV/cm) 30th: 1″ 2~ ----111-li1 ---
, -1111~-1'' Layer 1---------~hehe-----1112 Figure 3 procedural amendment (voluntary) Showa year month day

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上に窒化膜と酸化膜とにより構成され
る多層絶縁膜を形成する方法であつて、前記半導体基板
上に前記窒化膜を形成する工程と、 前記窒化膜上にCVD法により前記酸化膜を形成する工
程とを含む絶縁膜の形成方法。
(1) A method for forming a multilayer insulating film composed of a nitride film and an oxide film on a semiconductor substrate, the method comprising: forming the nitride film on the semiconductor substrate; and forming the nitride film on the nitride film by a CVD method. A method for forming an insulating film, including the step of forming the oxide film.
JP14432788A 1988-06-10 1988-06-10 Formation of insulating film Pending JPH01312838A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14432788A JPH01312838A (en) 1988-06-10 1988-06-10 Formation of insulating film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14432788A JPH01312838A (en) 1988-06-10 1988-06-10 Formation of insulating film

Publications (1)

Publication Number Publication Date
JPH01312838A true JPH01312838A (en) 1989-12-18

Family

ID=15359531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14432788A Pending JPH01312838A (en) 1988-06-10 1988-06-10 Formation of insulating film

Country Status (1)

Country Link
JP (1) JPH01312838A (en)

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