JPH0131304B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor integrated circuits, particularly to increasing the density of logic integrated circuits.

In recent integrated circuits, there is a demand for high speed and high density for large scale integration. In order to achieve high speed, bipolar integrated circuits
ECL has been adopted. While TTL has slow switching speeds due to the cumulative effects of using transistors in saturation, ECL speeds up switching by passing a constant current through unsaturated transistors.

This ECL circuit is shown in FIG. 1, and its operation will be explained. When the terminal V _Read becomes equal to or higher than the predetermined potential, the input voltage V _io of terminal 3 and the comparison voltage V _REF of terminal 4
When V _io is higher than V _REF , Q ₁
is ON, Q ₂ is OFF, current flows to R ₁ , and point 1
The potential of becomes lower. Conversely, no current flows through R ₂ and the potential at point 2 becomes high. The signals at points 1 and 2 become inputs to the next ECL, forming a logic circuit.

FIG. 2 shows an integrated circuit of transistor groups Q ₁ , Q ₂ , and Q ₃ of the ECL circuit in FIG. 1. FIG. 2a shows a plan view thereof, and FIG. 2b shows a sectional view taken along the line -' in FIG. 2a. The electrode wiring numbers 1 to 7 in FIG. 2a are equivalent to the portions numbered 1 to 7 in the circuit diagram of FIG. In FIG. 2b, 11 is a p-type semiconductor substrate, 12a and 12b are
The n ⁺ buried layer has the role of lowering the collector resistance.
13a and 13b are collector regions made of n-type epitaxial layers, and the electrodes of these parts are taken out from the wirings 1 and 2 in FIG. 2a, and resistors R ₁ and R ₂
connected to. 14a and 14b are p-type base regions, the electrodes of which are taken out from the wirings 3 and 4 in FIG. 2a, and are connected to the input signal voltage,
A comparison voltage is applied. 15a and 15b are n-type emitter regions, which are connected through the electrode 5 and to the collector of the transistor _Q3 .
16 is an insulating oxide film, 17 is a transistor Q ₁ , Q ₂
and other elements.

As mentioned earlier, the integrated circuit configured as described above has the advantage that the speed can be increased by passing a constant current through the unsaturated transistor. However, in actual logic circuits (especially recent logic circuits), the logic becomes complex and highly integrated, resulting in a very large area. Therefore, problems regarding yield and variation arise. Further, in FIG. 2b, contact is made with the metal wiring 5 from the emitter regions 15a and 15b. In this case, contact resistance is created between the Si and the metal. At this time, if the contact window is very small, such as about 3 μm square, the contact resistance becomes larger and its variation occurs, resulting in a difference in V _BE between the transistors Q ₁ and Q ₂ .

The present invention was made in view of the above drawbacks, and the collectors of transistors Q ₁ and Q ₂ are formed inside one island, and the emitters of Q ₁ and Q ₂ and the collector of Q ₃ are formed with an n-type epitaxial layer. The feature is that the area is reduced by bonding through an n-type buried layer.

An embodiment of the integrated circuit according to the present invention will be described below with reference to FIG. Figure 3a is a plan view;
Figure b shows a sectional view taken along line X-X' in a. Wirings 1-4, 6, and 7 are the same as those 1-4, 6, and 7 in FIG. In FIG. 3b, 21 is a p-type semiconductor substrate, and 22 is an n-type epitaxial layer formed on the p-type substrate 21. In FIG. This n-type epitaxial layer 22 is the emitter of transistors Q ₁ and Q ₂ as well as the collector of transistor Q ₃ .
Reference numeral 23 denotes an n ⁺ buried layer for lowering the collector resistance of the transistor Q ₃ as well as the connection resistance between the emitter of the transistor Q ₁ and the collector of the transistor Q ₃ and between the emitter of the transistor Q ₂ and the transistor Q ₃ . 24a, 24b, 24
c is a p-type region, and transistors Q ₁ , Q ₃ ,
This is the base area of _Q2 . 25 is an n-type emitter region, which is the emitter region of transistor _Q3 . 26 and 27 are n-type collector regions, which are the collector regions of transistors Q ₁ and Q ₂ , respectively. 28
2 is an insulating oxide film, and 29 is a p-type isolation region for isolation from other elements.

In this way, a circuit is formed and the electrodes 1 and 2 are
By connecting resistors R ₁ , R ₂ , and R ₃ to and 7,
An ECL circuit as shown in FIG. 1 is formed. The operation is as described above, by applying a predetermined potential to V _Read , V _io and V _REF are compared, and the next ECL is output at outputs 1 and 2.
It sends a signal to

In the integrated circuit of the present invention described above, (1) there is no need to wire the emitters of transistors Q ₁ and Q ₂ and the electrode of transistor Q ₃ ;

(2) Transistors Q ₁ , Q ₂ and transistor Q ₃
There is no need to separate areas in between.

Therefore, it is possible to reduce the area and increase the density. Now, the minimum dimensions are 3 μm for the contact, 1.5 μm for the margin between the n-type region in the base region and the contact.
Margin between base region and contact 2μm, margin between base and isolation region 6μm, width of isolation region
Assuming 4 μm, in the case of Figure 1 it is 2807 (μm) ² ,
In this example, it is 1764 (μm) ² and the area is approximately 63%.
This made it possible to achieve higher density.

Furthermore, in the present invention, (3) Since the electrodes are not taken out from the emitters of transistors Q ₁ and Q ₂ ,
There is no difference in V _BE .

(4) Transistors do not require separation and diffusion.
Q ₁ and Q ₂ can be formed close to each other, resulting in less variation due to diffusion.

It has this feature. Note that the emitter resistance becomes large due to the use of an epitaxial layer, but this can be compensated for by adjusting the circuit design.

Also, by changing the resistance R ₃ , the base of Q ₃ can be changed.
Since the emitter current of _Q3 can be changed by changing the emitter voltage, the necessary current can be passed to the parts that require speed, and a small current can be passed to the parts that do not require much speed. Therefore, it becomes possible to realize a highly integrated ECL LSI with low power consumption.

Next, another embodiment according to the present invention is shown in FIG. 1-4, 6, 7 and 21-2 in Figure 4
8 is the same as in FIG. 30a and 30b are in the n-type epitaxial layer 22 and are in the transistor
This is the n ⁺ emitter region of the transistors Q ₁ and _{Q 2} formed under the base regions 24 a and 24 c of Q 1 and Q ₂ .

This embodiment has the following features in addition to the features of the embodiment shown in FIG.

(6) Since the emitters are highly concentrated in transistors Q ₁ and Q ₂ , the emitter injection efficiency increases (h _FE increases).

(7) The emitter resistance of transistors Q ₁ and Q ₂ decreases.

As described above, according to the present invention, it is possible to obtain a high-density integrated circuit with no variation in contact resistance and little variation in diffusion, as well as high precision and high yield, which is of great industrial value.

[Brief explanation of drawings]

Figure 1 is the ECL circuit diagram, Figure 2 a is the conventional ECL
FIG. 3B is a plan view of the main part of the circuit; FIG.
A plan view of the main part of the ECL circuit, FIG. 4B is a sectional view taken along the line X-X' of FIG.
A plan view of the main part of the ECL circuit, FIG. 1-4, 6, 7... Electrode wiring, 21... P-type semiconductor substrate, 22... N-type epitaxial layer, 23
...n ⁺ buried layer, 24a, b, c...p type base region, 25...n type emitter region, 26, 27...
...n type collector region, 30a,b...n ⁺ emitter region.

Claims (1)

[Claims] 1. An island region of one conductivity type formed on a substrate of the other conductivity type, and first, second, and third regions of one conductivity type formed separately on the upper surface of this island region. , having fourth, fifth, and sixth regions of the other conductivity type formed on the upper surface of the first, second, and third regions, respectively, the fourth region, the first region, and the third region. a first transistor in which the island region serves as a collector region, a base region, and an emitter region; a second transistor in which the fifth region, the second region, and the island region serve as a collector region, a base region, and an emitter region, respectively; ,
A third transistor is formed in which the sixth region, the third region, and the island region serve as an emitter region, a base region, and a collector region, respectively, and the collector region of the third transistor and the first and second
emitter regions of the transistors are electrically connected through the island region, and electrodes from base regions of each of the first, second, and third transistors and collector regions of each of the first and second transistors. A semiconductor integrated circuit characterized in that contact regions for extraction are formed on the surface of the substrate. 2. The semiconductor integrated circuit according to claim 1, further comprising a high concentration region of the other conductivity type in the island region below the first, second, and third regions. 3. Claim 2, characterized in that the high concentration region is formed to reach the first and second regions.
The semiconductor integrated circuit described in .