JPH0131310B2 - - Google Patents

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Publication number
JPH0131310B2
JPH0131310B2 JP4244778A JP4244778A JPH0131310B2 JP H0131310 B2 JPH0131310 B2 JP H0131310B2 JP 4244778 A JP4244778 A JP 4244778A JP 4244778 A JP4244778 A JP 4244778A JP H0131310 B2 JPH0131310 B2 JP H0131310B2
Authority
JP
Japan
Prior art keywords
layer
electrode
gaas
ohmic
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4244778A
Other languages
Japanese (ja)
Other versions
JPS54134558A (en
Inventor
Keiichi Oohata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP4244778A priority Critical patent/JPS54134558A/en
Publication of JPS54134558A publication Critical patent/JPS54134558A/en
Publication of JPH0131310B2 publication Critical patent/JPH0131310B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 本発明は耐熱性の優れた、特に保管および動作
許容温度の高い−族化合物半導体装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a - group compound semiconductor device which has excellent heat resistance, and in particular has a high allowable storage and operation temperature.

ガンダイオード、インバツトダイオード、ミク
サダイオード電界効果トランジスタ等n型GaAs
半導体を用いた半導体装置は、少くとも一つ以上
のオーム性電極を備え、或いは該オーム性電極と
その他シヨツトキ障壁電極等とを備えている。こ
こで従来のオーム性電極は、比較的低キヤリア密
度のn型GaAsに対しても、容易に低接触抵抗の
オーム性接触が得られるところから、通常Au−
Ge、Au−Su、Ag−In−Ge等のIb族元素を主成
分として、n型不純物として、GeあるいはSnを
含有する材料をGaAsと熱処理合金化させること
によつて得られている。また通常、さらに該合金
化層上に、配線抵抗を減じ、ボンデイングを容易
にするために、第2層としてAu層が設けられる。
しかしながら、このようなオーム性電極を具備す
る従来のn型GaAs半導体からなる半導体装置
は、Siトランジスタに比較して、耐熱性が劣り特
に許容温度の低い欠点を有していた。この理由
は、例えばAu−Ge等のAuを主成分とする電極
について考えてみると、オーム性接触を得るため
の熱処理合金化によつて、AuはGaAs中のGaと
作用し、Au−Ga合金を形成する。この場合完全
に反応させれば、Au−Gaの共晶に近いものが生
成し、これは350℃付近の比較的低温で融解する。
すなわち、Auを主成分とするオーム性電極は、
AuがGaAsと400℃程度の低温で反応すること、
および反応生成物の融解点が低温度であるためで
ある。また、Ag−In−Geを用いた場合には、第
2層のAuが低温で容易に拡散、Agと固溶し、
AuがGaAs界面まで達するため、状況はAuを主
成分とする電極と同様となりこれらのオーム性電
極を備えた従来のn型GaAs半導体からなる半導
体装置の最高許容温度は、たかだか400℃であり
耐熱性に乏しいと云う欠点があつた。
n-type GaAs such as Gunn diodes, imbat diodes, mixer diodes, field effect transistors, etc.
A semiconductor device using a semiconductor includes at least one ohmic electrode, or the ohmic electrode and another shot barrier electrode. Here, conventional ohmic electrodes are usually made of Au--N-type GaAs, which has a relatively low carrier density, because ohmic contact with low contact resistance can be easily obtained.
It is obtained by thermally alloying a material containing Ge or Sn as an n-type impurity with GaAs as a main component, which is mainly composed of Ib group elements such as Ge, Au-Su, and Ag-In-Ge. Further, typically, an Au layer is further provided as a second layer on the alloyed layer in order to reduce wiring resistance and facilitate bonding.
However, conventional semiconductor devices made of n-type GaAs semiconductors equipped with such ohmic electrodes have the drawback of inferior heat resistance and particularly low allowable temperature compared to Si transistors. The reason for this is, for example, when considering an electrode whose main component is Au, such as Au-Ge, during heat treatment alloying to obtain ohmic contact, Au interacts with Ga in GaAs, and the Au-Ga Forms an alloy. In this case, if the reaction is complete, something close to an Au-Ga eutectic will be produced, which will melt at a relatively low temperature of around 350°C.
In other words, the ohmic electrode whose main component is Au,
Au reacts with GaAs at a low temperature of about 400℃,
This is because the melting point of the reaction product is low. In addition, when using Ag-In-Ge, the second layer of Au easily diffuses at low temperatures and forms a solid solution with Ag.
Since Au reaches the GaAs interface, the situation is similar to that of electrodes whose main component is Au, and the maximum allowable temperature of conventional semiconductor devices made of n-type GaAs semiconductors equipped with these ohmic electrodes is at most 400°C, making them heat resistant. He had the disadvantage of being lacking in sexuality.

本発明の目的は、前記従来の欠点を除去せしめ
低許容温度を大幅に引上げた高耐熱性の半導体装
置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a highly heat-resistant semiconductor device that eliminates the above-mentioned conventional drawbacks and significantly increases the low allowable temperature.

本発明によれば32〜64重量%のGeおよびNiか
らなる金属膜を熱処理してなるオーム性接触層
と、該層に接したAlでなる配線層を具備するこ
とを特徴とする−族化合物半導体装置が得ら
れる。
According to the present invention, the - group compound is characterized by comprising an ohmic contact layer formed by heat-treating a metal film made of 32 to 64% by weight of Ge and Ni, and a wiring layer made of Al in contact with the ohmic contact layer. A semiconductor device is obtained.

以下本発明について図面を用いて詳述する。 The present invention will be explained in detail below with reference to the drawings.

第1図は本発明の第1の実施例を示する斜視図
で、半導体装置としてプレーナ型のガン効果素子
を示す。同図においてn型GaAs12に接して、
32〜64重量%のGeと残部Niから成る金属層と熱
処理して成る第1の電極層13と、該第1層に接
してAlで成る配線層としての第2の電極層14
とから成る電極を具備している(なお11は高抵
抗基板である)。ここで第1の電極層は、n型
GaAsに対して、オーム性接触としての作用を有
し、第2層は配線抵抗を減じ、かつリードワイヤ
のボンデイングを容易にする作用を有する。第1
の電極層がn型GaAsに対してオーム性接触とな
り、かつ融解温度が非常に高く(800℃以上)、高
温における安定性の良好な優れた耐熱性を有して
いる。しかしながら、該第1の電極層といえど
も、第2層に従来のようにAu層を用いれば、従
来の如く、第1層にAuを主成分とする電極を使
用した場合よりも耐熱性はかなり改善されるもの
の、いずれはAuが活散、GaAs界面に達すること
となり、結局、時間の経過と共に耐熱性の低下、
許容温度の低下をきたすこととなる。時に500℃
以上の高温領域では、該第1層の特長は大きく減
じられる。ここで本発明のように前記第1層に接
する第2層をAlとすることによつて、上記のよ
うな第1層の特長を減じる現象すなわち耐熱性の
低下、許容温度の低下を防止することができる。
FIG. 1 is a perspective view showing a first embodiment of the present invention, and shows a planar Gunn effect element as a semiconductor device. In the same figure, in contact with n-type GaAs12,
A first electrode layer 13 formed by heat treatment with a metal layer consisting of 32 to 64% by weight of Ge and the balance Ni, and a second electrode layer 14 as a wiring layer made of Al in contact with the first layer.
(note that 11 is a high resistance substrate). Here, the first electrode layer is an n-type
It acts as an ohmic contact to GaAs, and the second layer has the effect of reducing wiring resistance and facilitating lead wire bonding. 1st
The electrode layer is in ohmic contact with n-type GaAs, has a very high melting temperature (over 800°C), and has excellent heat resistance with good stability at high temperatures. However, even if it is the first electrode layer, if an Au layer is used as the second layer as in the past, the heat resistance will be lower than in the case of using an electrode whose main component is Au in the first layer as in the past. Although it is considerably improved, Au will eventually become active and reach the GaAs interface, resulting in a decrease in heat resistance over time.
This will result in a decrease in the allowable temperature. sometimes 500℃
In the above high temperature range, the characteristics of the first layer are greatly reduced. Here, by using Al as the second layer in contact with the first layer as in the present invention, phenomena that reduce the features of the first layer as described above, that is, a decrease in heat resistance and a decrease in allowable temperature, can be prevented. be able to.

次の具体的一実施例について説明する。高抵抗
GaAs基板上にキヤリア密度5×1015cm-3厚さ7μ
mのn型層を成長させたウエハーを用いて、プレ
ーナ型のガン効果素子を製作した。素子長は30μ
mである。まず通常の化学エツチングにより、不
要のn型層を除去し、素子領域を形成した。次い
で、カソードおよびアノード電極部に40重量%
Ge、残部Niよりなる合金膜を1500Åの厚さに被
着し、水素ガス中500℃の温度で5分間熱処理し
てオーム性接触を得、すなわち第1の電極層を形
成した。さらに第1層上に1μmの厚さのAl膜の
第2層を形成した。この場合第2層はAlを全面
に蒸着し、しかる後、不要部のエツチングにより
形成され、平面的には、第1層の内部に限定され
ている。ここで比較のために、次の2種類のカソ
ードおよびアノード電極を備える同一形状の素子
を作成した。その1つは(比較素子1)、第1層
は前記本発明の実施例中と同一のものとし、第2
層を1μmの厚さのAu膜としたものであり、他の
1つは従来のように、第1層にAu−Ge−Niを
450℃の温度で30秒間熱処理オーム性接触とした
ものを用い、第2層に1μmの厚さのAu膜を用い
たものである。これら3種類の素子について、高
温保管によつて耐熱性、許容温度を調べた。比較
素子2は許容温度が最も低く、たとえば500℃の
温度では一瞬にして第2層のAuが反応し、電極
が完全に変質した。比較素子2においては、500
℃の温度で15分間以上経つと電極の変質が起こり
始めた。一方、本発明の実施例1の素子では、こ
れら比較素子よりはるかに高耐熱性であり、500
℃の温度で1時間電極の変質は起こらなかつた。
The following specific example will be described. high resistance
Carrier density 5×10 15 cm -3 thickness 7μ on GaAs substrate
A planar Gunn effect element was fabricated using a wafer on which an n-type layer of m was grown. Element length is 30μ
It is m. First, an unnecessary n-type layer was removed by ordinary chemical etching to form an element region. Then, 40% by weight was added to the cathode and anode electrode parts.
An alloy film consisting of Ge and the remainder Ni was deposited to a thickness of 1500 Å and heat treated in hydrogen gas at a temperature of 500° C. for 5 minutes to obtain ohmic contact, that is, to form a first electrode layer. Furthermore, a second layer of Al film having a thickness of 1 μm was formed on the first layer. In this case, the second layer is formed by depositing Al over the entire surface and then etching unnecessary parts, and is limited to the inside of the first layer in plan view. For comparison, the following two types of elements having the same shape and including cathode and anode electrodes were created. One of them (comparative element 1) is that the first layer is the same as in the example of the present invention, and the second layer is the same as in the example of the present invention.
The first layer is a 1 μm thick Au film, and the other is a conventional first layer with Au-Ge-Ni.
The ohmic contact was heat treated at a temperature of 450°C for 30 seconds, and a 1 μm thick Au film was used as the second layer. The heat resistance and allowable temperature of these three types of elements were investigated by storing them at high temperatures. Comparative element 2 had the lowest allowable temperature, for example, at a temperature of 500° C., the second layer of Au reacted instantly and the electrode completely changed in quality. In comparison element 2, 500
After more than 15 minutes at a temperature of °C, deterioration of the electrode began to occur. On the other hand, the element of Example 1 of the present invention has a much higher heat resistance than these comparative elements, and has a heat resistance of 500
No deterioration of the electrode occurred for 1 hour at a temperature of .degree.

次に本発明の第2の実施例として電界効果トラ
ンジスタのようなオーム性電極と、シヨツトキ障
壁ゲートあるいは絶縁ゲート電極とを備えたn型
GaAsからなる半導体装置について述べる。前記
電界効果トランジスタにおいてNi−Geを熱処理
してなる第1層と、Alの第2層によつてオーム
性電極を構成し、前記第2層を構成するAlによ
りゲート電極を形成せしめると、前記第1の実施
例のように高耐熱性の他に、製造技術上大きな利
点が得られる。即ちAlはn−GaAsに対して良好
なシヨツトキ接合を形成するのでゲート電極形成
と同時にオーム性電極の第2層の形成が同一工程
で行え、簡単な工程で製作が可能になる。この利
点は、前記半導体装置が集積回路を形成している
場合、なお一層効果的となる。これについて図面
を用いて説明する。第2図aは集積回路の基本単
位である2個の電界効果トランジスタからなる等
価回路を示し、bは具体的一実施構造の斜視図で
ある。例えば、第2図aの等価回路図で示す集積
回路の1単位をb図のように形成する場合、24
a,24b,24cの配線および、負荷として用
いるFETのゲート25bと負荷FETのソースお
よび駆動FETのドレイン23bとの結線等の配
線の工程は、ソースおよびドレインオーム性接触
層23a,23b,23cの形成後直ちに、トラ
ンジスタのゲート25a,25bの形成と同一工
程で、Alだけの単一層で行うことができ、極め
て簡単となる。なお21は高抵抗基板、22はn
型GaAs能動層である。
Next, as a second embodiment of the present invention, an n-type transistor having an ohmic electrode and a shot barrier gate or an insulated gate electrode, such as a field effect transistor, is described.
A semiconductor device made of GaAs will be described. In the field effect transistor, an ohmic electrode is formed by a first layer formed by heat treating Ni-Ge and a second layer of Al, and a gate electrode is formed by Al forming the second layer. In addition to high heat resistance as in the first embodiment, significant advantages can be obtained in terms of manufacturing technology. That is, since Al forms a good shot junction with n-GaAs, the second layer of the ohmic electrode can be formed in the same step at the same time as the formation of the gate electrode, allowing for simple manufacturing. This advantage becomes even more effective when the semiconductor device forms an integrated circuit. This will be explained using drawings. FIG. 2a shows an equivalent circuit consisting of two field effect transistors, which are the basic units of an integrated circuit, and FIG. 2b is a perspective view of a specific implementation structure. For example, when one unit of the integrated circuit shown in the equivalent circuit diagram of FIG. 2a is formed as shown in FIG.
The process of wiring, such as wiring of the source and drain ohmic contact layers 23a, 23b, 23c, and connection of the gate 25b of the FET used as a load with the source of the load FET and the drain 23b of the drive FET, Immediately after formation, it can be performed using a single layer of Al alone in the same step as forming the gates 25a and 25b of the transistors, which is extremely simple. Note that 21 is a high resistance substrate, and 22 is n
type GaAs active layer.

前記第2層のAlの配線部分は、第1層のオー
ム性接触部からはみ出している場合も当然含まれ
る。この場合該Alの配線部分はGaAsと直接接触
することになるが、この部分は金属接合的には
Alシヨツトキ障壁ゲートと同等であり、何ら耐
熱性を低下させる要因はない。さて従来技術で
は、このような配線部分は、例えば、Cr−Pt−
Auが用いられる場合があるが、Cr、Pt、Auのい
ずれも500℃以下の温度でGaAsと容易に反応し、
本発明の装置の耐熱性に及ぶものではない。また
このCr−Pt−Auでなる配線部分がたとえばSiO2
上に積載されている場合でも、前述したようにオ
ーム性電極部での反応が進行するのは防止できな
いため、結局本発明の装置の耐熱性特に許容温度
にははるかに及ばない。
Naturally, the case where the Al wiring portion of the second layer protrudes from the ohmic contact portion of the first layer is also included. In this case, the Al wiring part will be in direct contact with GaAs, but this part is not considered to be a metal bond.
It is equivalent to an Al shot barrier gate, and there is no factor that reduces heat resistance. Now, in the conventional technology, such a wiring part is, for example, Cr-Pt-
Although Au is sometimes used, Cr, Pt, and Au all easily react with GaAs at temperatures below 500°C.
The heat resistance is not comparable to that of the device of the present invention. Moreover, the wiring part made of this Cr-Pt-Au is, for example, SiO 2
Even if the device is stacked on top, it is not possible to prevent the reaction from progressing at the ohmic electrode portion as described above, and as a result, the heat resistance of the device of the present invention, particularly the allowable temperature, is far below.

この場合の具体的一実施例について説明する。
高抵抗GaAs基板上にキヤリア密度2×1017cm-3
厚さ0.15μmのn型層を成長させたウエハーを用
いて1.5μmのゲート長のシヨツトキ障壁ゲート
GaAs電界効果トランジスタを製作した。実施例
1と同様の工程で、ソースおよびドレイン電極部
に第1層を形成した。その後全面に0.4μmの厚さ
のAlを蒸着した後、ゲート電極部、ソースおよ
びドレイン電極のボンデイングパツド部分を覆う
マスクをホトレジストで形成した。続いてAlを
エツチングし、ゲート電極と、ソースおよびドレ
イン電極の第2層すなわちボンデイングバツドを
同時に形成し、電界効果トランジスタを形成し
た。該本発明の第2の実施例のトランジスタの高
温加速劣化テストを行つたところ、従来のトラン
ジスタの平均寿命が108時間であつたのに対し、
該トランジスタのそれは109時間以上の長寿命が
得られた。
A specific example in this case will be described.
Carrier density 2×10 17 cm -3 on high resistance GaAs substrate
A shot barrier gate with a gate length of 1.5 μm using a wafer grown with a 0.15 μm thick n-type layer
A GaAs field effect transistor was fabricated. A first layer was formed on the source and drain electrode portions in the same process as in Example 1. After that, Al was vapor-deposited to a thickness of 0.4 μm over the entire surface, and then a mask was formed using photoresist to cover the gate electrode portion and the bonding pad portions of the source and drain electrodes. Subsequently, Al was etched to simultaneously form a gate electrode and a second layer of source and drain electrodes, ie bonding pads, to form a field effect transistor. When the transistor of the second embodiment of the present invention was subjected to a high temperature accelerated deterioration test, the average life of the conventional transistor was 108 hours, whereas
The transistor had a long life of more than 10 9 hours.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を示すブレーナ
型ガン効果素子の斜視図であり、第2図a,bは
本発明の第2の実施例を示す図であり、GaAs集
積回路の1単位を示している。図において11,
21は高抵抗基板、12,22はn型GaAs能動
層、13,23a,23b,23cはGe−Ni膜
を熱処理してなるオーム性接触層、14,24
a,24b,24cはAl膜の配線層、25a,
25bはAlのゲートである。
FIG. 1 is a perspective view of a Brehner-type Gunn effect element showing a first embodiment of the present invention, and FIGS. 2a and 2b are diagrams showing a second embodiment of the present invention. It shows 1 unit. In the figure, 11,
21 is a high resistance substrate, 12 and 22 are n-type GaAs active layers, 13, 23a, 23b, and 23c are ohmic contact layers formed by heat-treating Ge-Ni films, 14, 24
a, 24b, 24c are wiring layers of Al film, 25a,
25b is an Al gate.

Claims (1)

【特許請求の範囲】[Claims] 1 n型GaAs上に32〜64重量%のGeおよび残部
Niからなる金属層を熱処理してなるオーム性接
触層と、該層に接したAlで成る配線層を具備す
ることを特徴とする−族化合物半導体装置。
1 32-64 wt% Ge and balance on n-type GaAs
1. A - group compound semiconductor device comprising: an ohmic contact layer formed by heat-treating a metal layer made of Ni; and a wiring layer made of Al in contact with the ohmic contact layer.
JP4244778A 1978-04-10 1978-04-10 Semiconductor device Granted JPS54134558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4244778A JPS54134558A (en) 1978-04-10 1978-04-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4244778A JPS54134558A (en) 1978-04-10 1978-04-10 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS54134558A JPS54134558A (en) 1979-10-19
JPH0131310B2 true JPH0131310B2 (en) 1989-06-26

Family

ID=12636320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4244778A Granted JPS54134558A (en) 1978-04-10 1978-04-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54134558A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5950213B2 (en) * 1979-04-27 1984-12-07 三菱電機株式会社 N-type gallium arsenide ohmic electrode and its formation method

Also Published As

Publication number Publication date
JPS54134558A (en) 1979-10-19

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