JPH01314325A - Memory access method for magnetic disk devices - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present method relates to a DMA transfer method in a magnetic disk device, and particularly relates to MA transfer, which is suitable for high-speed transfer of data read from and written to a magnetic disk.

[Conventional technology]

In a conventional transfer device with a transfer rate of 1.2 MB/S, it takes about 1 μs to transfer 1 byte of data read from a magnetic disk, and it takes about 1 μs to transfer 1 byte of data to a 3 MH2 microprocessor.
In a cycle of 0.333 μs.

There was enough time to read and write to the RAM before the next consecutive byte was transferred, but the transfer speed was 3MB.
/S transfer, it takes about 0.416 to transfer 1 byte.
μs, which cannot be processed by a 3MH2 microprocessor.

[Problem to be solved by the invention]

The above conventional technology is a conventional microprocessor.

ROM and RAM are used and cannot be used for data transfer faster than 1.2MB/S.

It is an object of the present invention to write continuous data from a RAM to a magnetic disk and from a magnetic disk to a RAM without intermittently using a microprocessor, a ROM, and a DMA that coexists with writing and reading data from an SC5I interface. The goal is to achieve high-speed transfer by controlling it on the data bus.

[Means to solve the problem]

The above purpose is to provide a method for 2-byte latching of data read and written from a magnetic disk, and a DMA
This is accomplished by sequential circuitry that synchronizes the data bus and prioritizes the data.

[Effect]

The 2-byte latch method is a method in which 2 bytes of the data to be transferred are latched and then transferred during continuous data transfer at a fixed cycle for data read from the magnetic disk device and written to the magnetic disk device. After latching the data, the second byte data is latched, and the transfer of the first byte data may be completed just before the third byte data is latched. In addition, the sequential circuit gives priority to data that cannot be interrupted at regular intervals, that is, data read and written from the magnetic disk device.
By synchronizing the data bus with a reference clock, D
To efficiently use an MA data bus and prevent data overrun.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows D of a magnetic disk device with SC8I interface.
A typical block diagram of MA control is shown. The data input from the data bus 7 of the SC8I interface is sent to the SC5
Data is transmitted and received in units of 8 bits by the REQ/ACK signal on the I control line 7a, and input data is sent to the bus line 1.
DMA bus 1 to RAM18 via DMAC2 via
5. The data stored in the RAM 18 is taken into the DMAC 2 via the same DMA bus 15 and written to the magnetic disk as NRZ write data via a parallel/serial converter via the bus line 14.

Reading from the 5C5I interface follows the reverse path as described above. RAM is MPU in addition to bus lines 13 and 15
The RAM pass line 15 is accessed from the three pass lines.

In the 2-byte latch system of the present invention, 8-bit data read from the magnetic disk is input from line 32 and is transmitted to line 33, the first byte is taken into LTO (24) by the clock on line 36, and the second byte is transferred to LTI. (25) by the clock on line 37. LTO(24
) is held until just before the third byte is taken into the LTO. The retained 2-byte data lines 34 and 35 are transmitted to the DMA bus 49 by the multiplexer 27 and written into the RAM. The data written to the RAM is transmitted to the bus line 44 via the DMA bus 49, and the first byte is LTO (29) and the second byte is LTO.
It is latched into TI (30) and sent out to the data bus of the SC3I interface as well.

Conversely, data input from the 5C5I interface is latched by a similar two-byte latch scheme and transmitted on line 42, and is transmitted by multiplexer 22 on line 43.
The data is stored in the RAM via the DMA bus 49, and the stored data is transferred via line 49 to the 2-byte latch 29.30.
LTO/L is latched and selected by multiplexer 31.
TI is selected and output to the bus line 36 via the multiplexer 26, and the NRZ write data 19 is written to the magnetic disk via the parallel/serial converter 5. This 2-byte latch method can reduce the processing time for 1 byte by about twice.

Next, a sequential circuit for efficiently controlling the DMA bus is shown in Fig. 3. Data read and written to a magnetic disk is continuous data with a constant period without any interruption, and the SCS
Since data on the I interface is generally transferred quickly and may be data that is interrupted once, priority is given to read/write data from the magnetic disk. On the other hand, the number of times the microprocessor and MA bus are occupied is small in DMA control, and it is desired to increase the processing time of the microprocessor. In the order of ace data, AREQ75 in Figure 3.
The order of data transfer requests is >BREQ76>CREQ77. If the ranking of the microprocessor is not raised, the microprocessor will not be able to perform any processing because it will not be able to acquire the rights to the microprocessor during reading or writing of data on the magnetic disk.

Figure 4 shows the data request signal (ASEL/ECL) of the microprocessor based on the synchronization clock CLKA81.
K) 83.84 and the disk write/read data request signal REQB85°5csr interface data request signal REQC87 synchronization and bus occupancy timing are shown. When ARBENIOI is true, it indicates that the DMA bus is occupied;
This is a signal indicating that the bus is in a state where the right to monopolize the bus can be obtained from the bus with higher priority. Signal 5REQA
89,5REQB90. and 5REQC91 indicate the synchronized microprocessor, disk write/read and data bus request signals of the 5C5I interface, respectively; 5ACKA102, 5ACKB
103 and 5ACKC104 indicate bus occupancy status. DMABUS105 indicates data on the DMA bus.

〔Effect of the invention〕

According to the present invention, a 2-byte data latch enables writing and reading of 1-byte data to and from a magnetic disk in the transfer time of 2 bytes, and a sequential circuit for acquiring DMA bus ownership allows efficient use of the DMA bus. Therefore, it is possible to easily increase the data transfer speed of the magnetic disk drive using conventional devices.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram showing a specific example of a 2-byte latch method, and Fig. 3 is a block diagram of an embodiment of the present invention.
The MA bus sequence circuit diagram, FIG. 4, is a detailed MA bus timing diagram. 7...SC8I interfunis data bus, 7a...
- Interface control signal, 8... Microprocessor address bus, 9... Microprocessor data bus, 10... Microprocessor control signal, 11, 12, 13... DMA control signal. 16... DMA address bus, 17... DMA data bus, 5... Variable register/serial converter. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In DMA (direct memory access) control of a magnetic disk device with a SCSI interface, priorities are set for the microprocessor, SCSI interface data processing, and disk write/read processing that share the RAM data bus. The data from the SCSI interface is written to the RAM, the data from the RAM is continuously written to the magnetic disk, and vice versa. A memory access method for a magnetic disk device characterized by writing continuous data from a magnetic disk into a RAM and sending the data from the RAM to a SCSI interface.