JPH01314362A - Error processing system - Google Patents

Abstract

PURPOSE:To improve a data transfer speed by generating a status command from a disk controller immediately after data transfer and validating this status command unless an error is detected. CONSTITUTION:The disk controller 1 transfers read data to a channel device 1 and generates the status command right after this data transfer. The channel device 11 checks whether or not an error occurs on an interface and when the error occurs, the status command is made invalid and error information is sent to the disk controller 1 while when no error occurs, the status command is validated. The disk controller 1 generates a retrial status command in response to the error information. Therefore, the status command is validated when no error is detected, so the normal end of the data transfer is reported speedily. Consequently, the transfer speed of the data transfer is increased and a command overrun and a data overrun are prevented.

Description

[Detailed description of the invention] [N required] Regarding the error handling method in channel devices and disk-based 611 devices, a status command is issued immediately after data transfer is completed from the disk control device, and if no error is detected, this status command is enabled. The purpose is to provide an error handling method that improves data transfer speed and prevents command overruns and data overruns by issuing a status command to the disk controller immediately after data transfer is completed. and retry status command issuing means for issuing a retry status command in response to an error notification. An error notification means for notifying an error when an error is detected, and a status command processing means for processing the status command are provided, and when an error is detected, the status command is invalidated, and when no error is detected, the status command is invalidated. Configured to enable commands.

[Industrial Application Field] The present invention relates to an error handling method in a channel device and a disk-based WJ device.

In recent years, with the development of computer systems, there has been a demand for improved data transfer speeds. Therefore, it is desirable to improve the data transfer speed also when transferring data from the disk controller to the channel device.

[Prior Art] Conventionally, when data is transferred from the disk controller side to the channel device side, that is, during read data transfer, if a data error occurs on the interface,
The channel device notifies the disk device that an error has occurred.

That is, as shown in FIG. 4, when a data error is detected by checking the error detection circuit on the channel device side, the channel device side notifies the occurrence of an error on the interface.

The disk device side issues a status command to the channel device side based on the error notification, and the channel device side receives this status command and sends a response command to the disk device side. Then, the disk device side receives the response command and issues an end status command to the channel device side.

In this case, the completion status after data transfer on the disk device side is issued after a certain period of time, taking into consideration the error notification time on the channel device side.

[Problems to be Solved by the Present Invention] However, as described above, the completion status is issued after data transfer on the disk device side after a certain period of time, taking into account the error notification time of the channel device, so if an error is detected, Otherwise, the preparation for the next data processing is delayed, making it impossible to increase the data transfer speed, and causing problems such as command overruns and data overruns.

The present invention has been made in view of such conventional problems, and it is possible to issue a status command from a disk controller immediately after data transfer is completed, and to make this status command valid if no error is detected. It is an object of the present invention to provide an error handling method that improves data transfer speed and prevents command overruns and data overruns.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 4A is provided in the disk control device 1 and issues a status command immediately after data transfer is completed, and 4B is also provided in the disk control device 1 and issues a retry status command in response to an error notification. Retry status command issuing means 17 is provided in the channel device 11 and detects an error in data transferred via the interface; 20 is also provided in the channel device 11 and detects an error when an error is detected. An error notification means 18 for notifying is also provided in the channel device 11,
A status command processing means for processing the status command.

[Operation] The disk control device 1 transfers the read data to the channel device 11, and immediately after this data transfer, issues a status command. The channel device 11 side checks whether an error has occurred on the interface, and if an error occurs, invalidates the status command and sends an error notification to the disk controller 1, and if no error occurs, sends the status command to the disk controller 1. Valid. On the disk control device 1 side, a retry status command is issued in response to the error notification.

Therefore, when the occurrence of an error is not detected, the status command becomes valid, so that it is possible to promptly notify that the data transfer has been successfully completed. As a result, the data transfer speed can be improved, and command overruns and data overruns can be prevented.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 2 and 3 are diagrams showing one embodiment of the present invention.

In FIG. 2, 1 indicates a disk control device, which includes an automatic data transfer control circuit (hereinafter referred to as an ADT control circuit) 2, a multiplexer 3, an MP
tJ4, a decoder 5, and registers 6.7.

ADH control circuit 2 is connected to multiplexer 3 via signal line 8.
At the same time, the MPU 4 is notified of the end of read data transfer via the signal line 9.

Therefore, the read data from the disk device is
Bus 10 from control circuit 2 and multiplexer 3 2 routes
is transferred to the channel device 11 via. Immediately after this data transfer is completed, the MPU 4 issues a status command to the channel device 11 via the bus 10 from the path 1 between the register 7 and the multiplexer 3.

Further, when the MPtJ4 is notified of the occurrence of an error from the channel device 11 via the bus 12 via the register 6 and the decoder 5, the MPtJ4 issues a retry status command based on this error notification.

Therefore, MPtJ4 has the functions of status command issuing means 4Δ for issuing status commands and retry status command issuing means 4B for issuing retry status commands.

Note that 12A indicates a bus through which write data is transferred.

Next, FIG. 3 shows the configuration of the channel device.

In FIG. 3, the channel device 11 includes registers 13,
14, ADT control circuit 15, main memory control circuit 16, error detection circuit 17, flip-flop 18A1 decoder 1
8B, a CPU control circuit 19, an MPU 20, and a multiplexer 21.

Read data transferred via bus 10 is in register 1.
3 to the ADT control circuit 15, and the ADT control circuit 1
5 transfers read data from the main memory control circuit 16 to a CP (not shown).
The signal is sent to the LJ and also sent to the error detection circuit 17 which is an error detection means.

The error detection circuit 17 detects whether a data error has occurred on the bus 10, and if an error has occurred, the output of the flip 70 knob 18A is set to 1'' and the status command from the disk controller 1 is input. When no error occurs, the output of the flip-flop 18A is set to "O" and the contents of the decoder 18B to which the status command is input are made valid.
8B functions as a status command processing means 18 for processing status commands. However, if no error occurs, the status command is sent to the decoder 18.
B is made valid and notified to the MPU 20 via the signal line 22. Furthermore, when an error occurs, the error detection circuit 17 notifies the ADT control circuit 15 via the signal line 23, and the ADT control circuit 15 notifies the MPU 20 via the signal line 24.

Based on this error notification, the MPU 20 changes the register 14,
The error is notified to the disk controller 1 from one path of the multiplexer 21 via the bus 12. Therefore, M
PL, 120 functions as an error notification means for notifying an error.

Note that 25 indicates a bus for transferring write data.

Next, the operation will be explained.

When data is transferred from the disk controller 1 to the channel device 11, that is, at the time of read data transfer, the second
As shown in the figure, ADT control circuit 2, multiplexer 3
Data is transferred to the channel device 11 via the bus 10 from the second path.

In the channel device 11, as shown in FIG.
Data is sent to the ADT control circuit 15 via 3.

Next, the data is sent from the ADT control circuit 15 to the error detection circuit 17, and the error detection circuit 17 checks whether a data error has occurred on the bus 10.

On the other hand, in FIG. 2, immediately after the data transfer, ADT!
lti [! 1 circuit 2 notifies MPU 4 of the end of data transfer, and MPU 4 sends a status command to channel device 11 from register 7 and path 1 of multiplexer 3 via bus 10 in response to this data transfer end notification.

This status command is sent to the decoder 18B via the register 13, as shown in FIG.

Here, if the error detection circuit 17 does not detect a data error, the output of the flip-flop 18A becomes "OF1", so the status command decoded by the decoder 18B is considered valid and is notified to the MPU 20.

On the other hand, when the error detection circuit 17 detects a data error, the output of the flip-flop 18A becomes "1", so that the contents of the decoder 18B are invalidated. The occurrence of an error is notified to the MPU 20 via the ADT control circuit 15, and the MPU 20 controls the register 14 and multiplexer 2.
The occurrence of the error is notified to the disk control device 1 via the route 1 of 1.

That is, the occurrence of an error is notified to the MPU 4 via the bus 12, through the register 6 and the decoder 5, as shown in FIG. The MPU 4 issues a retry status command in response to this error notification.

Therefore, if a status command is issued immediately after data transfer and no error is detected on the interface, the status command is validated, so that it is possible to quickly notify that the data transfer has ended normally. As a result, the data transfer speed can be improved, and command overruns and data overruns can be prevented.

[Effects of the Invention] As described above, according to the present invention, a status command is issued immediately after data transfer, and the status command is enabled or disabled depending on whether a data error occurs on the interface. Therefore, when no errors occur, it is possible to quickly notify that data transfer has been completed normally. As a result, the data transfer speed can be improved, and command overruns and data overruns can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a configuration diagram of a disk control device showing an embodiment of the invention. FIG. 3 is a configuration diagram of a channel device showing an embodiment of the invention. The figure is an explanatory diagram of a conventional example. In the figure, 1... Disk control device, 2... ADT control device, 3... Multiplexer, 4... MPU, 4A... Status command issuing means, 4B... Retry status command issuing means, 5... Decoder, 6.7... Register, 8.9... Signal line, 10.12... Bus, 11... Channel device, 13.14... Register, 15... ADT control circuit, 16... Main memory control circuit, 17... Error detection circuit (error detection means), 18A
...Flip-flop, 18B...Decoder, 18...Status command processing means, 19...C
PLJ control circuit, 20...MPU (error notification means), 21...Multiplexer, 22.23.24...Signal line, 25...Bus.

Claims (1)

[Claims] A status command issuing means (4A) that issues a status command to the disk control device (1) immediately after data transfer is completed, and a retry status command issuing means (4A) that issues a retry status command upon error notification.
4B), an error detection means (17) for detecting an error in data transferred to the channel device (11) via the interface, and an error notification means (20) for notifying an error when an error is detected. ), and status command processing means (
18) An error handling method characterized in that the status command is invalidated when an error is detected, and the status command is validated when no error is detected.