JPH0131636B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a data recording sheet for automatic performance, and aims to reduce the amount of data by recording chord name data and some generation timing data for chords to be generated. .

Conventionally, as this type of data recording sheet, one in which chord name data is recorded in the order in which the chords occur is known (for example, see Japanese Utility Model Application No. 50-926).

However, according to this recording method,
When the chords change frequently or irregularly as the music progresses, the amount of data to be recorded becomes enormous and the area of the recording section also increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a new data recording sheet for automatic performance that eliminates such inconveniences.

The automatic performance data recording sheet according to the present invention is characterized in that chord name data and some generation timing data are recorded for chords to be generated.Hereinafter, an embodiment shown in the accompanying drawings will be described in detail. .

FIG. 1 shows the format of automatic performance data recorded on a musical score as an automatic performance data recording sheet according to a first embodiment of the present invention.

A data recording section 10a is provided in the lower margin of the musical score 10.
is provided. The data recording section 10a is made up of, for example, one track of magnetic tape pasted on the sheet surface, and the magnetic tape contains melody pitch data corresponding to the melody content of the musical score 10 and end data FNS.
, the delimiter mark data DM ₁ , the melody note length data corresponding to the melody contents of the musical score 10, the delimiter mark data DM ₂ , and the chord data corresponding to the chord contents of the musical score 10 are serialized in accordance with this written order. It is recorded magnetically in the form of data.

Melody pitch data indicates the pitch using a 6-bit binary code for each melody note, and the upper 2 bits of the 6 bits represent the octave.
The remaining 4 bits represent the note name. The melody pitch data corresponding to each melody note is arranged in the order in which it should be sounded as the melody progresses, and the rest data consisting of the 6-bit binary code "111000" is placed in the position corresponding to the rest in the arrangement. Placed.

The end data FNS consists of a 6-bit binary code "110000" and represents the end of the melody.
Also, the delimiter mark data DM ₁ consists of a 6-bit binary code "110100", and the end data
Represents the break between FNS and the first melody note length data.

The melody note length data indicates the length of each note or rest in the melody progression, that is, the note length, and is composed of a 4-bit binary code. The delimiter mark data _DM2 consists of a 4-bit binary code, and represents the delimiter between the final melody note length data and the first chord data.

The chord data includes chord name data indicating the chord name of the chord to be generated and timing data indicating the chord generation timing, and both the chord name data and the timing data are composed of 10-bit binary codes. In the chord name data, the top 4 bits are "1" and represent the identification mark, and the top 2 of the remaining 6 bits represent the chord type such as major, seventh, etc., and the remaining 4 bits represent the root note name such as C, G, etc. By representing chord names such as C major ( _CM ), G seventh (G ₇ ), etc. The lower 6 bits of the chord name data can change from all bits "0" to all bits "1", so the chord name data can be expressed as a decimal number to represent different chord names corresponding to 960 to 1023. It is possible.

The upper 4 bits of the timing data represent an identification mark, and the remaining 6 bits represent an address number such as "1", "15", "40", etc. as exemplified for _CM . In this case, the address number corresponds to the address number used when the aforementioned melody pitch data is once transferred to the memory in the automatic performance device and then read out from there as the melody progresses.
Indicates the chord generation timing. Since the upper 4 bits of the timing data can vary from "0000" to "1110", the identification mark code is not constant, unlike the chord name data described above. Further, since the lower 6 bits of the timing data can be changed from "000000" to "111111", the timing data can be converted into a decimal number and can represent different address numbers corresponding to 0 to 959.

For chord data, the identification mark bit may be one bit (for example, chord name data is "1" and timing data is "0"), and the remaining nine bits may represent the chord name or address number. In this case, it is possible to express different chord names or different address numbers corresponding to decimal numbers 0 to 511. Further, regarding the chord name data, the chord type bits may be set to three or more bits to represent even more chord types.

Next, referring to FIG. 2, an automatic performance device as a device for using the musical score shown in FIG. 1 will be explained.

When the lower part of the musical score 10 is inserted into the receiving port of the data reading device 12, the data reading device 12 sequentially reads the automatic performance data in the data recording section 10a and stores it in RAM (Random Access Memory) in the form of serial data.
memory) is supplied to the write control circuit 14.

The RAM write control circuit 14 writes 6-bit serial melody pitch data in serial/parallel (S/
P) Supply the pitch data to the RAM 18 as 6-bit parallel data via the conversion circuit 16, write it to the RAM ₁₈ in response to the write address signal WA1,
When writing of the melody pitch data is completed, end data FNS is written to the RAM 18 in the same manner. next,
RAM write control circuit 14 is delimiter mark data
After detecting DM ₁ , the 4-bit serial melody note length data is transferred to the note length data RAM 2 in the form of 4-bit parallel data via the S/P conversion circuit 20.
2 and according to the write address signal WA ₂
Write to RAM22. Then, when writing of the melody note length data is completed, the RAM write control circuit 14 detects the delimiter mark data _DM2 , and then,
The chord data is supplied to the chord data RAM 28 as 16-bit parallel data via the S/P conversion circuit 24 and the data format conversion circuit 26,
Write to RAM 28 in response to write address signal _WA3 . In this case, the S/P conversion circuit 24 converts the 10-bit serial chord data into 10-bit parallel chord data, and the data format conversion circuit 26 converts the 10-bit serial chord data into 10-bit parallel chord data.
converts 10-bit parallel chord data into 16-bit parallel chord data as illustrated in FIGS. 3A and 3B. That is, on the input side of the data format conversion circuit 26, as illustrated in FIG. 3A, chord data indicating the chord name _CM and the generation timing of the chord _CM are stored as address numbers "1", "15",
The timing data shown corresponding to "40"... are all sequentially supplied as parallel 10-bit data, but the data format conversion circuit 26
On the output side, as shown in FIG. 3B, there is a parallel 6 output that indicates the chord name C _M for each of the parallel 10-bit timing data corresponding to the address numbers "1", "15", "40", etc. 16-bit parallel chord data in the form of a combination of bit chord name data is sequentially transmitted. Note that the parallel 6-bit chord name data in Figure 3B is the same as the parallel 6-bit chord name data in Figure 3A.
This corresponds to the 10-bit chord name data with the 4-bit identification mark bit removed.

Reading of melody data from RAMs 18 and 22 is controlled by a read control circuit 30,
Reading of chord data from RAM 28 is controlled by a search circuit 32.

In the read control circuit 30, the start switch
When the SW is turned on, the R-S flip-flop 34
is set, and its output Q="1" is supplied to the inverter 36 and the differentiating circuit 38. The inverter 36 generates an output signal = "1" when not playing, and the output signal of the flip-flop 34 is
="1", the output signal becomes "0".
Further, the differentiating circuit 38 generates a start signal ΔSTRT by differentiating the output Q=“1” of the flip-flop 34 at the rising edge in synchronization with the system clock signal φ.

The start signal ΔSTRT is supplied via the OR gate 40 as a clock input CK to the address counter 42 whose reset is released by the signal, so that the counter 42 receives the start signal ΔSTRT.
Accordingly, a read address signal _RA1 corresponding to the first read address is generated. This read address signal
In response to RA ₁ , melody pitch data corresponding to the first melody tone is read out from the RAM 18 and supplied to the key depression display device 44 and the melody sound source circuit 46. Therefore, the pressed key display device 44 uses a light emitting element or the like to display that the key corresponding to the first melody note should be pressed on the keyboard or keyboard diagram. Furthermore, the melody sound source circuit 46 electronically synthesizes a musical tone signal corresponding to the first melody tone and supplies it to the speaker 50 via the output amplifier 48.
From 0, the first melody sound is generated.

After the address counter 52 is reset by the signal, the read address signal corresponding to the first read address is reset in response to the start signal ΔSTRT.
Generates RA ₂ . Melody note length data corresponding to the first melody note is read from the RAM 22 in response to the read address signal RA ₂ and is supplied to the comparison circuit 56 via the length data conversion circuit 54 as one comparison input. Here, the length data conversion circuit 54 is composed of a ROM (read only memory) or the like, and converts the length of the note or rest indicated by the melody note length data from the RAM 22 using the tempo clock source 58. The conversion output as shown is generated in correspondence with the count value of the generated tempo clock signal TCL.

After being reset by the start signal ΔSTRT from the OR gate 62, the note length counter 60 counts the tempo clock signal TCL and supplies its count output to the comparison circuit 56 as the other comparison input.
Therefore, the comparison circuit 56 compares both comparison inputs and generates a coincidence signal EQ when the count value of the counter 60 reaches a value corresponding to the first melody note length.

This coincidence signal EQ is passed through a D-flip-flop 64 timed by the clock signal φ, and then to an OR
Since the counter 60 is reset through the gate 62, the counter 60 counts the tempo clock signal TCL again after the reset. Further, since the match signal EQ is supplied to the counter 42 via the OR gate 40, the counter 42 increments by one count and generates the read address signal _RA1 corresponding to the second read address. Therefore, melody pitch data corresponding to the second melody tone is read from the RAM 18 and supplied to the key press display device 44 and the melody sound source circuit 46. Therefore, the pressed key display device 44 displays a pressed key corresponding to the second melody tone as before, and the melody sound source circuit 46 synthesizes a musical tone signal corresponding to the second melody tone as before. A second melody sound is generated from the speaker 50.

The match signal EQ from the comparison circuit 56 is also supplied to the counter 52 via the gate 40, so that
Counter 52 generates a read address signal _RA2 corresponding to the second read address. For this reason,
Melody note length data corresponding to the second melody note is read from the RAM 22 and supplied to the comparison circuit 56 via the length data conversion circuit 54. At this time, since the count output of the counter 60 is also supplied to the comparison circuit 56, the comparison circuit 56 performs the comparison operation in the same manner as the previous time. The count value of counter 60 is 2
When the value corresponding to the note length of the th melody note is reached, a matching signal EQ is generated again. Thereafter, a coincidence signal EQ is generated in the same manner every time the measurement of note length (or rest length) is completed. Then, each time the coincidence signal EQ is generated, new melody data is read out.
Based on the read data, automatic key press display and automatic melody performance are performed.

Finally, the end data FNS is read from the RAM 18 and supplied to the end detection circuit 66. When the end detection circuit 66 detects the end data FNS, it uses its detection output to reset the flip-flop 34, thereby completing the series of melody data reading.

What has been described above is the melody data reading operation, but chord data is also read out in parallel.

In the search circuit 32, the R-S flip-flop 68 is set in response to the search command signal SI consisting of the output signal of the above-mentioned OR gate, and the search command signal SI is set by the address counter 70 that counts the clock signal φ. It is designed to reset the When the start signal .DELTA.STRT is generated, the search command signal SI consisting of the start signal .DELTA.STRT causes the flip-flop 68 to be set and the counter 70 to be reset. After this reset, the counter 70 counts the clock signal φ and supplies the read address signal RA ₃ to the RAM 28. Therefore, chord data is read out from the RAM 28 at high speed.

Of the chord data read out at this time, the timing data TD is supplied to the comparison circuit 72 as one comparison input, and the chord name data CD is supplied to the latch circuit 74. The other comparison input of the comparison circuit 72 is supplied with melody progress data (read address signal RA ₁ ) indicating the first read address number from the counter 42 . Therefore, the comparison circuit 72 compares both comparison inputs and generates a match signal EQ if they match. As previously illustrated with reference to _FIG .
Match signal when reading first data from RAM28
Generates EQ and supplies it to AND gate 76. At this time, since the AND gate 76 is conductive due to the output Q=“1” of the flip-flop 68, the match signal EQ from the comparison circuit 72 is sent to the latch circuit 74 via the AND gate 76 as a load signal.
Supplied as LD. Therefore, the latch circuit 7
4 latches the chord name data indicating the chord name C _M ,
The signal is supplied to an accompaniment sound source circuit 76.

The accompaniment sound source circuit 76 electronically generates a chord signal corresponding to the constituent tones of the _CM chord and a bass tone signal matching the _CM chord and the selected rhythm based on the first chord name data from the latch circuit 74. and these signals are supplied to the speaker 50 via the output amplifier 48. Therefore, the speaker 50 generates the above-mentioned first melody tone as well as the _CM chord and the bass tone corresponding thereto.

On the other hand, the tempo counter 78 whose reset is canceled by the signal counts the tempo clock signal TCL and supplies the count output to the rhythm pattern memory 80, so that the rhythm pattern signal RP corresponding to the selected rhythm and the accompaniment timing are output from the memory 80. A signal AT is generated. The accompaniment timing signal AT is supplied to the accompaniment sound source circuit 76 and is used to control the transmission timing of the chord signal and the bass tone signal in conjunction with the rhythm. The rhythm pattern signal RP is also supplied to the rhythm sound source circuit 82, which generates a rhythm sound signal by driving an appropriate rhythm sound source. Since the rhythm sound signal from the rhythm sound source circuit 82 is also supplied to the speaker 50 via the output amplifier, the speaker 50 also generates rhythm sound.

By the way, when the counter 70 reaches a count value corresponding to all addresses in the RAM 28 (one cycle of high-speed reading of chord data from the RAM 28 is completed), the counter 70 generates a carry-out output CO and resets the flip-flop 68.

Next, when the comparison circuit 56 generates the first matching signal EQ in response to the second melody tone, this matching signal EQ sends the search command signal SI to the search circuit 32.
, the flip-flop 68 is set again and the counter 70 resumes counting the clock signal φ after being reset. Therefore, high-speed data reading from the RAM 28 is performed in the same manner as the previous time, and the comparison circuit 72 detects that the timing data TD corresponding to address number "2" is read from the RAM 28.
Check whether it is read from 8. In this case, assuming that there is no timing data TD corresponding to address number "2", the chord name data in the latch circuit 74 will not be updated, so the speaker 50 will still generate the _CM chord and the corresponding bass tone. Ru.

Thereafter, the above operation is repeated, and when the time comes when the counter 42 supplies the data corresponding to the address number "8" to the comparison circuit 72, the comparison circuit 72 outputs the data corresponding to the address number "8" as before. The corresponding timing data TD is RAM2
Check whether it is read from 8. In this case, assuming that there is timing data TD corresponding to the address number "8" corresponding to the chord name _G7 as illustrated in FIG.
Therefore, in response to this coincidence signal EQ, the latch circuit 74 latches the chord name data CD indicating the chord name _G7 . Therefore, from speaker 50, G ₇
The chord CM and its corresponding bass note are generated in place of the _CM chord and its corresponding bass note.

As described above, the automatic performance device shown in FIG. 2 automatically displays the melody key presses based on the melody pitch data, melody note length data, and chord data transferred from the musical score 10 to the RAMs 18, 22, and 28. Since melody performance, chord/bass tone performance, and automatic rhythm performance can also be used, it is very useful when practicing playing or playing in an ensemble.

FIG. 4 shows the format of automatic performance data recorded in a musical score according to a second embodiment of the present invention. The format according to the second embodiment differs from the format according to the first embodiment described above in the manner in which the chord data is expressed, and is otherwise the same as the first embodiment. That is,
The chord data recorded in the data recording section 10a of the musical score 10 includes chord name data and timing data each consisting of a 9-bit binary code. In the chord name data, the most significant bit is "0" to represent the identification mark, and the remaining 8 bits represent the chord type with the upper 4 bits and the root note name with the remaining 4 bits, such as chords such as C _M and G ₇ . represents a name. Also,
In the timing data, the most significant bit is "1" and represents an identification mark, and the remaining 8 bits represent the measure number with the upper 6 bits and the beat number with the remaining 2 bits, thereby identifying the first beat of the first measure (1.
1), represents the chord generation timing, such as the first beat of the third measure (3・1).

FIG. 5 shows an automatic performance device as an apparatus for using the musical score shown in FIG. 4, and the same parts as in FIG. 2 are given the same reference numerals and detailed explanation thereof will be omitted.

The S/P conversion circuit 24 converts the 9-bit serial chord data into 9-bit parallel chord data and supplies it to the data format conversion circuit 26.
The data format conversion circuit 26 converts 9-bit parallel chord data into 16-bit parallel chord data as illustrated in FIGS. 6A and 6B.
That is, on the input side of the data format conversion circuit 26, as illustrated in FIG. 6A, chord name data indicating the chord name _CM and the generation timing of the chord _CM are stored in the bar/beat number "1.1". The timing data shown in correspondence with "3.1" . Parallel 8 compatible with measure/beat numbers "1.1", "3.1"...
16-bit parallel chord data is sequentially transmitted in the form of a combination of parallel 8-bit chord name data indicating the chord name _CM for each bit of timing data. The 8-bit timing data and chord name data in FIG. 6B correspond to the 9-bit timing data and chord name data in FIG. 6A with one identification mark bit removed.

The counter 90 counts the tempo clock signal TCL after being reset by a signal, and supplies a count output corresponding to the beat number to the rhythm pattern memory 80.
Further, the counter 90 supplies the carry-out output CO to the measure counter 92 every time the count value corresponding to one measure is reached, and the measure counter 92 counts the carry-out output CO after being reset by a signal. and generates a count output corresponding to the bar number.

The count outputs of the counters 90 and 92 are combined to form bar/beat number data BD, which is supplied to the search circuit 32 as progress data indicating the progress of the music. Further, among the count outputs of the counter 90, a beat pulse BP generated for each beat is supplied to the search circuit 32 as a search command signal.

Every time a beat pulse BP is generated, the search circuit 32 reads the chord data from the RAM 28 at high speed in the same way as described above and compares it with the bar/beat number data BD to determine the timing corresponding to the bar/beat number indicated by the data BD. Check whether data is read from RAM 28. As illustrated in Figure 6, 1
Assuming that there is timing data corresponding to the first beat "1.1" of the measure, the search circuit 32 latches the chord name data indicating the chord name _CM when reading this timing data, and sends it to the accompaniment sound source circuit 76. supply Therefore, the speaker 50 generates the _CM chord and the bass tone corresponding thereto, as described above.

After this, the timing corresponding to the second beat of the second bar is reached, and the timing data indicating the timing "2.2" is read out from the RAM 28 as illustrated in FIG.
2 extracts chord name data indicating the chord name G ₇ and supplies it to the accompaniment sound source circuit 76 . Therefore, instead of recording _CM and the corresponding bass tone, the speaker 50 generates the _G7 chord and the corresponding bass tone.

FIG. 7 shows the format of automatic performance data recorded in a musical score according to a third embodiment of the present invention. The format according to the third embodiment differs from the format according to the first embodiment described above in that the melody pitch data includes accompaniment commands and the chord timing data is determined in accordance with the number of accompaniment commands. be. In other words, the melody pitch data is a 6-bit binary code "111100" corresponding to multiple points in the melody progression.
This is recorded in the data recording section 10a of the musical score 10 in a form that includes an accompaniment instruction consisting of the following. Further, the chord data includes chord name data and timing data each consisting of an 8-bit binary code. In the chord name data, the most significant bit is “0” and represents an identification mark.
Of the remaining 7 bits, the upper 3 bits represent the chord type, and the remaining 4 bits represent the root note name, such as _CM , G _7, etc. In the timing data, the most significant bit is "1" to represent an identification mark, and the remaining 7 bits represent the number of accompaniment commands such as "1", "5", and "9" to represent the chord generation timing.

FIG. 8 shows an automatic performance device as a device for using the musical score shown in FIG. 7, and the same parts as in FIG. 2 are given the same reference numerals and detailed explanation thereof will be omitted.

The accompaniment instructions read from the musical score 10 are converted into parallel 6-bit data by the S/P conversion circuit 16 in the same way as individual melody pitch data, and then stored in the RAM.
18. Further, the chord data is converted into parallel 8-bit data by the S/P conversion circuit 24 and then stored in the RAM 28.

In the read control circuit 30, when the start signal ΔSTRT is generated, this signal ΔSTRT becomes
Since the clock signal φ is supplied to the AND gate 102 via the OR gate 100, the clock signal φ is supplied to the counter 42 via the AND gate 102. The counter 42 counts the clock signal φ by 1 and outputs the read address signal RA ₁ corresponding to the first read address.
Supply to RAM18. Therefore, melody pitch data corresponding to the first melody tone is read from the RAM 18 and supplied to the latch circuit 104. At this time, the accompaniment command detection circuit 106 which inputs the read data of the RAM 18 outputs a signal = "0".
Therefore, the inverter 108 that receives this output signal inputs the output signal = “1” to the AND gate 1.
Supply to 10. For this reason, AND gate 110
supplies the clock signal φ to the latch circuit 104 as the load signal LD, and in response, the latch circuit 1
04 latches the first melody pitch data from the RAM 18 and supplies it to the key press display device 44 and the melody sound source circuit 46. Therefore, the key press display device 4
4, a key depression display corresponding to the first melody sound is made, and the first melody sound is generated from the speaker 50.

On the other hand, the start signal ΔSTRT is the OR gate 11
2 to the counter 52,
Melody note length data corresponding to the first melody note is read from the RAM 22 and supplied to the comparison circuit 56 via the length data conversion circuit 54. Comparison circuit 56 generates a coincidence signal EQ when the count value of counter 60 reaches a value corresponding to the note length indicated by the first melody note length data. This coincidence signal EQ is a conductive AND with the output signal of the inverter 108.
The clock signal φ from the AND gate 102 is supplied to the AND gate 102 through the gate 114 and the OR gate 100, so that the counter 42 again counts the clock signal φ from the AND gate 102. Therefore, the first accompaniment instruction is read from the RAM 18 and supplied to the accompaniment instruction detection circuit 106.

The accompaniment command detection circuit 106 generates an output signal="1" in response to the first accompaniment command. This output signal is supplied to the AND gate 102 via the OR gate 100, so the melody pitch data corresponding to the second melody tone is read out from the RAM 18 and latched into the latch circuit 104 as before. As a result, the key depression display corresponding to the second melody tone and the automatic performance of the second melody tone are performed.

Further, the output signal from the accompaniment command detection circuit 106 is supplied as a signal to the number counter 116 whose reset has been canceled, and the counter 116 is incremented by one count, while being supplied to the search circuit 32 as a search command signal SI. Note that the comparison circuit 5
Since the coincidence signal EQ from 6 is supplied to the counter 52 via the OR gate 112, the melody note length data corresponding to the second melody tone is read out from the RAM 22 and subjected to the same note length measurement as the previous time. .

The data reading operation as described above is repeated in the same manner, thereby performing automatic key press display and automatic melody performance. Then, the number counter 116 generates number data indicating the number of accompaniment commands generated from the RAM 18, and the data is sent to the comparison circuit 7 of the search circuit 32 as melody progress data.
supplied to

By the way, the search circuit 32 reads chord data from the RAM 28 at high speed every time the search command signal SI is generated in synchronization with the reading of an accompaniment command from the RAM 18. The signal of the most significant bit of the read data from the RAM 28 is supplied to the gate circuit 118 as an enable signal EN, and is also supplied as a load signal to the latch circuit 122 via an inverter 120.
The remaining 7-bit signal becomes input data to the gate circuit 118 and latch circuit 122. As mentioned above, the most significant bit signal represents an identification mark, and is "0" if it is chord name data, and "1" if it is timing data. Therefore, each time the timing data TD is read from the RAM 28, the gate circuit 118 becomes conductive and supplies it to the comparison circuit 72. Also, latch circuit 1
22 latches the chord name data CD each time it is read from the RAM 28 and supplies it to the latch circuit 74.

The comparison circuit 72 compares the number data from the number counter 116 and the timing data TD from the gate circuit 118, and generates a match signal EQ every time the two match.
The data is supplied to the latch circuit 74 via the AND gate 76, and the chord name data CD at this time is latched by the latch circuit 74. Now, assuming that the first accompaniment command is read from the RAM 18, the comparison circuit 72 generates a coincidence signal EQ when the timing data TD indicating the number of accompaniment commands "1" is read from the RAM 28, and in response A latch circuit 74 latches chord name data CD indicating chord name _CM .
Therefore, the speaker 50 generates _CM and bass sounds corresponding thereto.

After this, when the third accompaniment command is generated from the RAM 18, the comparison circuit 72
When the timing data TD indicating the number of accompaniment commands "3" is read from the RAM 28, the coincidence signal EQ
The latch circuit 74 generates the chord name in response to this.
Latch the chord name data CD showing G ₇ . Therefore, the G ₇ chord and the bass tone corresponding thereto are generated from the speaker 50 in place of the _CM chord and the bass tone corresponding thereto.

Note that in the third embodiment described above, the search circuit 32
This embodiment differs from the first and second embodiments described above in that the generated chord always changes when the reading operation is performed.

In the embodiments described above, a musical score was used as an example of the automatic performance data recording sheet, but this may be a sheet other than the musical score.

As described above, according to the present invention, since the chord name data and some generation timing data are recorded for the chords to be generated, the chords change frequently or irregularly as the music progresses. Even in such a case, since there is no need to record the same chord name data overlappingly, the amount of data to be recorded can be reduced accordingly. Furthermore, no matter how complex a piece of music is, the chord progression can be expressed by a combination of chord names and chord generation timings, which has the effect of making automatic chord performance possible for all kinds of pieces of music.

[Brief explanation of drawings]

FIG. 1 is a format diagram of automatic performance data recorded in a musical score according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram of the automatic performance device according to the first embodiment, FIGS. 3A and 3B are diagrams for explaining the data format conversion operation in the circuit of FIG. 2, and FIG. A format diagram of automatic performance data recorded in a musical score according to a second embodiment of the present invention, FIG. 5 is a circuit diagram of an automatic performance apparatus according to the second embodiment, and FIGS. FIG. 7 is a diagram for explaining the data format conversion operation in the circuit shown in the figure, FIG. FIG. 2 is a circuit diagram of an automatic performance device according to an embodiment of the present invention. 10... Musical score, 10a... Data recording section, 12
...Data reading device, 18...Pitch data
RAM, 22... Note length data RAM, 28... Chord data RAM, 30... Read control circuit, 32...
...Search circuit, 44...Key press display device, 46...
...melody sound source circuit, 76...accompaniment sound source circuit.

Claims (1)

[Scope of Claims] 1. An automatic system characterized by having a part in which chord name data indicating the chord name of the chord to be generated is recorded, and a part in which timing data indicating different generation timings of the chord are recorded. Performance data recording sheet. 2. The automatic performance data recording sheet according to claim 1, wherein the timing data is comprised of coded data indicating bar numbers and beat numbers. 3. A part where melody data is recorded corresponding to the melody progression, a part where chord name data indicating the chord name of the chord to be generated is recorded, and different generation timings of the chords are shown in relation to the melody progression. 1. A data recording sheet for automatic performance, comprising a portion in which timing data is recorded. 4. The automatic performance data recording sheet according to claim 3, wherein the timing data is comprised of coded data indicating an address number when reading the melody data after transferring it to a memory. A data recording sheet for automatic performance. 5. In the automatic performance data recording sheet according to claim 3, the melody data includes accompaniment commands corresponding to a plurality of points in the melody progression, and the timing data includes a code indicating the number of accompaniment commands. A data recording sheet for automatic performance, characterized in that it consists of converted data.