JPH01319320A - digital signal processing device - Google Patents

Abstract

PURPOSE:To reduce the scale of an input circuit and an arithmetic circuit by executing directly the filtering processing to a data signal subject to compression. CONSTITUTION:The unit is provided with a convolution arithmetic unit 3 receiving its input i a form of being compressed into a digital differential signal with a signal before the unit time and applying convolution with the weight coefficient, an adder 4 and a register 5. Then an output of the convolution arithmetic unit 3 is given to one input of the adder 4, an output itself of the adder 4 is inputted with a delay of unit time via a register 5 and an output of the adder 4 is used as the final output. Thus, it is possible to apply arithmetic processing directly to a signal being subject to data compression as a difference signal between the input and the signal before the unit time. Then the bit width of the input data is reduced, the bit width of the input data is reduced and the bit width of the input circuit and the arithmetic circuit is decreased and the circuit scale is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal processing device that realizes an acyclic digital filter.

Conventional technology In digital signal processing, analog input signals are
Desired processing is achieved by performing arithmetic processing on the digital signal that has been discretized and quantized by the /D converter. With recent advances in technology, digital signal processing of images has become possible, but many technical issues remain in image processing due to the large amount of data to be handled and high speed processing.

FIG. 2 shows an example of a digital signal processing device that realizes a two-dimensional acyclic filter expressed by equation (1).

・・・・・・(D F(x, y); Input G (x * y); Output Wij; Load coefficient n, m; Number of taps To simplify the explanation here, n=m=3, that is, 3 ×3
This will be explained as a two-dimensional filter for a local region of pixels. In FIG. 2, image data F(x, y) taken out as one-dimensional data by scanning is stored in line memories 1 and 2.
The data is converted into 3 lines of data by the convolution operator 3.
input at the same time.

The convolution calculator 3 executes the convolution operation shown in equation (1) and outputs the operation result G (x, y).

Here, as the configuration of the convolution calculator 3, for example,
As shown in Japanese Patent Application No. 2-262277, a program-controlled processor may also be used.
As shown in Japanese Patent No. 86064, a configuration may be used in which a plurality of arithmetic units are integrated and operated in parallel in a pipeline manner.

Problems to be Solved by the Invention In digital signal processing, particularly in image data processing, the amount of data to be handled is enormous, so the scale of the processing device has tended to be large and complex.

The present invention has been made in view of the above, and an object of the present invention is to provide a digital signal processing device that significantly reduces the scale of the entire processing device by processing data-compressed human input signals as they are. .

Means for Solving the Problems In order to solve the above problems, the present invention provides a convolution calculator in which input is compressed into a digital difference signal with a signal from a unit time ago, and is convolved with a weighting coefficient. It has an adder and a register, the output of the convolution operator is input to one of the adders, and the output of the adder itself and a unit time delay are input to the other via the register, and the output of the adder is is the final output.

Effect: With the above-described configuration, the present invention can directly perform arithmetic processing on a signal whose input is data compressed as a difference signal with a signal from a unit time ago. That is, by reducing the bit width of input data, the bit widths of the input circuit and the arithmetic circuit become smaller, resulting in a significant reduction in circuit scale.

Embodiment FIG. 1 is a block diagram showing an embodiment of the digital signal processing apparatus of the present invention. In FIG. 1, 1.2 is a line memory, 3 is a convolution arithmetic unit, 4 is an adder, and 5 is a register.

In Fig. 1, the input signal Q (x, y) is the input signal F (x, y) shown in Fig. 2 and the signal F (
The data is compressed by taking the difference from

Q(x,y)=F(x,y)-F(x-1+y)””■
Input Q(x,y) is converted into three lines of data by line memories 1 and 2, and input to a convolution calculator 3. The convolution arithmetic unit 3 is similar to the conventional example shown in FIG.
) Execute the convolution operation shown in the formula and obtain the output H(x, y)
get.

l...(3) Next, the output H(x, y) of the convolution operator 3 in FIG.
It is input to one side of the adder 4. The output Z (x, y) of the adder 4 is input to the other input of the adder 4 after being delayed by a unit time by the register 5 .

That is, the output Z (x, y) of the adder 4 is expressed by equation (4).

Z(x,y)-H(x,y)+Z(x-1,y)...
”...■ This Z (x, y) is extracted as the final output.

Here, the output H of the convolution operator 3 shown in equation (3)
When (x, y) is transformed using equations (1) and 0, it becomes as shown in equation (9).

−F(x−1+ i, y+jN =G (x, y)−G (x−1, y)・・・・・・(
ω Therefore, the final output Z (x, y) shown in formula ■ is (
6) It is shown by the formula.

Z (x, y) = G (x, y) - G (x - 1, y) + Z (
x-1, y) ... (6) Here, as an initial state, the convolution operator 3. And if adder 4 is controlled, equation (6) becomes Z (1, y) = G (1, y) - G (0, y) + Z (0,
y)=G(1,y) Z(2,y)=G(2,y)−G(1,y)+Z(1
,y)=G(2,y) Z(3,y)=G(3,y)−G(2,y)+Z(2
, y) = G (3, y) Z (X, Y) = G (X, y) ・
...Q) σ) formula, and from adder 4, (
It is possible to obtain the same result as the filtering processing result G(x,y) for the signal F(X,V) before data compression shown in equation 1).

That is, according to the present invention, an input signal whose data has been compressed by taking the difference with a signal before a unit time is directly convolved with a weighting coefficient, and the result is calculated once with an adder. By simply doing this, it is possible to obtain the same result as a conventional digital filter that performs a convolution operation on the signal before data compression.

Effects of the Invention As described above, according to the present invention, by directly performing filtering processing on a data-compressed signal, input circuits and arithmetic circuits are The purpose of the present invention is to provide a useful digital signal processing device whose scale can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a digital signal processing device of the present invention, and FIG. 2 is a block diagram of a conventional digital signal processing device. 1.2-3...Line memory, 3...Convolution operator, 4...Adder, 5...
register.

Claims (1)

[Claims] The input is given in time series in the form of a digital difference signal with a signal from a unit time ago, and has a convolution operator, an adder, and a register that performs a convolution operation of the digital difference signal and a weighting coefficient, A digital device characterized in that the output of the convolution operator is inputted to one side, the output of the adder itself delayed by a unit time via the register is inputted to the other side, and the output of the adder is used as the final output. Signal processing device.