JPH01319323A - Clock generation circuit for microprocessors - Google Patents
Clock generation circuit for microprocessorsInfo
- Publication number
- JPH01319323A JPH01319323A JP63152997A JP15299788A JPH01319323A JP H01319323 A JPH01319323 A JP H01319323A JP 63152997 A JP63152997 A JP 63152997A JP 15299788 A JP15299788 A JP 15299788A JP H01319323 A JPH01319323 A JP H01319323A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- clock
- output
- clock generation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 101150110971 CIN7 gene Proteins 0.000 description 1
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 1
- 101150110298 INV1 gene Proteins 0.000 description 1
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 1
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Landscapes
- Pulse Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
【産業上の利用分野１
本発明は、マイクロプロセッサに供給される、クロック
信号の生成回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a clock signal generation circuit supplied to a microprocessor.
従来の技術として、デユーティ比１対２の出力を生成す
る回路の例を第２図に示す、従来前記デユーティ比１対
２を実現する手段として、マイクロプロセッサ用クロッ
クの３倍の周波数を出力する発振回路（第２図Ｄ）と、
前記出力を３分周し、デユーティ比１対２とした出力を
生成する３分周回路Ｅを用いていた。As a conventional technique, an example of a circuit that generates an output with a duty ratio of 1:2 is shown in FIG. An oscillation circuit (Fig. 2D),
A divide-by-3 circuit E was used which divides the frequency of the output by three and generates an output with a duty ratio of 1:2.
［発明が解決しようとする課題］
しかし、従来の技術においては、目的とするマイクロプ
ロセッサ用クロックの、３倍またはそれ以上の周波数を
出力する発振回路と、前記周波数にて動作する分周回路
を必要とするため、高い周波数のマイクロプロセッサ用
クロックを生成するには技術的難かしさが存在した。[Problems to be Solved by the Invention] However, in the conventional technology, an oscillation circuit that outputs a frequency three times or more than that of the target microprocessor clock, and a frequency dividing circuit that operates at that frequency are required. Therefore, there are technical difficulties in generating high frequency microprocessor clocks.
本発明では、従来の問題点を解決するため、高い周波数
での動作が要求される回路を減らし、容易に実現可能な
マイクロプロセッサ用クロック生成回路を提供すること
を目的とする。In order to solve the conventional problems, it is an object of the present invention to reduce the number of circuits required to operate at high frequencies and to provide a clock generation circuit for a microprocessor that can be easily realized.
ｃ課題を解決するための手段］
上記課題を解決するため、本発明のクロック生成回路は
、目的とするマイクロプロセッサ用クロツクの２倍の周
波数を出力する発振回路と、前記出力を２分周する回路
及び遅延素子とゲート回路より成る、波形成形回路を有
し、非対称波形を得ることを特徴とする。c.Means for Solving the Problems] In order to solve the above problems, the clock generation circuit of the present invention includes an oscillation circuit that outputs twice the frequency of the target microprocessor clock, and a frequency division of the output by two. It is characterized by having a waveform shaping circuit consisting of a circuit, a delay element, and a gate circuit, and obtaining an asymmetric waveform.
〔実 施 例］
以下に本発明の実施例を図面に基づいて説明する。第１
図において、点線内Ａのブロックは、水晶振動子Ｘｉ、
ＣＭＯＳインバータゲートＩＮＶｌ、ＩＮＶ２、コンデ
ンサＣ１、Ｃ２及び抵抗Ｒ１からなる、水晶発振回路で
ありその発振周波数は主に、振動子ｘ１のもつ定数によ
り定まる。ここでは、ｘ１振動子は、マイクロプロセッ
サのクロック周波数の２倍の周波数を信号線Ｐｌに出力
するように選択されている。ブロックＢはＤ形フリップ
フロップを使用した２分周回路であり、出力Ｐ２は、周
波数がＰＩの２分の１であり、デユーティ比がｌ対ｌの
、対称な波形が得られる。ブロックＣは、遅延素子ｄｅ
ｌａｙ−１及び負論理型のＯＲゲートより成る波形成形
回路である６本実施例は、クロック出力の”Ｌｏｗ“レ
ベルパルス幅を拡張した場合を示した。この回路におい
て、入力信号Ｐ２が周期Ｔ （ｓｅｃ）、デユーティ比
１対ｌであり、遅延素子ｄｅｌａｙ−１の有する遅延時
間がｔ （ｓｅｃ）の時、出力Ｐ４の”Ｈｉｇｈ”レベ
ルパルス幅は、Ｔ／２−ｔ（ｓｅｃ）、又″Ｌｏｗ”レ
ベルパルス幅はＴ／２＋ｔ （ｓｅｃ）で示され、結果
としてデユーティ比が（Ｔ／２−ｔ）対（Ｔ／２＋ｔ）
の非対称クロック波形が出力される。ここで遅延素子の
遅延時間をクロック周期Ｔの約１７％とすることにより
、出力Ｐ４には、デユーティ比１対２の非対称クロック
を得ることができる。[Example] Examples of the present invention will be described below based on the drawings. 1st
In the figure, the block A within the dotted line is a crystal oscillator Xi,
This is a crystal oscillation circuit consisting of CMOS inverter gates INV1, INV2, capacitors C1, C2, and resistor R1, and its oscillation frequency is mainly determined by the constant of the vibrator x1. Here, the x1 oscillator is selected to output a frequency twice the clock frequency of the microprocessor to the signal line Pl. Block B is a divide-by-2 circuit using a D-type flip-flop, and the output P2 has a frequency that is one-half of PI, and a symmetrical waveform with a duty ratio of 1 to 1 is obtained. Block C includes a delay element de
The sixth embodiment, which is a waveform shaping circuit consisting of a lay-1 and a negative logic type OR gate, shows a case where the "Low" level pulse width of the clock output is expanded. In this circuit, when the input signal P2 has a period T (sec) and a duty ratio of 1:1, and the delay time of the delay element delay-1 is t (sec), the "High" level pulse width of the output P4 is: T/2-t (sec), and the "Low" level pulse width is expressed as T/2+t (sec), resulting in a duty ratio of (T/2-t) versus (T/2+t).
An asymmetric clock waveform is output. By setting the delay time of the delay element to about 17% of the clock period T, an asymmetric clock with a duty ratio of 1:2 can be obtained at the output P4.
〔発明の効果１
以上示したように、本発明においては、水晶発振回路に
要求される周波数がマイクロプロセッサのクロックの２
倍で済むという利点を有し、発振回路の上限周波数が同
一であるならば、従来の技術と比較し、より高い周波数
のマイクロプロセッサ用クロックを作成可能という利点
を有する。[Effect of the invention 1] As shown above, in the present invention, the frequency required for the crystal oscillation circuit is twice as high as the clock of the microprocessor.
It has the advantage that it only requires twice as much time, and if the upper limit frequency of the oscillation circuit is the same, it has the advantage that it is possible to create a clock for a microprocessor with a higher frequency than the conventional technology.
また、同一周波数のマイクロプロセッサ用クロックを作
成するための、発振回路の出力周波数が低くて良いとい
うことは、電子装置からの不要な電波輻射を減少させ、
他の機器の雑音源となる可能性を減少させるという点で
も、利点を有する。In addition, the fact that the output frequency of the oscillation circuit to create a microprocessor clock of the same frequency can be low reduces unnecessary radio wave radiation from electronic devices.
It also has the advantage of reducing the possibility of becoming a noise source for other equipment.
第１図は、本発明の実施例を示す図。 第２図は、従来技術による回路例を示す図。 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 鈴 木 喜三部（他１名）第１図 FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an example of a circuit according to the prior art. that's all Applicant: Seiko Epson Corporation Agent: Patent attorney Kisanbe Suzuki (and 1 other person) Figure 1
Claims (1)
周回路を有するマイクロプロセッサ用クロック生成回路
において、前記分周回路を２分周としその出力を遅延素
子とゲート回路を用いた波形成形回路を通加させること
により、非対称なクロック波を生成することを特徴とす
るマイクロプロセッサ用クロック生成回路。In a clock generation circuit for a microprocessor having an oscillation circuit using a crystal resonator and a frequency dividing circuit for the output of the oscillation circuit, the frequency of the frequency dividing circuit is divided by two, and the output thereof is waveform-shaped using a delay element and a gate circuit. A clock generation circuit for a microprocessor, characterized in that it generates an asymmetric clock wave by applying current to the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152997A JPH01319323A (en) | 1988-06-21 | 1988-06-21 | Clock generation circuit for microprocessors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63152997A JPH01319323A (en) | 1988-06-21 | 1988-06-21 | Clock generation circuit for microprocessors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01319323A true JPH01319323A (en) | 1989-12-25 |
Family
ID=15552697
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63152997A Pending JPH01319323A (en) | 1988-06-21 | 1988-06-21 | Clock generation circuit for microprocessors |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01319323A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309034A (en) * | 1991-05-28 | 1994-05-03 | Sharp Kabushiki Kaisha | Timer circuit for stretching the duration of an input pulse |
| JP2010220249A (en) * | 2003-07-31 | 2010-09-30 | Qualcomm Inc | Delay matching for clock distribution in logic circuit |
-
1988
- 1988-06-21 JP JP63152997A patent/JPH01319323A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309034A (en) * | 1991-05-28 | 1994-05-03 | Sharp Kabushiki Kaisha | Timer circuit for stretching the duration of an input pulse |
| JP2010220249A (en) * | 2003-07-31 | 2010-09-30 | Qualcomm Inc | Delay matching for clock distribution in logic circuit |
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