JPH01319902A - Chip resistor - Google Patents
Chip resistorInfo
- Publication number
- JPH01319902A JPH01319902A JP63153917A JP15391788A JPH01319902A JP H01319902 A JPH01319902 A JP H01319902A JP 63153917 A JP63153917 A JP 63153917A JP 15391788 A JP15391788 A JP 15391788A JP H01319902 A JPH01319902 A JP H01319902A
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- base material
- chip resistor
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- firing
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- Non-Adjustable Resistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 産業上の利用分野 本発明はチップ型固定抵抗器に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to a chip type fixed resistor.
従来の技術
近年、電子機器の軽薄短小化に対する要求がますます増
大していく中、回路基板の配線密度を高めるため、固定
抵抗器には非常に小型なチップ抵抗器が多く用いられる
ようになってきた。Conventional technology In recent years, with the increasing demand for electronic devices to be lighter, thinner, and smaller, extremely small chip resistors are increasingly being used as fixed resistors in order to increase the wiring density of circuit boards. It's here.
従来の小型のチップ抵抗器の構造を、第3図に示す。(
工業調査会発行最新サーフヱイスマウントテクノロジー
p27〜p33)
従来の小型のチップ抵抗器は焼成済みの96アルミナ基
板6による基材と、ムg系厚膜電極による上面電極層7
と端面電極層8、上面電極層7の一部に重なるルテニウ
ム系厚膜抵抗による抵抗層9と、抵抗層を覆うホウケイ
酸鉛系のガラスによる絶縁ガラスパターン層10からな
っている。なお露出電極面には半田付は性を向上させる
ためにN1と5n−Pbメツキ層を電解メツキにより施
している。The structure of a conventional small chip resistor is shown in FIG. (
Latest Surf Is Mount Technology published by Kogyo Kenkyukai p27-p33) Conventional small chip resistors have a base material made of a fired 96 alumina substrate 6 and a top electrode layer 7 made of a mug-based thick film electrode.
It consists of an end surface electrode layer 8, a resistance layer 9 made of a ruthenium-based thick film resistor that overlaps a part of the top electrode layer 7, and an insulating glass pattern layer 10 made of lead borosilicate glass that covers the resistance layer. Note that N1 and 5n-Pb plating layers are electrolytically plated on the exposed electrode surface to improve solderability.
発明が解決しようとする課題
しかし、従来の小型のチップ抵抗器は焼成済みの96ア
ルミナ基板を基材としていたため、上面電極層と端面電
極層はλg系電極ペースト中のガラス成分の溶融によっ
てのみ9eアルミナ基板に焼き付けられていた。このた
め、上面電極層と端面電極層の接着強度が弱いといった
問題があった。Problems to be Solved by the Invention However, since conventional small chip resistors were based on fired 96 alumina substrates, the top electrode layer and end electrode layer could only be formed by melting the glass component in the λg-based electrode paste. It was baked onto a 9e alumina substrate. Therefore, there was a problem in that the adhesive strength between the top electrode layer and the end electrode layer was weak.
本発明は、このような問題点を解決するもので、96ア
ルミナ基板と上面電極層、端面電極層の接着強度の強化
を目的とする。The present invention solves these problems and aims to strengthen the adhesive strength between the 96 alumina substrate, the top electrode layer, and the end electrode layer.
課題を解決するための手段
本発明のチップ抵抗器は、人2□0./ホウケイ酸鉛系
ガラス比が40/6o〜e o / 40の低温焼成セ
ラミックを基材とし、前記基材と同時焼成することによ
り形成されたAg系厚膜電極を導体電極とし、前記導体
電極の一部て重なり、前記基材と同時焼成することによ
り形成されたルテニウム系厚膜抵抗を抵抗層とするよう
に構成するものである。Means for Solving the Problems The chip resistor of the present invention has a capacity of 2□0. A conductor electrode is an Ag-based thick film electrode formed by co-firing a low-temperature fired ceramic with a lead/borosilicate glass ratio of 40/6 o to e o/40 as a base material, and is co-fired with the base material. A ruthenium-based thick film resistor formed by partially overlapping with the base material and co-fired with the base material is used as a resistance layer.
作用
これにより、基材となっている低温焼成セラミックと上
面電極層、端面電極層の接着強度の強化を実現すること
ができる。As a result, it is possible to strengthen the adhesive strength between the low-temperature fired ceramic that is the base material, the top electrode layer, and the end electrode layer.
実施例
以下、本発明の実施例1について、第1図を用いて説明
する。EXAMPLE Hereinafter, Example 1 of the present invention will be explained using FIG. 1.
v、1図において、本発明のチップ抵抗器は、Al2O
3/ホウケイ酸鉛系ガラス比が40/6o〜80 /
40の低温焼成セラミック基板1を基材とし、前記低温
焼成のセラミック基板1と同時に焼成することによシ形
成されたλg系厚電極を上面電極層2と端面電極層3と
し、前記上面電極層2の一部に重なり、前記低温焼成セ
ラミック基板1と同時焼成することにより形成されたル
テニウム系厚膜抵抗を抵抗層4とし、さらに抵抗層4の
保護層としてホウケイ酸鉛ガラ2分、前記低温焼成セラ
ミック基板1と個別に焼成したものを絶縁ガラスパター
ン層5としたものである。v, 1, the chip resistor of the present invention is made of Al2O
3/Lead borosilicate glass ratio is 40/6o~80/
40 low-temperature-fired ceramic substrate 1 as a base material, λg-based thick electrodes formed by firing simultaneously with the low-temperature-fired ceramic substrate 1 are used as a top electrode layer 2 and an end electrode layer 3, and the top electrode layer 2, a ruthenium-based thick film resistor formed by co-firing with the low temperature fired ceramic substrate 1 is used as the resistance layer 4, and as a protective layer for the resistance layer 4, 2 parts of lead borosilicate glass and the low temperature The insulating glass pattern layer 5 is formed by firing separately from the fired ceramic substrate 1.
まず、実施例1に用いた、ホウケイ酸鉛系ガラスの組成
を表1に−示す。First, Table 1 shows the composition of the lead borosilicate glass used in Example 1.
(以下余白)
表 1
このホウケイ酸鉛系ガラスを白金のルツボに入れて、1
000℃で3時間攪拌しつつ加熱溶融した。次に、これ
を水砕し、さらに粉砕器により平均粒径2μm〜3μm
になるように粉砕した。−方、純度98%以上のム12
03粉を粉砕器により平均粒径3μm〜4μmになるよ
うに粉砕した。(Left below) Table 1 This lead borosilicate glass was placed in a platinum crucible and 1
The mixture was heated and melted at 000°C for 3 hours with stirring. Next, this is pulverized and further milled to an average particle size of 2 μm to 3 μm.
It was crushed to look like this. - Mu12 with a purity of 98% or more
03 powder was pulverized using a pulverizer to have an average particle size of 3 μm to 4 μm.
次いでこれらのAJ205粉末と、ガラス粉末を表2の
割合で混合し、本発明による3種類の組成物(人〜C)
を得た。次いで、この組成物知アクリル系の有機バイン
ダーを添加し、24時間混練することにより、スラリー
状にした。次いでこれとドクターブレードを用いて幅2
0cm+厚さ0.5 mmのシートにし、乾燥後50
rrrm X 2 rranの大きさに切断した。Next, these AJ205 powders and glass powders were mixed in the proportions shown in Table 2, and three types of compositions according to the present invention (Human to C) were prepared.
I got it. Next, an acrylic organic binder was added to this composition, and the mixture was kneaded for 24 hours to form a slurry. Next, use this and a doctor blade to make a width of 2
Make a sheet of 0cm + 0.5mm thick and dry it for 50 minutes.
It was cut into a size of rrrm x 2 rran.
次いで、この上にAg系導体ペーストをスクリーン印刷
し、Ag系導体ペーストを端面にローラーによって塗布
し乾燥後した後に、更にルテニウム系抵抗ペーストをス
クリーン印刷し乾燥した。Next, an Ag-based conductor paste was screen-printed on top of this, the Ag-based conductor paste was applied to the end face with a roller, and after drying, a ruthenium-based resistance paste was further screen-printed and dried.
この後、前記印刷物、を空気中で脱パイ温度450℃・
ピーク温度900℃で1時間脱パイ・1時間焼成を行い
、低温焼成セラミック基板1と上面電極層2と端面電極
層3と抵抗層4を同時に形成した。After that, the printed matter was de-piped in air at a temperature of 450°C.
Depyrining and firing were performed for 1 hour at a peak temperature of 900° C. to form a low-temperature fired ceramic substrate 1, a top electrode layer 2, an end electrode layer 3, and a resistance layer 4 at the same time.
次いで、抵抗値修正のためにレーザートリミングを行っ
た。更にこの後、低融点のホウケイ酸鉛系ガラスペース
トeスクリーン印刷し、空気中で500℃・1時間焼成
を行い絶縁ガラスパターン層5を形成した(なお露出電
極面には半田付は性を向上させるためにNiと5n−P
bメツキ層を電解メツキにより施している)。これらの
チップ抵抗器について、ムg電極の電極接着強度、抵抗
温度係数(TCtR)、素子の変形度合を知るため素子
の反りを測定した。これらの結果を表2に記載した。Next, laser trimming was performed to correct the resistance value. Furthermore, after this, an insulating glass pattern layer 5 was formed by e-screen printing a low melting point lead borosilicate glass paste and baking it in air at 500°C for 1 hour (note that soldering on the exposed electrode surface improves the properties). Ni and 5n-P to
The plating layer b is applied by electrolytic plating). Regarding these chip resistors, the warpage of the element was measured in order to determine the electrode adhesion strength of the mug electrode, temperature coefficient of resistance (TCtR), and degree of deformation of the element. These results are listed in Table 2.
比較例として、本発明の組成物以外のものについて同様
のテストを行ったのでその結果も同様に記載した。なお
、各特性の測定方法は、次に示す通りである。As a comparative example, similar tests were conducted on compositions other than those of the present invention, and the results are also described in the same manner. The method for measuring each characteristic is as follows.
電極接着強度
チップ抵抗器をプリント基板に実装し、ブツシュデルゲ
ージにより引っ張り試験を行い、チップ抵抗器の電極が
剥離したときの強度を測定し、その値を1圏 当たりの
値に換算したものを、電極接着強度と定義した。Electrode adhesion strength A chip resistor is mounted on a printed circuit board, a tensile test is performed using a Butschdel gauge, the strength is measured when the electrode of the chip resistor peels off, and the value is converted to a value per area. was defined as the electrode adhesion strength.
抵抗温度係数(TCR)
チップ抵抗器をプリント基板に実装し、25℃での抵抗
値を測定しく R25)、その後、126℃雰囲気に1
0分間放置後、その雰囲気中で抵抗値を測定しくR12
5)、次の式で計算した値を抵抗温度係数(TCR)と
定義する。Temperature Coefficient of Resistance (TCR) Mount the chip resistor on a printed circuit board and measure the resistance value at 25℃ (R25), then place it in a 126℃ atmosphere for 1 hour.
After leaving it for 0 minutes, measure the resistance value in that atmosphere.R12
5) The value calculated using the following formula is defined as the temperature coefficient of resistance (TCR).
チップ抵抗器の反り
次の式で計算したものをチップ抵抗器の反りと定義する
。Warpage of a chip resistor The warpage of a chip resistor is calculated using the following formula.
チップ抵抗器の反り=チップ抵抗器の全厚みm−極層の
厚さ一抵抗層の厚さ一絶縁ガラスパターン層の厚さ一低
温焼結基板の基板厚さ
表、2
表2より明らかなように、本発明によるものは電極接着
強度が大きく、TCR,チップ抵抗の反りの面でもすぐ
れている。Warpage of chip resistor = Total thickness of chip resistor m - Thickness of pole layer - Thickness of resistance layer - Thickness of insulating glass pattern layer - Substrate thickness of low temperature sintered substrate Table, 2 It is clear from Table 2 As can be seen, the device according to the present invention has high electrode adhesion strength and is excellent in terms of TCR and chip resistance warpage.
基材のムJ 20 s /ホウケイ酸鉛系ガラス比が4
゜/50より小さいと(ガラス成分が多い)、焼成時に
基材中のガラス成分の抵抗層へのしみ出しが激しくなり
、TCHの悪化を招く。また基材のλB2O5/ホウケ
イ酸鉛系ガラス比が50 / 40より多くなると、チ
ップ抵抗器の反りが発生する。The base material's MuJ20s/lead borosilicate glass ratio is 4.
If it is smaller than .degree./50 (the glass component is large), the glass component in the base material will seep out into the resistance layer during firing, leading to deterioration of TCH. Moreover, when the ratio of λB2O5/lead borosilicate glass of the base material exceeds 50/40, warping of the chip resistor occurs.
次に、本発明による実施例2について説明する。Next, Example 2 according to the present invention will be described.
実施例2においては、表1のホウケイ酸鉛系ガラスの組
成を変化させて3種類のホウケイ酸鉛系ガラス粉末(D
−F)を作製し、この組成物に、人120 s /ホウ
ケイ酸鉛系ガラス比が50 / 50になるように、ム
β20.粉末を混合し、この組成物にアクリル系の有機
バインダーを添加し、24時間混練することにより、ス
ラリー状にした。次いでこれをドクターブレードを用い
て幅20 CWL r厚さ0.5 mmのシートにし、
乾燥後50mX2mの大きさに切断した。In Example 2, three types of lead borosilicate glass powders (D
-F) was prepared, and this composition was mixed with Mu β20. The powders were mixed, an acrylic organic binder was added to the composition, and the mixture was kneaded for 24 hours to form a slurry. Next, this was made into a sheet with a width of 20 CWL and a thickness of 0.5 mm using a doctor blade.
After drying, it was cut into a size of 50 m x 2 m.
次いで、この上KAg系導体ペーストをスクリーン印刷
し、λg系導体ペーストを端面にローラーによって塗布
し乾燥後した後に、更にルテニウム系抵抗ペーストをス
クリーン印刷し乾燥した。Next, a KAg-based conductor paste was screen-printed on top of this, a λg-based conductor paste was applied to the end face with a roller, and after drying, a ruthenium-based resistance paste was further screen-printed and dried.
この後、前記印刷物を空気中で脱パイ温度450℃・ピ
ーク温度800’C〜10oo℃で1時間脱パイ・1時
間焼成を行い低温焼成セラミック基板1と上面電極層2
と端面電極層3と抵抗層4を同時に形成した。Thereafter, the printed matter was de-piped and fired for 1 hour in air at a de-piping temperature of 450°C and a peak temperature of 800'C to 1000°C for 1 hour, thereby forming a low-temperature fired ceramic substrate 1 and a top electrode layer 2.
The end face electrode layer 3 and the resistance layer 4 were formed simultaneously.
次いで、抵抗値修正のためにレーザートリミングを行っ
た。更にこの後、低融点のホウケイ酸鉛系ガラスペース
トをスクリーン印刷し、空気中でeoo℃・1時間焼成
を行い絶縁ガラスパターン層6を形成した(なお露出電
極面には半田付は性を向上させるためにN1と5n−P
bメツキ層を電解メツキに゛より施している)。これら
のチップ抵抗器について、基材の抗折強度とTCRを測
定した。これらの結果を表3に記載した。Next, laser trimming was performed to correct the resistance value. Furthermore, after this, a low melting point lead borosilicate glass paste was screen printed and baked in air at 00°C for 1 hour to form an insulating glass pattern layer 6 (note that soldering on the exposed electrode surface improves properties) N1 and 5n-P to make
b) The plating layer is applied by electrolytic plating). For these chip resistors, the flexural strength and TCR of the base material were measured. These results are listed in Table 3.
比較例として、本発明の組成物以外、焼成温度8oo℃
〜1000℃以外のものについて同様のテス)&行った
のでその結果も表3に記載した。As a comparative example, other than the composition of the present invention, the firing temperature was 80°C.
Similar tests were conducted for temperatures other than ~1000°C, and the results are also listed in Table 3.
なお、抗折強度の測定方法は、次に示す通りである。Note that the method for measuring the bending strength is as shown below.
抗折強度 抗折強度は第2図に示すような治具を用いて測定した。bending strength The bending strength was measured using a jig as shown in FIG.
すなわち、チップ抵抗器11を治具13の凹み13a上
に橋渡しするように置き、そしてチップ抵抗器11をプ
ッシュプルゲージ12で押した。チップ抵抗器が破壊し
たときの強度を抗折強度と定義する。That is, the chip resistor 11 was placed so as to bridge the recess 13a of the jig 13, and the chip resistor 11 was pushed with the push-pull gauge 12. The strength when a chip resistor breaks is defined as the bending strength.
C以下余白)
表 3
表3よシ明らかなように、基材中のホウケイ酸鉛系ガラ
スのガラス転移点が550°C未満になると、脱バイン
ダプロセス中にガラスが軟化を始め、十分な脱パイが出
来なくなり、基材が非常にポーラスとなりチップ抵抗器
の抗折強度が小さくなる。Table 3 As is clear from Table 3, when the glass transition point of the lead borosilicate glass in the base material becomes less than 550°C, the glass begins to soften during the debinding process, and sufficient debinding is not achieved. As a result, the base material becomes extremely porous and the bending strength of the chip resistor decreases.
また、基材中のホウケイ酸鉛系ガラスのガラス転移点が
650℃を超えると、1000℃以下での十分な焼成が
できなくなり、同様にチップ抵抗器の抗折強度が小さく
なる。Furthermore, if the glass transition point of the lead borosilicate glass in the base material exceeds 650°C, sufficient firing at 1000°C or lower will not be possible, and the bending strength of the chip resistor will similarly decrease.
また、焼成温度が800’C未満で焼成したチップ抵抗
器は焼結不足のため基材の抗折強度が低下し、逆に、1
000℃を超えると、抵抗層が過焼結となり、抵抗性能
(TCR)が劣化する。従って、焼成温度は800°C
〜1000°Cの範囲が相応しい。In addition, chip resistors fired at a firing temperature of less than 800'C have a lower bending strength of the base material due to insufficient sintering.
When the temperature exceeds 000° C., the resistance layer becomes oversintered and the resistance performance (TCR) deteriorates. Therefore, the firing temperature is 800°C
A range of ~1000°C is suitable.
なお、実施例1,2においては、ホウケイ酸鉛系ガラス
は表1に示す組成にしたが、ガラス転移点が550℃〜
650℃のホウケイ酸鉛系ガラスならなんでも良い。ま
た、ガラス粉はさらに粉砕器により平均粒径2μm〜3
μmになるように粉砕したが、平均粒径を限定するもの
ではない。−方、純度98%以上のム1205粉を粉砕
器により平均粒径3μm〜4μmVCなるように粉砕し
たが、これも同様に、平均粒径を限定するものではない
。In Examples 1 and 2, the lead borosilicate glass had the composition shown in Table 1, but the glass transition point was 550°C ~
Any lead borosilicate glass with a temperature of 650°C may be used. In addition, the glass powder is further processed into a pulverizer with an average particle size of 2 μm to 3 μm.
Although the particles were ground to a particle size of μm, the average particle size is not limited. - On the other hand, Mu1205 powder with a purity of 98% or more was pulverized using a pulverizer to give an average particle size of 3 μm to 4 μm VC, but this also does not limit the average particle size.
また、シートに成型するのに1 ドクターブレードを用
いているが、これは押し出し成型法などの別の方法でも
良い。また、実施例1においては抵抗層の保護層として
絶縁ガラスを用いているが、これは、樹脂系のコート材
料でも良い。Furthermore, although a single doctor blade is used to form the sheet, other methods such as extrusion molding may also be used. Further, although insulating glass is used as the protective layer of the resistance layer in Example 1, a resin-based coating material may be used instead.
発明の効果
以上の説明から明らかなように本発明は、人7!203
/ホウケイ酸鉛系ガラス比が40 / 50〜50/4
oの低温焼成セラミックを基材とし、前記基材と同時焼
成することにより形成されたAg系厚膜電極を導体電極
とし、前記導体電極の一部に重なり、前記基材と同時焼
成することによシ形成されたルテニウム系厚膜抵抗を抵
抗層とするように構成されているので、基材となってい
る低温焼成セラミックと上面電極層、端面電極層の接着
強度の強化といった優れた効果が得られる。Effects of the Invention As is clear from the above explanation, the present invention
/Lead borosilicate glass ratio is 40/50 to 50/4
A low-temperature fired ceramic of o is used as a base material, an Ag-based thick film electrode formed by co-firing with the base material is used as a conductor electrode, overlaps a part of the conductor electrode, and is co-fired with the base material. Since it is constructed using a well-formed ruthenium-based thick film resistor as the resistance layer, it has excellent effects such as strengthening the adhesive strength between the low-temperature fired ceramic base material, the top electrode layer, and the end electrode layer. can get.
第1図は本発明のチップ抵抗器の構造を示す断面図、第
2図は抗折強度の測定方法を示す概略図、第3図は従来
の小型のチップ抵抗器の構造を示す断面図である。
1・・・・・・低温焼成セラミック基板、2・・・・・
・上面電極層、3・・・・・・端面電極層、4・・・・
・・抵抗層、5・・・・・・絶縁ガラスパターン層。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名1−
−ft!、湛1成℃ラミ・ツク墨擾2− よatw層
3− 塙 i 電母屑
l
第2図Figure 1 is a sectional view showing the structure of the chip resistor of the present invention, Figure 2 is a schematic diagram showing the method for measuring bending strength, and Figure 3 is a sectional view showing the structure of a conventional small chip resistor. be. 1...Low temperature firing ceramic substrate, 2...
・Top electrode layer, 3... End electrode layer, 4...
...Resistance layer, 5...Insulating glass pattern layer. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
-ft! , 1st generation ℃ Rami Tsuku ink 2- yo atw layer 3- Hanawa i Electron mother dust l Fig. 2
Claims (2)
/60/40の低温焼成セラミックを基材 とし、前記基材と同時焼成することにより形成されたA
g系厚膜電極を導体電極とし、前記導体電極の一部に重
なり、前記基材と同時焼成することにより形成されたル
テニウム系厚膜抵抗を抵抗層としたことを特徴とするチ
ップ抵抗器。(1) Al_2O_3/lead borosilicate glass ratio is 40
/60/40 low temperature fired ceramic as a base material, A formed by co-firing with the base material.
1. A chip resistor characterized in that a g-based thick film electrode is used as a conductor electrode, and a ruthenium-based thick film resistor that overlaps a part of the conductor electrode and is formed by co-firing with the base material is used as a resistance layer.
550℃〜650℃、基材の焼成温度が800℃〜10
00℃であることを特徴とする請求項1記載のチップ抵
抗器。(2) The glass transition point of the lead borosilicate glass in the base material is 550°C to 650°C, and the firing temperature of the base material is 800°C to 10°C.
The chip resistor according to claim 1, characterized in that the temperature is 00°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63153917A JPH01319902A (en) | 1988-06-22 | 1988-06-22 | Chip resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63153917A JPH01319902A (en) | 1988-06-22 | 1988-06-22 | Chip resistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01319902A true JPH01319902A (en) | 1989-12-26 |
Family
ID=15572922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63153917A Pending JPH01319902A (en) | 1988-06-22 | 1988-06-22 | Chip resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01319902A (en) |
-
1988
- 1988-06-22 JP JP63153917A patent/JPH01319902A/en active Pending
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