JPH01320870A - Synchronizing controller for tv - Google Patents

Abstract

PURPOSE:To prevent output of many vertical signals even at the time of drop- out of a vertical synchronizing signal by adding plural reset value setting horizontal programmable logic arrays(PLA) and a free running reset signal changeover switch. CONSTITUTION:A phase comparator 2, an LPF 3, and a VCO 4 constitute a PLL. A horizontal counter 5 receives the output of the VCO 4 to give an address of a horizontal PLA 7, and a clock of a vertical counter 9 is generated by a 1/2 frequency divider 6. The vertical counter 9 outputs a signal to give an address of a vertical PLA 10. A generating circuit 12 of a reset signal to reset the vertical counter 9 resets the vertical counter 9. When the vertical synchronizing pulse is not outputted from a synchronizing signal separating circuit 1 or vertical synchronization is delayed because of rewinding and playback or the like of a VTR, the signal from a first or second reset value setting PLA 13 or 14 is used as the reset signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a TV synchronization controller, and in particular to a TV synchronization controller that has a function of resetting a vertical counter using a value set in a programmable logic array when a vertical synchronization signal is lost.
This invention relates to a synchronous controller for V.

[Conventional technology]

Conventionally, this type of TV controller uses a programmer full logic array (hereinafter referred to as PLA) to determine the value to reset the vertical counter when the vertical synchronization signal is lost.
It has -.

FIG. 2 is a block diagram of a TV synchronous controller for explaining an example of such a conventional system.

As shown in FIG. 2, the conventional TV synchronization controller includes a synchronization separation circuit 1 that separates horizontal and vertical synchronization pulses consisting of a video signal, and a synchronization separation circuit 1 that separates horizontal and vertical synchronization pulses from a video signal. Phase comparator for synchronizing 2. Phase-locked loop (PLL) consisting of 3 low-pass filters (LPF) and 4 voltage-controlled oscillators (VCO)
circuit, a horizontal counter 5 that counts the basic clock transmitted by the VCO 4, a 1/2 frequency divider 6 that receives the output of the horizontal counter 5 and creates a signal for one horizontal synchronization to the phase comparator 2, and a horizontal A vertical counter 9 that counts the horizontal pulses output from the counter 5, horizontal and vertical PLAs 7 and 10 that specify the rising and falling positions of the horizontal and vertical output signals, respectively, and A flip-flop 8°11 is connected to J- for horizontal and vertical outputs to create horizontal and vertical output signals.
A reset signal generation circuit 2 generates a signal for resetting the vertical counter 9 using the vertical synchronization pulse from the sync separation circuit 1, and a reset signal generation circuit 12 generates a reset signal based on the output of the vertical counter 9. and a reset value setting PLA 13 for setting a reset value.

[Problem to be solved by the invention]

The conventional TV synchronization controller described above has no PLAIO, which determines the value to reset the vertical counter 9 when the vertical synchronization signal is lost, so the vertical period may change due to VTR rewind playback, etc. If the vertical synchronization signal is delayed and enters after the set value of the reset value setting PLA 13, the vertical counter 9 will be reset twice, resulting in the disadvantage that two vertical system outputs with small addresses will be output.

SUMMARY OF THE INVENTION An object of the present invention is to provide a TV synchronization controller that prevents a large number of vertical signals from being output even when a vertical synchronization signal is lost.

[Means to solve the problem]

The TV synchronization controller of the present invention includes a synchronization separation circuit that separates horizontal and vertical synchronization pulses from a video signal;
A PLL circuit consisting of a phase comparator, an LPF, and a VCO for synchronizing the separated horizontal synchronizing pulse with the input video signal, a horizontal counter that counts the basic clock oscillated by the vCO, and an output from the horizontal counter. a vertical counter that counts horizontal pulses, horizontal and vertical PLAs that specify the rising and falling positions of the horizontal and vertical output signals, respectively, and horizontal and vertical output signals that are calculated based on the outputs of these PLAs. a flip-flop for the horizontal and vertical output J- to be created; a reset signal creation circuit that creates a signal for resetting the vertical counter by the vertical synchronization pulse from the synchronization separation circuit; In the TV synchronous controller, the TV synchronous controller has a reset value setting PLA that sets a rectangular reset value for creating a reset signal from a reset signal creation circuit, and a first and second PLA that sets a plurality of reset values of the vertical counter. A switch is provided to change these reset values depending on the status of the input video signal, and the configuration is configured to prevent disturbances in the vertical output signal due to fluctuations in the vertical period of the video signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram of a TV synchronous controller for explaining one embodiment of the present invention.

As shown in FIG. 1, a synchronization separation circuit 1 in the Gagaru controller receives an external video signal and outputs horizontal synchronization pulses and vertical synchronization pulses. Among these, the phase of the horizontal synchronizing pulse and one horizontal synchronizing signal are compared by a comparator 2, and the output thereof is sent to the VCO 4 via the LPF 3. Note that this phase comparator 2, LPF 3, and vCO4 form a PLL (face-locked loop). This vCO4 oscillates a clock that matches the resolution of the horizontal output signal, so the horizontal counter 5
The oscillation output of
Create a clock (a signal whose period is 1/2 that of the horizontal pulse). Horizontal system PLAY generates pulses corresponding to the rising and falling addresses of the horizontal system output signal, so this is sent to horizontal output J- by flip-flop 8, so that the position from the rising pulse to the falling pulse is at high level. Outputs the horizontal signal. Incidentally, the phase comparator 2 described above. LPF3. The vCO 4 includes a horizontal counter 5 and a 1/2 frequency divider 6 to form a phase-locked loop to synchronize the external video signal and the output signal.

On the other hand, as in the horizontal system, the vertical counter 9 is the horizontal counter 5.
(a signal whose period is 1/2 of the horizontal pulse) and outputs a signal giving the address of the vertical system PLAIO. This vertical system PLA 10 outputs pulses corresponding to the rising and falling addresses of the vertical system output signal, so these are sent to the vertical output J- through the flip-flop 1.
1 outputs a vertical signal in which the position from the rising pulse to the falling pulse becomes high level.

Here, in the reset signal generation circuit 12 that resets the vertical counter 9, the vertical counter 9 is normally reset by the vertical synchronization pulse separated by the synchronization separation circuit 1, but due to a weak electric field etc. If no pulse is output, the first reset value setting PL
Reset with the signal from A13. However, if an external vertical synchronizing pulse is input first, the reset by the pulse from the reset value setting PLA 13 is not performed. Further, if the vertical synchronization is delayed due to rewinding the winding of the VTR or playback, etc., this is done by switching the reset value changeover switch 15, and the above-mentioned operation is performed by a signal from the second reset value setting PLA 14. Normally, the first reset value setting PLA 13 has a count number corresponding to one vertical period (525 in the international TV transmission system: NTSC system), and the second reset value setting PLA 14 has a delay rate of vertical period N. %, the value x(1+N/100) of the first reset value setting PLA is set.

〔Effect of the invention〕

As explained above, the TV synchronous controller of the present invention includes a plurality of reset value setting PLAs and a self-running reset signal changeover switch, so that vertical synchronization is delayed during special playback of a VTR, etc. This has the effect of preventing disturbances such as two vertical signals being output by switching the free-running reset value even when the system is in use.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a TV synchronous controller for explaining an embodiment of the present invention, and FIG. 2 is a block circuit diagram of a TV synchronous controller for explaining a conventional example. -9 = 1...Synchronization separation circuit 1.2...Phase comparator, 3...
・Low pass filter (LPF), 4... Voltage controlled oscillator (vCO), 5... Horizontal counter, 6... 1/2
Frequency divider, 7...Horizontal programmable logic array (P
LA), 8...Flip-flop in J- for horizontal output, 9...Vertical counter, 10...Vertical programmable logic array (PLA), 11...J- for vertical output
a flip-flop, 12... a reset signal generation circuit, 13... a first reset value setting PLA, 14...
・Second reset value setting PLA, 15...Switch for changing reset value. 21ha〇-

Claims (1)

[Claims] A synchronization separation circuit that separates horizontal and vertical synchronization pulses from a video signal, a phase comparator, and an LPF for synchronizing the separated horizontal synchronization pulses with an input video signal.
and a PLL circuit consisting of a VCO, a horizontal counter that counts the basic clock oscillated by the VCO, a vertical counter that counts horizontal pulses output from the horizontal counter, and rising and rising edges of horizontal and vertical output signals. A horizontal and vertical PLA that specifies the downstream position, a J-K flip-flop for horizontal and vertical outputs that creates horizontal and vertical output signals based on the outputs of these PLAs, and a vertical output signal from the sync separation circuit. A reset signal generation circuit that generates a signal to reset the vertical counter using a synchronization pulse, and a reset value setting circuit that sets a reset value for generating a reset signal from the first reset signal generation circuit based on the output of the vertical counter. In a TV synchronous controller having a PLA,
A first and second PLA for setting a plurality of reset values of the vertical counter, and a switch for switching these reset values according to the status of the input video signal are provided, and the vertical system output signal is controlled by the fluctuation of the vertical period of the video signal. A TV synchronous controller characterized by preventing disturbances.