JPH01321382A - Test circuit for mos transistor - Google Patents

Abstract

PURPOSE:To enable accurate measurement of a MOS transistor by inserting a p-channel transistor between a drain and a constant current source. CONSTITUTION:A p-channel MOS transistor Qp is inserted between a load resistance R and a drain D and combined with an n-channel MOS transistor Qn to compose a CMOS transistor Qc and both gates are connected in common. When a test signal SN is switched over to an H level from an L level, a drain current I1 so far flowing is interrupted with a switching circuit 2 and a drain output voltage VD drops so steeply that a falling delay time is reduced to the extent of a switching time of an ordinary CMOS transistor thereby facilitating the judgement of the results of testing.

Description

[Detailed description of the invention] [Industrial application field] The invention relates to a test circuit for MOS transistors.

In particular, it relates to a test circuit for n-channel open-drain transistors.

[Conventional technology]

In general, an operation test for an n-channel open-drain transistor is performed by connecting a constant current source to the drain and another power source via a resistor, and inputting a ``H'' or @L1'' level test signal to the gate. This is done by measuring the drain voltage waveform.

FIGS. 3(a) and 3(b) are circuit diagrams of an example of a conventional MOS transistor test circuit.

The MOS transistor test circuit includes a resistor R3 in series with the drain D of the n-channel MO8 transistor Qn to be tested.
Voltage power source Voot”!Continued 9 Operating circuit under test 1
A drain power supply voltage '%ll is supplied to the drain D of the circuit via a load resistor kLL.

Next, the test procedure will be explained.

As shown in FIG. 3 (al), a test signal SN1 which switches from @H" level to "L" level is applied to the gate terminal T.n.

If the ``L'' level is lower than the threshold voltage of the transistor Qn, the drain output voltage VD of the drain DVC'''1 ('' level is not outputted).

Next, as shown in Figure 3 (bl), from "L" level to "
If the test signal SN2 that switches to the ``L'' level exceeds the threshold voltage, the output voltage VD of the drain D becomes the ``L'' level.

[Problem to be solved by the invention]

FIG. 4 shows the ninth drain voltage waveform factor, which explains the problem in FIG. 3.

The test signal SN2 has a 1L” level at the time of 41,0.
Even when the drain output voltage VD is switched to the "9th power supply voltage V.0" level, a delay time τd of about 3 μs occurs until it reaches 1.5V.

The time also varies depending on the load resistance RL.

The above-mentioned conventional MOS transistor test circuit has a drawback in that the delay time of the downward waveform of the drain output circuit is large, so that the test equipment is likely to misjudge the test result. [Means for Solving the Problem] The present invention M (JS transistor test circuit is tested, s
A constant current source is connected to the drain of an n-channel open-drain type transistor, and a resistor is connected to the voltage source, and all test signals are supplied to the gate to detect the entire voltage at the drain of the MOS transistor. In the test circuit, a p-channel transistor is inserted between the drain and the constant current source to completely configure the n-channel open-drain transistor and CMOS transistor under test,
supplying the test signal to the gate of the p-channel transistor.

〔Example〕

Next, referring to the drawings regarding the embodiments of the present invention, 1. I will explain.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

MOS transistor test 1: The rugged circuit consists of a p-channel MO8 transistor Q, between the load resistor RL and the drain D.
? N-channel MO8 transistor Q under test.

Look at CMOS transistors. f: MO in Figure 3 except that both gates are connected in common and the t point is different.
This is the same as the S transistor test circuit.

When the test signal SN switches from the "L" level to the "H" level, the drain current 1 that has been flowing until now is cut off by the switch circuit 2, so the drain output voltage VD drops sharply and the fall is delayed. Time τd is general 0MO8
g) The switching time of the y resistor is significantly reduced.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

The test circuit is a p-channel MO8 transistor Q.

gate end TGP of the n-channel MO8 transistor under test Qn gate end I11. ．． 1 in Fig. 1 except that the mode setting circuit 3 of the OR circuit OR is inserted between the
This is the same as the embodiment.

The iX1 table is a signal state table of each part for explaining the entire operation of the circuit shown in FIG.

When the mode signal S is at the ``L'' level, the mode is set to be tested using the test signal SN as in the first embodiment.

Table 1 When the mode signal SM is at the "H'" level, the transistor Q is turned off, so the transistor Q is turned off. is in operating mode as an oven-drain transistor.

Therefore, in this embodiment, if the switch circuit 2 and the mode setting circuit 3 are formed on the same chip together with the circuit under test 1 in advance, the test mode and the operation mode as an n-channel open drain transistor can be switched by the mode setting signal SM of the mode TM. This has the effect of simplifying the external circuit during testing.

〔Effect of the invention〕

Having explained the above, the present invention is based on the n-channel MOS under test.
? CMUS with p-channel MO8 transistor in the transistor
By connecting them to form a transistor, a test circuit for MUS transistors that provides accurate foot measurement results can be obtained.

[Brief explanation of the drawing]

Figure M1 is a circuit diagram of the first embodiment of the present invention, Figure 2 is a circuit diagram of the second embodiment of the present invention, and Figures g3 (a) and (b) are examples of conventional MOS transistor test circuits. circuit diagram,
FIG. 4 is a ninth drain voltage waveform diagram illustrating the problem in FIG. 3. l... Operating circuit under test, 2... Switch circuit, 3... Mode setting circuit s Qc...
...CMOS transistor s Qn...n-channel MOS transistor under test, Qp...p
Channel MO8)? 2 jista, R, 几＄...
Resistance, SN...Test signal %Tlf,...
・P channel gate, ■j+, -...Drain output voltage, ■Okit...Drain power supply voltage s voo
······Power-supply voltage. Agent Patent Attorney Uchihara Otoday 72

Claims (1)

[Claims] In a MOS transistor test circuit, a constant current source is connected to the drain of an n-channel open-drain transistor under test, and a voltage power source is connected via a resistor, and a test signal is supplied to the gate to detect the voltage at the drain. A p-channel transistor is inserted between the drain and the constant current source to configure the n-channel open-drain transistor under test and a CMOS transistor, and the test signal is supplied to the gate of the p-channel transistor. Test circuit for MOS transistors.