JPH02280069A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To perform a test for high impedance state accurately and surely in the operation check of a function test by providing a mode making an output terminal in the high impedance state to a medium level. CONSTITUTION:When a high impedance control signal HZC is on a low level and a medium output control signal MOC is on a high level, the output of an inverter I2, i.e. one side of the input end of an AND gate G3 is on the high level and also another side is made to the high level; therefore, an output of the AND gate G3, i.e. a medium output control signal MGC is made to the high level, and a transistor Q3 is made to a connected state to make the output terminal T0 to the middle level between the low and high levels of an output signal OUT of the voltage subtracting the voltage between a source and drain of the transistor Q3 from a high level voltage of the medium output generating control signal MGC. With this arrangement, the test for the high impedance state can be made accurately and surely in the operation check of the function test and also performed in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit, and in particular, the present invention relates to an output buffer circuit in which an output signal can take two states, low level and high level, and an output impedance can take a high impedance state. This invention relates to a three-state output buffer circuit that can be used.

[Conventional technology]

Conventionally, this type of output buffer circuit, as shown in FIG. 2, includes an N-channel MO3 type first transistor Q1 connected between a ground terminal, which is a first power supply terminal, and an output terminal To; An inverter circuit 1 including a P-channel MO3 type second transistor Q2 connected between a second power supply terminal (power supply voltage Vcc) and an output terminal To, an inverter 1, a NAND gate G, and a NOR Gate G2
, inputs the input signal IN and the high impedance control signal H2C, and connects the first and second output terminals to the first and second output terminals.
The transistor Q1. When the high-impedance control signal H2C is at a low level, the transistors Ql and Q2 are turned off to set the output impedance of the inverter circuit 1 to a high-impedance state, and when the high-impedance control signal H2C is at a high level, The configuration includes an output control circuit 2 that sets the output signal OUT of the inverter circuit 1 to a low level or a high level depending on the level of the input signal IN.

[Problem to be solved by the invention]

The conventional output buffer circuit described above has an inverter circuit 1.
and an output control circuit 2 that controls the output state of the inverter circuit 1 into three states: low level, high level, and high impedance, so the high impedance state of this output buffer circuit is tested. for,
Either stop the function pattern of the test device with a high impedance pattern and measure it directly, or connect it to the output terminal T. The former measurement method requires too much test time to measure all high-impedance states in the function pattern, and also This method has the disadvantage that it does not serve as an operation check during a frequency function test, and the latter measurement method also has the disadvantage that high impedance and high level cannot be distinguished.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output buffer circuit that can accurately, reliably, and quickly test a high impedance state during an operation check of a functional test.

[Means to solve the problem]

The output buffer circuit of the present invention includes a first transistor connected between a first power supply terminal and an output terminal, a second transistor connected between a second power supply terminal and the output terminal, and a second transistor connected between a second power supply terminal and the output terminal. an inverter circuit having an input signal and a high-impedance control signal, having first and second output terminals connected to the gates of the first and second transistors, respectively, and having an input signal and a high-impedance control signal; is at a first level, the first and second transistors are turned off, and the high impedance control signal is at a second level.
an output control circuit that sets the output signal of the inverter circuit to first and second levels according to the level of the input signal when the high impedance control signal is at the first level;
an intermediate output control circuit that outputs an intermediate output generation control signal when the intermediate output control signal is at a predetermined level; and an intermediate output control circuit that outputs an intermediate output generation control signal when the intermediate output control signal is at a prescribed level; 1st and 2nd
and an intermediate level generation circuit that generates a level intermediate between the levels of .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

This embodiment differs from the conventional output buffer circuit shown in FIG. 2 in that the inverter I2 and AND gate G,
an intermediate output control circuit 3 which outputs a high level intermediate output generation control signal MGC when the high impedance control signal H2C is at a low level and the intermediate output control signal MOC is at a high level; and a predetermined threshold value. It is equipped with an N-channel MO3 type transistor Q3 having a high voltage, and when a high level intermediate output generation control signal MGC is input, the level of the output signal OUT of the inverter circuit 1 is changed to the level of the output signal OUT of the inverter circuit 1.
The present invention is characterized in that an intermediate level generating circuit 4 is provided which generates an intermediate level between the low level and high level of T.

Next, the operation of this embodiment will be explained.

When the high impedance control signal H2C is at a high level, the output of the inverter E2, that is, one of the input terminals of the AND gate G, is at a low level. The output, that is, the intermediate output generation control signal MGC becomes low level, the transistor Q3 is turned off, and the intermediate level generation circuit 4 is disconnected from the inverter circuit 1. Therefore, as in the conventional example, the output signal OUT of the inverter circuit 1 has a level corresponding to the level of the input signal IN.

The high impedance control signal H2C is at a low level,
And when the intermediate output control signal MOC is at low level, AN
Since the other input terminal of D gate G3 is at a low level, the intermediate level generation circuit 4 is separated from the inverter circuit 1 in the same way as when the high impedance control signal H2C is at a high level, and the inverter circuit 1 is operated as in the conventional example. becomes a high impedance state.

High impedance control signal H2C is at low level,
When the intermediate output control signal MO8 is at a high level, the output of the inverter 2, that is, one of the input terminals of the AND gate G3 is at a high level, and the other is also at a high level, so the AND
The output of gate G3, that is, intermediate output generation control signal MGC, becomes high level, transistor Q3 becomes conductive, and output terminal To changes from the high level voltage of intermediate output generation control signal MGC to the source-drain voltage of transistor Q3. is set to a voltage that is between the low level and high level of the output signal OUT. At this time, the transistor Ql
, Q2 are turned off by the high impedance control signal H2C.

By providing a mode in which the output terminal To is at an intermediate level in the high impedance state in this way, the test in the high impedance state can be performed accurately and reliably during the operation check of the function test.

〔Effect of the invention〕

As explained above, the present invention provides a mode in which the level of the output terminal in the high impedance state is set to an intermediate level between the low level and the high level of the output signal, so that the test in the high impedance state can be performed using a function function. This has the advantage that it can be performed accurately, reliably, and in a short time during the operation check of the test.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional output buffer circuit. 1... Inverter circuit, 2... Output control circuit, 3.
... intermediate output control circuit, 4... intermediate level generation circuit,
G1...NAND gate, G2...NOR gate,
G,...AND gate, 1. , I2...inverter, Q1-Q3...transistor. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] an inverter circuit including a first transistor connected between a first power supply terminal and an output terminal; a second transistor connected between a second power supply terminal and the output terminal; signal and a high impedance control signal, first and second output terminals are respectively connected to the gates of the first and second transistors, and when the high impedance control signal is at a first level, the 1st
and a second transistor is turned off, and when the high impedance control signal is at the second level, the output signal of the inverter circuit is set to the first level according to the level of the input signal.
and a second level output control circuit, and an intermediate output control circuit that outputs an intermediate output generation control signal when the high impedance control signal is at a first level and the intermediate output control signal is at a predetermined level. An output buffer circuit comprising: an intermediate level generation circuit that sets the level of the output signal of the inverter circuit to a level intermediate between the first and second levels of the output signal according to the intermediate output generation control signal.