JPH0132143Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a circuit that can reliably and quickly obtain various information set by a dip switch.

When setting various information using a dip switch and transmitting the information to a control device such as a microprocessor, a parity bit is added to increase the reliability of the dip switch. FIG. 1 is an external view of the deep switch, in which a is a plan view and b is a front view. When transmitting information with a parity bit added using such a dip switch, the following procedure is performed. That is, various information is set with 7 bits from 1 to 7, and the 8th switch is used as a parity bit. For example, if you use odd parity, the setting information is 0101101
If the parity is odd, set the eighth switch to "1". Which of ON and OFF is set to "1" can be arbitrarily determined.

FIG. 2 is a diagram showing an example of an information transmission circuit using a dip switch. In the figure, 1 is a deep switch, 2 is a buffer that receives setting information of the deep switch, and 3 is a control device that receives the output of the buffer. As the control device, for example, a microcomputer is used as described above. An information transmission circuit like this, consisting of a deep switch and a buffer, is a data bus.
It is common for multiple devices to be connected to a DB. Therefore, in order to prevent a plurality of pieces of information from colliding on the data bus DB, a prohibition signal is input to the buffer 2 as shown in the figure. The inhibition signal is given from a separate control circuit (not shown).
When transmitting the information set by the dip switch 1 from the circuit shown in the figure to the control device 3, the prohibition signal is released and the information set by the dip switch 1 is transmitted to the control device 3 via the buffer 2. Conversely, when information is not transmitted, a prohibition signal is input to buffer 2, and the output of the buffer becomes a high impedance state and connects to the data bus DB.
bus DB, and other information transmission circuits exclusively use the bus DB.

If a parity check method is adopted in an information transmission circuit having such a configuration, it is necessary to perform a parity check every time the information transmission circuit is called, which requires a lot of processing time.

The present invention was developed in view of these points, and includes a memory that stores the correct data confirmed in the first parity check, and from then on, the data stored in the memory and the imported data are stored in the memory. This realizes an information check circuit that has a fast processing time and can check information simply by checking whether the data match. Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 3 is an electrical configuration diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 2 are designated with the same numbers. Reference numeral 4 denotes a memory in which correct data confirmed by a parity check is stored for each information transmission circuit. The memory is, for example, RAM.
is used. The operation of the device configured as described above will be explained as follows.

Various information is set from the deep switch 1. Possible types of information include the model number of the I/O device, upper and lower limit settings for input data, and the like. Taking the dip switch shown in FIG. 1 as an example, parity data is set at the 8th bit. If, for example, 0101101 is set using all 7 bits as setting information, the parity data will be "1" for odd parity. Therefore, the 8-beat data 01011011 is
It is transmitted to the control device 3 via. Note that at this time, the inhibit signal of buffer 2 has been released. The control device 3 counts the number of "1"s in the captured data. If the result of addition is an odd number, it means that the information is being conveyed correctly. On the other hand, if the result of the addition is an even number, the information has been transmitted in error.
If the information is erroneously transmitted, the control device 3 executes abnormality processing such as outputting an error message.

On the other hand, if the information is transmitted correctly,
The control device 3 stores the received data in the memory 4. The memory address for storing this data is determined for each transmission circuit, and the data is stored at the determined address. In this way, once correct information is stored in the memory 4, the next time when receiving information from the relevant transmission circuit, the received data and the memory 4 will be stored.
You can check whether the information was transmitted correctly by simply comparing it with the data stored in the . That is, since there is no need to perform a parity check each time, the processing time is significantly shortened. In the above description, the case where the number of bits of the dip switch is 8 bits has been explained as an example, but it goes without saying that the number of bits is not limited to 8 bits. It can be any number of bits.

As explained in detail above, according to the present invention, a memory is provided to store the correct data confirmed in the first parity check, and from then on, whether the data stored in the memory and the imported data match. It is possible to realize an information check circuit for a dip switch in which the processing time is improved by checking the information only by checking whether the information is correct or not.

[Brief explanation of the drawing]

FIG. 1 is an external view of a deep switch, FIG. 2 is a diagram showing an example of an information transmission circuit, and FIG. 3 is an electrical configuration diagram showing an embodiment of the present invention. 1...Deep switch, 2...Battle switch, 3
...Control device, 4...Memory.

Claims (1)

[Scope of utility model registration request] When setting various information on the dip switch and transmitting it to the control device, the setting information is transmitted to the control device via a buffer, and a memory is provided to store the results of the first parity check. Features a deep switch information check circuit.