JPH0132952B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a logic analyzer,
In particular, the present invention relates to a logic analyzer having a logic operation function.

Recently, with the advancement of microprocessor technology and computer technology, various electronic devices are
Logic signal processing technology has become popular. There are oscilloscopes, logic probes, logic analyzers, etc. as measuring instruments for the development, adjustment, and fault repair of electronic devices using logic technology. Ideal as a measuring instrument.
That is, a logic analyzer stores input logic signals (data) of multiple channels in a storage means such as a random access memory (RAM), and then transfers the data stored in this storage means to a cathode ray tube (CRT) or the like. This is because since it is displayed on the display means, data before the trigger signal is generated can be measured. By the way, logic analyzers have two types of display modes. One is a timing display mode that displays logic signals as signal waveforms, and the other is a timing display mode that displays stored data in binary, octal,
This is a state display mode that displays characters (including numbers) as words in hexadecimal format.

In this way, logic analyzers are ideal as instruments for measuring logic signals, but conventional logic analyzers simply observe the signals at each measurement point of the circuit under test (or device under test). However, it did not have a function to determine whether the measurement result is correct (that is, whether the circuit under test is operating normally). In other words, conventional logic analyzers measure input and output signals of logic circuits, but
There was a problem that it was not possible to judge whether the measured input-output relationship was correct or not.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a logic analyzer that has a logic operation function and can predict the output of a circuit under test.

Another object of the present invention is to provide a logic analyzer which has a logic operation function, can compare the result of the logic operation with the actual output from the circuit under test, and can display the comparison result.

Still another object of the present invention is to provide a logic analyzer which has a logic operation function and performs calculations taking into account the skew (phase shift between input and output) of the circuit under test.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. First, a first embodiment of the present invention will be described with reference to FIGS. 1 to 6.

FIG. 1 is a block diagram of a first embodiment of a logic analyzer according to the present invention. The logic analyzer shown in Figure 1 includes four probes 10.
A to 10D are connected. Each probe has eight chips and can each receive eight channels of input logic signals. probe 10
Logic signals from A-10D are provided to comparator 12. The comparator 12 converts the level of the input logic signal to a logic level (for example, TTL (transistor-transistor level)) suitable for each block in FIG. and trigger circuit 16
(including word recognizers and counters). Data storage circuit 14, trigger circuit 1
6 is connected to bus 20 (including data, address and control buses). The start/stop control circuit 22 receives a command signal from the bus 20.
The storage operation of the data storage circuit 14, that is, the input data acquisition is started, and further, the storage operation of the data storage circuit 14 is stopped in response to the output from the trigger circuit 16. The central processing unit (CPU) 24 is, for example, a commercially available Z80A type microprocessor,
It operates as a logic operation means and a circuit operation processing means. Read-only memory (ROM) 26
is a memory circuit for firmware that stores the processing procedure of the CPU 24, and the RAM 28 is a storage circuit for the firmware that stores the processing procedure of the CPU 24.
4. Operates as a temporary memory circuit and displays
This is a storage circuit that also includes a RAM area. ROM 26 and RAM 28 are also connected to bus 20. The keyboard 30 has a plurality of keys, is an input means used for controlling a cursor, inputting control signals, data, etc., and is also connected to the bus 20. A display control circuit 32 connected to the bus 20 outputs a horizontal synchronization signal, a vertical synchronization signal, and a display of the RAM 28.
A brightness signal is output based on the data in the RAM area, and the data is displayed on a raster scanning type CRT 34, which is a display means. The clock pulse generator 36 is
A clock pulse of a frequency corresponding to the command signal from the bus 20 is sent to the data storage circuit 14 and the trigger circuit 1.
Supply to 6th grade. In addition, CPU24, ROM26,
The clock frequencies of the RAM 28 and the keyboard 30 are fixed at, for example, 4MHz (when the CPU 24 is Z80A).

Next, a first embodiment of the present invention will be described in more detail with reference to the attached FIGS. 2 to 5. In this embodiment, the logic circuit shown in FIG. 2 is assumed as the circuit to be measured. In FIG. 2, 1 to 6 are input terminals of the circuit, and 7 is an output terminal. Input terminals 1 and 2 are connected to the input terminal of the AND circuit 40,
The output terminal of AND circuit 40 is connected to the clock terminal of D flip-flop 42. D flip
The data input terminal of flop 42 is connected to input terminal 6, and the Q output terminal of D flip-flop 42 is connected to one input terminal of OR circuit 44. The other input terminal of the OR circuit 44 is connected to the Q output terminal of the D flip-flop 46, and the data input terminal and clock terminal of the D flip-flop 46 are connected to the input terminal 5 and the output terminal of the AND circuit 48, respectively. , two input terminals of the AND circuit 48 are connected to input terminals 3 and 4, respectively.

Next, the measurement and calculation of logic signals according to the present invention will be explained. First, the operator selects one suitable probe from among the probes 10A to 10D, and connects seven of the eight chips of the probe to input terminals 1 to 6 and output terminal 7 of the circuit shown in FIG. , 7 chips and terminals 1 to 6 in Figure 2.
It is assumed that the connection relationship has already been input from the keyboard 30. In order to simplify the explanation, terminals 1 to 7 in FIG.
It is assumed that the circuit is connected to chips 1 to 7. next,
The steps for measuring and calculating logic signals will be numbered and explained in order.

(1) When the operator instructs to capture input data from the keyboard 30, the start/stop control circuit 22 sends a capture start command signal to the data storage circuit 1 based on a command signal from the CPU 24.
Output to 4.

(2) In response to this acquisition start signal, the data storage circuit 14 acquires the input data from the designated probe chip in a chronological order via the comparator 12, and sequentially stores it in a predetermined storage area. .

(3) The trigger circuit 16 generates a trigger from the input data.
Upon detecting a word and subsequently counting a predetermined number of clock signals, trigger circuit 16 outputs a signal to start/stop control circuit 22.

(4) The start/stop control circuit 22 applies a capture stop signal to the data storage circuit 14 in response to the output signal from the trigger circuit 16 to stop the data storage circuit 14 from capturing input data.

(5) From the keyboard 30 to the data storage circuit 14
Instructs to display the imported data.

(6) The CPU 24 transfers the data stored in the data storage circuit 14 to the CPU/RAM 28.
The display contents are transferred to and stored in the first area (first storage means) of the RAM, and then the display contents are stored as font information (for example, a code signal) in the display area of the RAM 28, and the contents of the display RAM are displayed on the CRT 34. .

(7) Enter the logical operation formula of the logic circuit shown in Fig. 2 from the keyboard 30, and input it to the CPU/RAM 28.
Store in the arithmetic expression area of RAM.

(8) The CPU 24 parses the arithmetic expression stored in the CPU/RAM of the RAM 28, retrieves data from the first area of the CPU/RAM of the RAM 28 according to the analysis result, and extracts data from the first area of the CPU/RAM of the RAM 28, The calculation is performed by a calculation subroutine (described later with reference to FIGS. 10 to 14), and the result is stored in a second area (second storage means) of the CPU/RAM of the RAM 28. Note that the intermediate results are stored in a temporary storage circuit of the CPU 24.

(9) Input logical operation expression and second part of RAM28
RAM28 uses area data as font information
The contents of this display RAM are displayed on the CRT 34.

The logical operation formula for the circuit under test shown in FIG. 2 is expressed as ((1Λ2)↑6)V((3Λ4)↓5). Here, the numbers 1 to 6 indicate the signals input to the input terminals 1 to 6 of the circuit under test in Fig. 2, Λ indicates the AND, V indicates the OR, and ↑ indicates that the D flip-flop is connected to the clock pulse. This indicates that the signal input to the data end is latched (captured and held) at the rising edge, and ↓ indicates that the D flip-flop latches the signal input to the data edge at the falling edge of the clock pulse. That is, the above logical operation formula is based on the logic of the signal applied to input terminals 3 and 4, which is obtained by latching the signal at input terminal 6 at the rising edge of the AND output of the logic signals applied to input terminals 1 and 2. It represents the logical sum with the signal of input terminal 5 latched at the falling edge of the product output.

FIG. 3 is a diagram showing the display screen in the timing display mode, and FIG. 2 shows the timing waveform of the input signal of the logic circuit (circuit under test), the logical operation formula of the circuit in FIG. 2 shows a timing waveform of a signal obtained by calculating the input signal of FIG. 2 based on the signal (that is, an expected output signal of the circuit under test of FIG. 2). To explain the display in Figure 3 in more detail, the PAGE=CAL box enclosed in the square at the top row
indicates that the current display is a calibration display (or a simulated display), and A6 to A1 surrounded by a square on the left end are probes 10A selected via the keyboard 30.
(i.e. probe 10A by Alphabet)
-10D (indicating which one is selected) (that is, the selected channel number), and the numbers 1 to 6 at the left end indicate the channel numbers on the display screen. Therefore, the timing waveforms of the 6th channel from the top of the screen are as follows:
2 shows the timing waveforms of the signals inputted to the input terminals 6-1 of FIG. 2 and taken in from the chips 6-1 of the probe 10A, respectively. In addition, input terminal 6~
1 and probe 10A (i.e.,
The connection relationship) is specified by the operator by inputting it from the keyboard 30. The right side of the upper ** mark represents the above-mentioned logical operation formula, and the timing waveform on the right side of the lower ** mark is the timing waveform of the signal calculated based on the upper stage calculation formula.

In this way, by inputting the arithmetic expression for the circuit under test from the keyboard 30 and further inputting the input signal to the circuit under test into the logic analyzer according to the present invention, the timing waveform of the output signal of the circuit under test can be predicted. can. Furthermore, as will be described later, when the operation of the circuit under test is not normal, the output of the logic analyzer according to the present invention can be used as an input signal to the circuit under test at the next stage. -The analyzer can also be used as a pattern generator.

4 is a diagram in which, in addition to the display shown in FIG. 3, the output of the circuit under test in FIG. 2 is actually input to a logic analyzer and its timing waveform is simultaneously displayed. The difference between Figure 4 and Figure 3 is that
In the figure, the timing waveform of the output signal of the circuit under test of FIG. 2 is shown in the seventh channel at the lower left end of the display screen and on the right side of the square A7. Note that this A7 indicates the seventh chip of the probe 10A, and the signal input to this chip is
It is displayed as the seventh channel according to the operator's instructions. That is, in the case of FIG. 4, the output of the input terminal 7 of FIG. 2 is taken in from the seventh chip of the probe 10A, and its timing waveform is displayed as a seventh channel signal. In the display screen of FIG. 4, the output signal waveform of the circuit under test is the same as the calculation result based on the calculation formula in the upper row, indicating that the circuit under test is operating normally. In this manner, the operator can easily compare the timing waveform of the output signal of the circuit under test with the timing waveform based on the calculation result, and therefore can very easily determine whether the operation of the circuit under test is normal or abnormal.

Figure 5 is a diagram showing the state table (when the state display mode is selected) displayed on the CRT34 (Figure 1), and shows part of the display shown in Figures 3 and 4. ing. In FIG. 5, the ** marks on the top row are the calculation formulas explained in FIGS. 3 and 4, and the numbers 1 to 7 on the second row are the signal channel numbers (in the case of this example, the channel numbers and probe chips). Similarly, the ** marks in the second column indicate the calculation results, and the numbers 0 to 13 at the left end of the screen indicate the address numbers of the first or second area of the RAM 28. That is, the table in Figure 5 is
RAM2 via chips 1 to 7 of probe 10A
In addition to indicating the logic level of the input signal stored in addresses 0 to 13 of the first or second area of 8, the prediction result of the output ( (** column on the far right) allows for quantitative comparison of actual results and predicted results. In Figure 5, if the output signal of the circuit under test differs from the predicted result in the ** column on the right, the display of that part should be controlled (for example, by brightness modulation, black and white inversion, surrounding it with squares, etc.). Ba,
This has the effect of attracting the operator's attention. For this purpose, in the firmware in ROM26,
For example, it may be provided with a comparison function that performs an exclusive OR operation between the output signal of the circuit under test and the prediction result based on the arithmetic expression. In the state display mode shown in Fig. 5, for example, the pulse width of the input signal is very narrow, and in the timing mode shown in Figs. 3 and 4, the actual measured waveform is compared with the predicted waveform based on the calculation result. This is effective when it is not easy to do so.

By the way, in the circuit under test shown in FIG.
The signals applied to the clock ends of flip-flops 42 and 46 are delayed in phase with respect to the logic signals at input terminals 6 and 5 (i.e., AND circuit 4
There is a phase shift (so-called skew) between the input and output of 0 and 48). Due to this phase, even if the circuit under test is operating normally, the actual output signal may differ from the calculation result, so it is necessary to compensate for this phase shift before performing the calculation.

For this reason, the present invention takes measures against skew using software. This skew countermeasure using software will be explained.

FIG. 6 shows the RAM 28 in order to explain skew countermeasures using software according to the present invention.
FIG. 2 is a diagram schematically showing a storage area division of the CPU/RAM and a part of the first area of the CPU/RAM.
In Figure 6, 0000 to 0100, 0 on the left side
101 to FFFF indicate the address of RAM28,
The CPU/RAM includes a first area (first storage means),
There are a second area (second storage means), an arithmetic expression area, a flag area, a skew area, etc. In order to perform the skew using software, it is necessary to partially change steps (1) to (9) for measuring and calculating logic signals according to the present invention as described above. That is, after step (7), ``(7') Express the phase deviation (skew information) of each channel from the keyboard 30 by the number of clocks (the skew of each element can be obtained from a catalog or actual measurement,
(represented by the product of the clock cycle and the number of clocks), and its value is stored in the CPU/RAM skew area of the RAM 28. ” step (8) and (9).
are changed to the following (8) and (9), respectively.

``(8) The CPU24 is the CPU and CPU of the RAM28.
The arithmetic expression stored in the RAM is parsed, the number of bits is shifted as necessary based on the analysis result and skew information, the data is read from the first area, the calculation is performed using a subroutine stored in the ROM 26, and the result is RAM28 CPU・
Store in the second area of RAM. ” (9) The arithmetic expression, the skew information, and the data in the second area are fonted and stored in the display RAM area. Note that the period of the clock signal that captures the input signal must be shorter than the phase shift (skew time) to be considered.

In FIG. 6, to simplify the explanation, among the addresses in the first area, addresses 0100 and 0101 are shown.
is exemplified. Addresses 0100 and 0101
A7-A0 are storage portions that store logic signals taken in from chips 7-0 of the selected probe 10A at different (but consecutive) times of the same clock signal. In the case of the circuit under test shown in FIG. 2, in order to simplify the explanation, it is assumed that the phase shift (phase delay) between the input and output of the AND circuits 40 and 48 is one clock cycle, and the calculation is performed using the address 0100 described above. A case will be described in which this is performed based on the data of 0101 and 0101. The operator is
Skew information (information corresponding to one clock cycle) is sent from the keyboard 30 to the CPU of the RAM 28 in advance.
Store in RAM skew area. CPU24
parses the already stored arithmetic expression, and based on the result, performs a logical product operation of the data of A6 and A5 of 0101. The result is transferred to CPU/RAM
, and latches the data of A1 at address 0100 based on the stored contents.
The results are stored in the temporary storage circuit of the CPU/RAM. Similarly, A4 and A at address 0101
Perform a logical product operation on the data in 3 and use the result as
It is stored in the temporary storage circuit of the CPU/RAM, and based on the stored contents, the data at address 0100 A2 is latched, and the result is stored in the temporary storage circuit. Note that for data that does not require consideration of phase shift, it is sufficient to read data within the same address and perform calculations. In this way, when there is a phase shift between the input and output of the circuit under test, by inputting skew information from the keyboard 30, the software can compensate for the phase shift and perform correct logical operations.

This is a block diagram when the above-mentioned skew countermeasure is implemented using hardware, and the block shown in FIG. A buffer means 62 used for outputting the data to the outside is added. Regarding blocks other than the variable delay means 60 and the buffer means 62, the first
Since it has already been explained with reference to the figures, the same reference numerals will be given and the explanation will be omitted.

FIG. 8 is a diagram showing a specific example of the variable delay means 60 shown in FIG. 7. The variable delay means shown in FIG. 7 must be provided for each channel of the input signal (that is, for each chip of the probe).

In FIG. 8, the multiplexer 64 has data input terminals D0 to D5, an output terminal 64A, and a bus 2
It has a control end 64B connected to 0. The data input terminal D5 is connected to the input terminal 66 via the delay line 68, the input terminal D0 is directly connected to the data input terminal 66, and the other data input terminals D1 to D4 are connected to the input terminal 66 via the delay line 68.
is connected to a predetermined tap (intermediate connection point).
Note that the input terminal 66 and the output terminal 70 are respectively connected to the seventh
It is connected to the comparator 12 and data storage circuit 14 shown in the figure. The multiplexer 64 selects the data input terminals D0 to D0 according to the control signal applied to the control terminal 64B.
Select one of D5 and connect it to the output terminal 64A,
Control the signal delay time. In addition, the operator
Inputting skew information (phase shift information) from the keyboard 30 is the same as in the case of countermeasure against skew using software described above. It is also desirable that the multiplexer 64 has the function of latching the control signal.

As mentioned above, the buffer means 62 in FIG.
This is provided to output data in the second area of the CPU/RAM of the RAM 28 to the outside. Therefore, by providing the buffer means 62, the logic analyzer according to the present invention can be used as a pattern generator. Incidentally, if the buffer means 62 is simply a buffer amplifier, the CPU/
Data stored in RAM can only be output using the CPU clock (4MHz, as mentioned above), but if the buffer means 62 is equipped with a high-speed storage circuit and a buffer amplifier, data can be transferred from the CPU/RAM using the CPU clock. , a desired clock frequency (entered by the operator from the keyboard 30). However, if the buffer means 62 is provided with a high-speed memory circuit and a buffer amplifier, the applications can be expanded, but there is a drawback that the manufacturing cost increases. It should be noted that the buffer means 62 may be configured to transfer not only the calculation results of the second area of the CPU/RAM of the RAM 28 but also the data taken into the second area. As described above, the logic analyzer according to the present invention uses a pattern generator that applies the output of the logic analyzer (i.e., the output of the buffer means 62) to the circuit under test at the next stage when the operation of a certain circuit under test is not normal. Can be used as an energizer. Of course, regardless of whether the operation of the circuit under test is normal or abnormal, the logic analyzer according to the present invention can be used as a standalone pattern generator by storing a desired logical operation formula in the logic analyzer and inputting a predetermined input signal. It can also be used as a rater.

FIG. 9 is a diagram showing a grouping (GROUPING) menu that is effective when implementing the present invention. In Figure 9, G1 to G on the left side of the display screen
4 is the group number, and ON is enclosed in a square.
indicates that the corresponding group number is being used, and OFF, also enclosed in a square, indicates that the corresponding group number is not being used. Furthermore,
F~0 on the top row is the signal number within each group expressed in hexadecimal, A1, B2, C surrounded by a large square
4, D3, etc. indicate the chip number of the probe (ie, the alphabet indicates the probe and the number indicates the chip number). Grouping is instructed by the operator from the keyboard 30, and information regarding the grouped probes and chips is stored in the RAM 28.
Stored in the flag area of the CPU/RAM. Grouping allows you to freely select (overlapping) signals input to different probe chips and group them, which is useful when only signals from a limited number of channels can be calculated due to firmware constraints. It is. Furthermore, grouping is useful for state table displays. Furthermore, since the restriction that a specific probe must be connected to a specific location of the circuit under test is relaxed, measurement becomes easier.

10 to 14 are flowcharts of logic operation subroutines stored in the ROM 26. FIG. 10 shows logical product, FIG. 11 shows logical sum, and FIG. 12 shows one data. A logical operation that latches the other data at the rising edge of
FIG. 13 shows a logic operation in which one data is latched at the falling edge of the other data, and FIG. 14 shows an exclusive OR operation. In FIG. 10, step (74): Data A is stored in the temporary storage circuit X.

Step (76): Store data B in temporary storage circuit Y.

Step (78): Determine whether the data stored in the temporary storage circuits X and Y are both 1. If both are 1, go to step (80), and if both are not 1, go to step (82).

Step (80): Store 1 in the temporary storage circuit Z and end.

Step (82): 0 is stored in the temporary storage circuit Z and the process ends.

In FIG. 11, step (84): Data A is stored in temporary storage circuit X.

Step (86): Store data B in temporary storage circuit Y.

Step (88): Determine whether the data stored in the temporary storage circuits X and Y are both 0. If both are 0, go to step (90), and if both are not 0, go to step (92).

Step (90): 0 is stored in the temporary storage circuit Z and the process ends.

Step (92): Store 1 in the temporary storage circuit Z and end.

In FIG. 12, step (94): Data A is stored in temporary storage circuit X.

Step (96): Store the contents of the next address of data A in temporary storage circuit Y.

Step (98): Determine whether the contents of temporary memory circuit Go to step (102).

Step (100): Store the contents of temporary memory circuit Y in temporary memory circuit X and return to step (96).

Step (102): Data A in temporary memory circuit Y
Temporary storage circuit Z stores data B corresponding to the address of
Save and exit.

In FIG. 13, step (104): Data A is stored in the temporary storage circuit X.

Step (106): Store the contents of the next address of data A in temporary storage circuit Y.

Step (108): Determine whether the content of temporary memory circuit Go to step (112).

Step (110): Store the contents of temporary memory circuit Y in temporary memory circuit X and proceed to step (106).

Step (112): Data A in temporary memory circuit Y
Temporary storage circuit Z stores data B corresponding to the address of
Save and exit.

In FIG. 14, step (114): Data A is stored in the temporary storage circuit X.

Step (116): Store data B in temporary storage circuit Y.

Step (118): Determine whether the contents of temporary memory circuits X and Y are different. If they are different, go to step (120); if they are the same, go to step (122).

Step (120): Store 1 in the temporary storage circuit Z and end.

Step (122): 0 is stored in the temporary storage circuit Z and the process ends.

The flowchart of logical operations has been illustrated above, but in addition to these, there are also NAND, NOR, R-S flip-flop, T-flip-flop, JK-
Flowcharts for logic operations such as flip-flop, reset, and phase inversion can be considered in the same way. As explained above, since the logic analyzer according to the present invention has a logical operation function,
It has the feature that the output of the circuit under test can be predicted by applying a signal input to the circuit under test, and furthermore, the result of logical operation can be compared with the actual output from the circuit under test and the comparison result can be displayed. Furthermore,
The logic analyzer according to the present invention is characterized in that, when there is a phase shift between the input and output of the circuit under test, calculations can be performed in consideration of the phase shift.

Although the preferred embodiments of the present invention have been described above, those skilled in the art can easily make modifications and changes to the embodiments described in this specification. For example, as the buffer means 62 shown in FIG. 7, the phase delay circuit disclosed in FIG. 4 of Japanese Patent Application No. 55-17805 (Japanese Unexamined Patent Publication No. 56-115026) filed by the present applicant may be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a logic analyzer (first embodiment) according to the present invention, FIG. 2 is a specific circuit diagram of a circuit under test for explaining the present invention, and FIG.
5 to 5 are display screen diagrams of a display device for explaining the present invention, FIG. 6 is a diagram schematically showing storage area divisions of a memory circuit, etc. for explaining the present invention, and FIG. is a block diagram when the skew countermeasure of the logic analyzer according to the present invention is realized in hardware, FIG. 8 is a concrete diagram of one block in FIG. 7, and FIG. 9 is a display for explaining the present invention. The display diagrams of the apparatus and FIGS. 10 to 14 are flowcharts of the calculation formulas used in the present invention. 24: CPU (calculation means), 28: RAM (storage means), 30: input means, 34: CRT (display means).

Claims (1)

[Scope of Claims] 1. A first storage means for sequentially storing input logic signals of a plurality of channels taken in a time series, an input means for inputting logical operation information and skew information, and the above logic signals taken in at different times. a calculation means for selectively reading out the logic signal from the first storage means according to the skew information and performing a logical operation on the read logic signal according to the logical operation information; and a second memory for storing the calculation result of the calculation means. and display means for selectively displaying the stored contents of the first and second storage means.