JPH0134432Y2 - - Google Patents
Info
- Publication number
- JPH0134432Y2 JPH0134432Y2 JP19399482U JP19399482U JPH0134432Y2 JP H0134432 Y2 JPH0134432 Y2 JP H0134432Y2 JP 19399482 U JP19399482 U JP 19399482U JP 19399482 U JP19399482 U JP 19399482U JP H0134432 Y2 JPH0134432 Y2 JP H0134432Y2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- electrodes
- winding
- forming
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Coils Or Transformers For Communication (AREA)
Description
【考案の詳細な説明】
本考案はデイレイラインに関し、特に積層タイ
プのデイレイラインに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay line, and particularly to a laminated type delay line.
インダクタとコンデンサとより成るデイレイラ
インは例えば第1図に示すようにL1,L2,L3,
L4を直列に接続し、C1,C2,C3,C4,C5を並列
に接続し、端子Fを接地として端子A,E間に遅
延特性を持たせたものである。 For example, as shown in Fig. 1, a delay line consisting of an inductor and a capacitor has lines L 1 , L 2 , L 3 ,
L 4 is connected in series, C 1 , C 2 , C 3 , C 4 , and C 5 are connected in parallel, terminal F is grounded, and a delay characteristic is provided between terminals A and E.
本考案はこのような種類のデイレイラインを極
く簡単な構造の積層体により構成するものであ
り、製造工程を単純化し、デイレイラインを小型
化することができる。本考案のデイレイラインは
コイル形成用導体と磁性体層との交互積層体であ
つて、前記導体は前記磁性体層の層間から次の層
間へと周回する導体コイルを形成しており、前記
導体コイルの巻きはじめケ所、巻き終りケ所及び
巻きはじめから巻き終りに至る中間の少なくとも
1ケ所からそれぞれ別個の引出し導体によつて周
辺のそれぞれ異なるケ所に引出された端子電極を
有する第1の積層体と、複数組の容量形成用電極
と誘電体層との交互積層体であつて、前記各組の
電極は導体により周辺へ引出されている第2の積
層体との一体重畳体であつて、前記複数組の容量
形成用電極の一方の極性の引出端は前記コイル状
導体の複数の端子電極にそれぞれ接続し、前記複
数組の容量形成用電極の他方の極性はまとめて独
立の端子電極に接続されている積層体デイレイラ
インである。 According to the present invention, this type of delay line is constructed from a laminated body having an extremely simple structure, and the manufacturing process can be simplified and the delay line can be made smaller. The delay line of the present invention is an alternately laminated body of coil-forming conductors and magnetic layers, and the conductor forms a conductor coil that goes around from one layer of the magnetic layer to the next. a first laminate having terminal electrodes drawn out from the winding start point of the coil, the winding end point, and at least one intermediate point from the winding start to the winding end to different places around the periphery by separate lead-out conductors; , a plurality of sets of alternating laminates of capacitance-forming electrodes and dielectric layers, each set of electrodes being a single laminate with a second laminate led out to the periphery by a conductor; The drawn ends of one polarity of the plurality of sets of capacitance forming electrodes are respectively connected to the plurality of terminal electrodes of the coiled conductor, and the other polarity of the plurality of sets of capacitance forming electrodes are collectively connected to independent terminal electrodes. This is a laminate delay line.
本考案は、このように2種の積層体において、
導電パターンを選択するだけで、容易かつ能率的
にデイレイラインを構成できる利益を有する。以
下本考案を詳しく説明する。 In this way, the present invention has two types of laminates:
This has the advantage that a delay line can be easily and efficiently constructed simply by selecting a conductive pattern. The present invention will be explained in detail below.
第2図ないし第15図は本考案のデイレイライ
ンの磁性体層部分の製造方法と構造を示す。なお
以下に磁性体層とは磁性フエライト粉末のペース
トの印刷から形成される層、誘電体層とは
BaTiO3などの誘電体粉末のペーストの印刷から
作られる層、導体とはAg,Ag−Pd,Pdなどの
金属粉末のペーストの印刷から作られる層であ
る。そして、これらの層の積層体は焼結されて、
外部に接続用や外部端子用の導体が焼付けられる
もので、同様の金属粉末から作られるものとす
る。 2 to 15 show the manufacturing method and structure of the magnetic layer portion of the delay line of the present invention. In the following, a magnetic layer is a layer formed by printing a paste of magnetic ferrite powder, and a dielectric layer is a layer formed by printing a paste of magnetic ferrite powder.
Layers made from printing of pastes of dielectric powders such as BaTiO3 , conductors are layers made from printing of pastes of metal powders such as Ag, Ag-Pd, Pd. The stack of these layers is then sintered,
Conductors for connections and external terminals are baked onto the outside, and are made from the same metal powder.
第2図のように磁性体層1を形成し、その上に
第3図のように導体2を形成し、その際同時に左
辺に引出端aを形成し、第4図のように磁性体層
3により一部を覆い、第5図のように導体4を導
体2に続けて形成し、その際に引出部bも同時に
形成する。第6図のように積層体の一部を磁性体
層5により覆い、次で第7図のように導体6を印
刷し、その際に同時に引出部cも印刷する。第8
図のように磁性体層7を形成し、さらにその上に
第9図のように導体8を下側の導体6と接続させ
て形成し、その際に引出部dも同時に形成する。
次に、第10図のように磁性体層9を形成し、さ
らに第11図のように導体10を導体8に接続す
るように印刷し、同時にその一端を引出部eとし
て右辺に引出し、最後に第12図のように積層体
の表面を覆う磁性体層11を形成する。こうして
得た積層体を高温焼成して焼結体とし、後述の誘
電体層部分と重畳結合する。あるいは誘電体層部
分との重畳を先に行い、その後に焼成を行つても
良い。 A magnetic layer 1 is formed as shown in FIG. 2, a conductor 2 is formed on it as shown in FIG. 3, a conductor 4 is formed following the conductor 2 as shown in FIG. 5, and at the same time, a lead-out portion b is also formed. A part of the laminate is covered with a magnetic layer 5 as shown in FIG. 6, and then a conductor 6 is printed as shown in FIG. 7, and at the same time, the lead portion c is also printed. 8th
A magnetic layer 7 is formed as shown in the figure, and a conductor 8 is formed thereon to be connected to the lower conductor 6 as shown in FIG. 9, and at the same time, a lead-out portion d is also formed.
Next, a magnetic layer 9 is formed as shown in FIG. 10, and a conductor 10 is printed to be connected to the conductor 8 as shown in FIG. Then, as shown in FIG. 12, a magnetic layer 11 is formed to cover the surface of the laminate. The thus obtained laminate is fired at a high temperature to form a sintered body, which is superimposed and bonded to a dielectric layer portion to be described later. Alternatively, the overlapping with the dielectric layer portion may be performed first, and then the firing may be performed.
第13図は誘電体層部分を示し、第13図のよ
うに誘電体層12の上に電極13を形成し、その
一端を左辺に引出して引出部fとする。その上に
第14図のように誘電体層14を形成した後に、
電極15,16,17,18,19を互に離間し
て形成し、その際にそれぞれの一端を第2〜12
図の引出部a,b,c,d,eに重なる位置に引
出して引出部a′,b′,c′,d′,e′とする。さらに
、
第15図のように全面に誘電体層20を積層す
る。この積層体を焼成した後、磁性体層部分と重
畳する。別法として、先に述べたように焼成前に
両者を重畳させてから一体に焼成結合する。 FIG. 13 shows a dielectric layer portion, and as shown in FIG. 13, an electrode 13 is formed on the dielectric layer 12, and one end of the electrode 13 is drawn out to the left side to form a lead-out portion f. After forming a dielectric layer 14 thereon as shown in FIG.
The electrodes 15, 16, 17, 18, and 19 are formed spaced apart from each other, and one end of each is connected to the second to twelfth electrodes.
It is pulled out to positions overlapping with the drawer parts a, b, c, d, and e in the figure to form the drawer parts a', b', c', d', and e'. moreover,
A dielectric layer 20 is laminated on the entire surface as shown in FIG. After firing this laminate, it is overlapped with the magnetic layer portion. Alternatively, as described above, the two may be overlapped before firing and then fired and bonded together.
得られた焼結複合積層体の周辺に露出する引出
端a,a′;b,b′;c,c′;d,d′;e,e′;及
びfのところにそれぞれ外部端子A,B,C,
D,E,Fを塗布・焼付けて本考案のデイレイラ
インを完成する。この回路構成は第1図に示す通
りである。端子Fはコンデンサの共通電極につな
がる接地用の端子である。端子A,B,C,D,
Eはコンデンサの反対電極につながり、また直列
インダクタの入力端から出力端まで順に各インダ
クタの前後にこれら反対電極を接続している。 External terminals A, A, and F are respectively attached to the lead-out ends a, a'; b, b'; c, c'; d, d'; e, e'; and f exposed around the periphery of the obtained sintered composite laminate. B,C,
Apply and bake D, E, and F to complete the day delay line of this invention. This circuit configuration is as shown in FIG. Terminal F is a grounding terminal connected to the common electrode of the capacitor. Terminals A, B, C, D,
E is connected to the opposite electrode of the capacitor, and these opposite electrodes are connected before and after each inductor in order from the input end to the output end of the series inductor.
以上のように、本考案によれば単純な積層法に
より所望のデイレイラインを容易に構成でき、し
かもこうして得られたデイレイラインは小型のチ
ツプ構造を有し、集積度の高いデイレイラインと
なる。 As described above, according to the present invention, a desired delay line can be easily constructed by a simple lamination method, and the delay line thus obtained has a small chip structure and is a highly integrated delay line.
第1図はデイレイラインの回路図、第2図ない
し第15図は本考案の実施例によるデイレイライ
ンの製造工程及び構造を示す平面図、および第1
6図は本考案のデイレイラインの斜視図である。
図中主な部分は次の通りである。1,3,5,
7,9,11……磁性体層、2,4,6,8,1
0……インダクタ用導体、12,14,20……
誘電体層、13,15,16,17,18……電
極、a,b,c,d,e,f,a′,b′,c′,d′,
e′……引出端、A,B,C,D,E,F……端子
電極。
FIG. 1 is a circuit diagram of a delay line, FIGS. 2 to 15 are plan views showing the manufacturing process and structure of a delay line according to an embodiment of the present invention, and FIG.
FIG. 6 is a perspective view of the delay line of the present invention. The main parts in the figure are as follows. 1, 3, 5,
7, 9, 11...magnetic layer, 2, 4, 6, 8, 1
0...Inductor conductor, 12, 14, 20...
Dielectric layer, 13, 15, 16, 17, 18... Electrode, a, b, c, d, e, f, a', b', c', d',
e'... Leading end, A, B, C, D, E, F... Terminal electrode.
Claims (1)
あつて、前記導体は前記磁性体層の層間から次の
層間へと周回する導体コイルを形成しており、前
記導体コイルの巻きはじめケ所、巻き終りケ所及
び巻きはじめから巻き終りに至る中間の少なくと
も1ケ所からそれぞれ別個の引出し導体によつて
周辺のそれぞれ異なるケ所に引出された端子電極
を有する第1の積層体と、複数組の容量形成用電
極と誘電体層との交互積層体であつて、前記各組
の電極は導体により周辺へ引出されている第2の
積層体との一体重畳体であつて、前記複数組の容
量形成用電極の一方の極性の引出端は前記コイル
状導体の複数の端子電極にそれぞれ接続し、前記
複数組の容量形成用電極の他方の極性はまとめて
独立の端子電極に接続されている積層体デイレイ
ライン。 A coil-forming conductor and a magnetic layer are alternately laminated, the conductor forming a conductor coil that goes around from one layer of the magnetic layer to the next, and where the conductor coil starts winding, A first laminate having terminal electrodes drawn out to different places around the periphery by separate lead-out conductors from the end of the winding and at least one place in the middle from the beginning of the winding to the end of the winding, and a plurality of sets of capacitance formation. a laminated body of alternately laminated electrodes and dielectric layers, each set of electrodes being an integrated body with a second laminated body led out to the periphery by a conductor, and the plurality of sets of electrodes for forming capacitances; A laminated derailleur in which one polarity of the lead-out end of the electrode is connected to a plurality of terminal electrodes of the coiled conductor, and the other polarity of the plurality of capacitance forming electrodes are collectively connected to an independent terminal electrode. in.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19399482U JPS5999507U (en) | 1982-12-23 | 1982-12-23 | Daylay line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19399482U JPS5999507U (en) | 1982-12-23 | 1982-12-23 | Daylay line |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5999507U JPS5999507U (en) | 1984-07-05 |
| JPH0134432Y2 true JPH0134432Y2 (en) | 1989-10-19 |
Family
ID=30417103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19399482U Granted JPS5999507U (en) | 1982-12-23 | 1982-12-23 | Daylay line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999507U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6077508A (en) * | 1983-10-05 | 1985-05-02 | Elmec Corp | Electromagnetic delay line |
-
1982
- 1982-12-23 JP JP19399482U patent/JPS5999507U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5999507U (en) | 1984-07-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4322698A (en) | Laminated electronic parts and process for making the same | |
| US6956455B2 (en) | Method of manufacturing laminated ceramic electronic component and laminated ceramic electronic component | |
| JP2655657B2 (en) | Structure of laminated application parts | |
| JPS5924535B2 (en) | Laminated composite parts | |
| JPH0134432Y2 (en) | ||
| JPH0310212B2 (en) | ||
| JPS6228891B2 (en) | ||
| JPH0529147A (en) | Laminated chip transformer | |
| JP2000216024A (en) | Multilayer inductor | |
| JPH0115160Y2 (en) | ||
| JPH0115159Y2 (en) | ||
| JPH01151212A (en) | Structure of laminate-applied component | |
| JPS6119179B2 (en) | ||
| JPS6031242Y2 (en) | LC composite parts | |
| JPH0447950Y2 (en) | ||
| JP2958804B2 (en) | Multilayer chip common mode choke coil | |
| JP2967843B2 (en) | Multilayer chip inductor and method of manufacturing the same | |
| JPS6229885B2 (en) | ||
| JPH0313729B2 (en) | ||
| JPS6031243Y2 (en) | composite parts | |
| JPS6328585Y2 (en) | ||
| JP3245835B2 (en) | Manufacturing method of multilayer inductor | |
| JPS5933248B2 (en) | composite electronic components | |
| JPH0132331Y2 (en) | ||
| JPS6017895Y2 (en) | LC composite parts |