JPH0310212B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a laminated component.

Multilayer components such as multilayer chip capacitors and multilayer chip inductors using printing technology are well known. 1 and 2 show an example of a multilayer chip capacitor, and FIGS. 3 and 4 show an example of a multilayer chip inductor. In a multilayer chip capacitor, dielectric layers 1, 2, 3, 4, and 5 are formed by printing a paste of insulating powder having dielectric properties, and dielectric layers 1, 2, 3, 4, and 5 are formed by printing a paste of metal powder such as Ag, Pd-Ag, etc. The electrode layers 6, 7, 8, and 9 are printed and laminated alternately from the bottom in the order shown in FIG. an external electrode 11 connected to one end of the electrodes 6 and 8;
and an external electrode 12 connected to one end of the electrodes 7 and 9 are formed by baking a conductive paste to form a chip capacitor. In a multilayer chip inductor, magnetic layers 13, 14, 15, 16, 17, 1 are formed by printing a paste of insulating powder having magnetic permeability.
8, and linear conductor layers 19, 20, 2 formed by printing a paste of metal powder such as Ag, Pd-Ag, etc.
1, 22, and 23 are printed and laminated alternately from the bottom in the order shown in Figure 3 (the dotted line area is the area where the conductor ends overlap), and the resulting laminate is sintered at a high temperature. A solid body 24 is formed, and external terminals 25 and 26 connected to the lead-out ends of the conductors are formed by baking a conductive paste to form a chip inductor.

However, when the number of laminated layers increases (sometimes 100 to 200 layers), the ratio of the total amount of dielectric layers or magnetic layers to the total amount of metal layers constituting the conductive layer (metal amount / dielectric or magnetic layer) When the amount (volume) exceeds a certain limit value, problems arise in that the layers of the sintered body tend to separate or crack. This is because the shrinkage ratio during firing is different between the metal and the insulator.

The purpose of the present invention is to solve such problems, and in a laminated component made of a multilayer laminate of metal and insulator layers, there is a layer at the interface between the layers due to the difference in shrinkage ratio during firing. This problem is overcome by intervening an intermediate layer that absorbs the internal stresses that arise.

As the intermediate layer, the same kind or the same material as the insulator used in the lamination can be used, a different material such as glass can be used, or a mixture material of the insulator and metal used in the lamination can be used. In general, any material can be used as long as it can absorb or alleviate the internal stress caused by the difference in shrinkage ratio.

The laminated component of the present invention will be explained in detail below with reference to the drawings. FIG. 5 shows an embodiment in which the present invention is embodied in a multilayer chip capacitor, in which a multilayer capacitor similar to that described in connection with FIG. interpose an intermediate layer of More specifically, the dielectric layer 30, one electrode layer 31, and the other electrode layer 32 (for simplicity, all the same types of layers 30, 3
1 and 32 respectively) are laminated by the method shown in FIG. The layer 34 and the other electrode layer 35 are similarly laminated to form part B, and the thus obtained laminated body is fired at a high temperature to form a sintered body having an integral structure. Finally, external terminals 36 and 37 are baked to form the multilayer chip capacitor of the present invention.

6-7 show other embodiments of the invention. This example embodies the invention in a multilayer chip inductor, which is fabricated using the method described in connection with FIG. The multilayer chip inductor has two parts C,
In relation to FIG. The portion C is formed by laminating layers alternately in the manner described above, and a magnetic layer 43', which is thicker than the other magnetic layers, is printed on top of it as shown in FIG. 7 (for example, by repeating the same layer 41 several times). printing), a conductor 42' connected to the lower conductor 42 is printed on that surface,
On top of that, a similarly thick magnetic layer 43'' is printed, and then a conductor 45' connected to the conductor 42' is printed, and then a magnetic layer 44 of the same thickness as the magnetic layer 41 is printed on top of that.
(all layers are indicated by 44 for simplicity) and a coil-forming conductor layer 45 are alternately laminated in the same manner as shown in FIG. 3 to form a laminate of part D. layer 4
3' and 43'' are combined to form the intermediate layer 43.The thus obtained laminate is fired at a high temperature to form an integral sintered body, and the external terminals 46 and 47 are connected to the lead conductor. The laminated chip inductor of the present invention is manufactured by baking the inductor into a multilayer chip inductor.

With the above structure, the internal stress caused by the difference in shrinkage rate during firing between the metal layer and the insulator layer is absorbed by the intermediate layer, eliminating the problems of distortion, cracking, and delamination. . Note that the material and thickness of the intermediate layer and the number of intermediate layers can be changed as necessary, but those skilled in the art can easily select the optimum one experimentally. Further, although the embodiments have been described only with respect to a multilayer chip inductor and a multilayer chip capacitor, the present invention can be easily applied to a multilayer component that is a composite of these.

[Brief explanation of the drawing]

Figure 1 is an exploded perspective view of a conventional four-layer capacitor, Figure 2 is a perspective view of the finished product, Figure 3 is an exploded perspective view of a conventional multilayer chip inductor, and Figure 4 is a perspective view of the finished product. 5 is a cross-sectional view of a multilayer chip capacitor according to a first embodiment of the present invention, FIG. 6 is a cross-sectional view of a multilayer chip inductor according to a second embodiment of the present invention, and FIG. It is a perspective view showing the details of the section. The main parts in the figure are as follows. 30, 33: dielectric layer, 32, 34: electrode layer,
36, 37: external terminal, 40: intermediate layer, 41, 4
4: Magnetic layer, 42, 45: Coil forming conductor,
43: Middle class.

Claims (1)

[Scope of Claims] 1. In a laminate component consisting of a printed alternating laminate of a large number of conductive layers and insulating layers, the alternating laminate is formed into two or more parts in a plane parallel to the plane in which the layers extend. the divided interface is sufficiently thicker than the thickness of the insulating layer and wide enough to cover the entire interface in order to absorb internal stress caused by the difference in shrinkage ratio between the conductive layer and the insulating layer. A laminated part characterized by interposing an intermediate layer of. 2. The laminated component according to item 1 above, wherein the conductive layer is a coil-forming conductor that extends spirally from one layer to another of the insulating layers via the edge of the insulating layer, and the insulating layer is a magnetic material. . 3. The laminated component according to item 1 or 2 above, wherein the conductive layer is a capacitor electrode sandwiched between insulating layers, and the insulating layer is a dielectric. 4. The laminated component according to item 1 or 2 above, wherein the intermediate layer is formed of a material selected from dielectrics, insulators such as glass, magnetic materials, and mixtures of these and metal powders.