JPH0134509B2 - - Google Patents

Info

Publication number
JPH0134509B2
JPH0134509B2 JP57232814A JP23281482A JPH0134509B2 JP H0134509 B2 JPH0134509 B2 JP H0134509B2 JP 57232814 A JP57232814 A JP 57232814A JP 23281482 A JP23281482 A JP 23281482A JP H0134509 B2 JPH0134509 B2 JP H0134509B2
Authority
JP
Japan
Prior art keywords
film
forming
electrode
insulating film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57232814A
Other languages
Japanese (ja)
Other versions
JPS59119980A (en
Inventor
Okio Yoshida
Nozomi Harada
Hiroshi Washida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP57232814A priority Critical patent/JPS59119980A/en
Publication of JPS59119980A publication Critical patent/JPS59119980A/en
Publication of JPH0134509B2 publication Critical patent/JPH0134509B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/191—Photoconductor image sensors

Landscapes

  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は固体撮像装置に係り、特に電荷転送
素子と光電変換膜を組合せて構成される固体撮像
装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a solid-state imaging device, and particularly to a method for manufacturing a solid-state imaging device configured by combining a charge transfer element and a photoelectric conversion film.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

固体撮像素子は従来の撮像管と比べて小型、軽
量、高信頼性のカメラとなり、残像の殆ない良質
の画像を得ることができるという利点を有する。
Solid-state image sensors have the advantage of being smaller, lighter, and more reliable cameras than conventional image pickup tubes, and of being able to obtain high-quality images with almost no afterimages.

しかしながら、固体撮像素子は主としてSiウエ
ハ上に形成され、使用可能な感度波長領域が可視
近辺に限定される欠点、また光電変換を行うPn
ホトダイオードの有効感光部と信号電荷転送を行
う無効感光部があり十分な感度が得られず、モア
レ等の偽信号が出やすいといつた撮像管にはない
欠点が存在する。このような欠点を除く固体撮像
素子として、従来の固体撮像素子をそのまま走査
部として使用し、その上に設けた光導電体膜にて
光電変換を行う構造のものが提案されている。第
1図はこのような光導電体膜と電荷転送素子を組
合せたインタライン転送形固体撮像素子の一画素
部分の断面図である。P型Si基板10を用い、n+
層111とその上に絶縁膜を介して配設したポリ
Siからなる転送ゲート電極121,122により埋
込みチヤネル型の垂直読出しCCDを構成し、又、
n+層112により信号電荷を蓄積する蓄積ダイオ
ードを構成している。このようにCCDと蓄積ダ
イオードが形成された基板の蓄積ダイオード部分
には熱酸化膜を含む第一酸化膜13にエツチング
を行い、n+層112を露出させてAlなどの第一電
極14を所定形状に形成する。この後更に第二酸
化膜15を積層してこれにエツチングを行い、第
一電極14の一部を露出させてAlなどの第二電
極16を形成する。この上部にアモルフアスSi
(a―Si)などの光導電体膜17をスパツタやグ
ロー放電分解法により形成し、更に透明電極膜1
8を形成して、走査部と光電変換部を有する固体
撮像素子を得る。
However, solid-state imaging devices are mainly formed on Si wafers, and have the drawback that the usable sensitivity wavelength range is limited to the visible region, and Pn which performs photoelectric conversion
They have disadvantages not found in image pickup tubes, such as the effective photosensitive area of the photodiode and the ineffective photosensitive area that transfers signal charges, making it difficult to obtain sufficient sensitivity and easily producing false signals such as moiré. As a solid-state imaging device that eliminates these drawbacks, a structure has been proposed in which a conventional solid-state imaging device is used as it is as a scanning section, and a photoconductor film provided thereon performs photoelectric conversion. FIG. 1 is a cross-sectional view of one pixel portion of an interline transfer type solid-state image pickup device that combines such a photoconductor film and a charge transfer device. Using a P-type Si substrate 10, n +
Layer 11 1 and the polyester layer disposed on it with an insulating film interposed thereon.
The transfer gate electrodes 12 1 and 12 2 made of Si constitute a buried channel type vertical readout CCD, and
The n + layer 11 2 constitutes a storage diode that stores signal charges. In the storage diode part of the substrate where the CCD and the storage diode are formed, the first oxide film 13 including the thermal oxide film is etched to expose the n + layer 112 and the first electrode 14 made of Al or the like is etched. Form into a predetermined shape. Thereafter, a second oxide film 15 is further laminated and etched to expose a portion of the first electrode 14 to form a second electrode 16 made of Al or the like. At the top of this amorphous Si
A photoconductor film 17 such as (a-Si) is formed by sputtering or glow discharge decomposition method, and a transparent electrode film 1
8 to obtain a solid-state image sensor having a scanning section and a photoelectric conversion section.

なお、第一、第二の電極14,16をそれぞれ
ポリSi、モリブデンとして同様の構造としたもの
が特開昭57―32183号公報に記載されている。
Note that a similar structure in which the first and second electrodes 14 and 16 are made of poly-Si and molybdenum, respectively, is described in JP-A-57-32183.

このような固体撮像素子においては、従来なら
ば蓄積ダイオードの部分のみが一画素として有効
に働いたのに対して、第二電極16の部分が一画
素として有効な光電変換を行うので感度が増加す
る利点が生ずる。この場合、本来第一電極14上
に光導電体膜17を形成してもよいのであるが、
これでは基板表面の凹凸による段差が2〜4μm
程度あつてエツチング部に急峻な段差が形成され
ているため、光導電体膜が段差で不連続になり、
画像の欠陥を生じたり、極端な場合は感度が得ら
れず出画不良となつてしまう。これを防ぐため、
図示のように第二酸化膜15と第二電極16を用
いて段差を解消しつゝ、なるべく平滑な面に光導
電体膜17を形成することが行われている。しか
しこの構成であつても、基板表面の段差は完全に
は解消されず画像欠陥が出やすい。また製造工程
も複雑であり、パターンのずれによる不良を生ず
る危険が大きい。
In such a solid-state image sensor, whereas conventionally only the storage diode functioned effectively as one pixel, the second electrode 16 performs effective photoelectric conversion as one pixel, increasing sensitivity. There are advantages to doing so. In this case, originally the photoconductor film 17 may be formed on the first electrode 14, but
With this, the level difference due to unevenness on the substrate surface is 2 to 4 μm.
Because a certain degree of steep steps are formed in the etched area, the photoconductor film becomes discontinuous due to the steps.
Defects may occur in the image, or in extreme cases, sensitivity may not be obtained, resulting in poor image output. To prevent this,
As shown in the figure, a second oxide film 15 and a second electrode 16 are used to eliminate the step difference while forming a photoconductor film 17 on a surface as smooth as possible. However, even with this configuration, the level difference on the substrate surface cannot be completely eliminated and image defects are likely to occur. Furthermore, the manufacturing process is complicated, and there is a high risk of defects due to pattern misalignment.

〔発明の目的〕[Purpose of the invention]

本発明は上記の点に鑑みなされたもので、固体
走査部と光電変換部を接続する新しい電極構成を
導入し、光電変換部の欠陥を減少した固体撮像装
置の製造方法を提供することを目的とする。
The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a solid-state imaging device that reduces defects in the photoelectric conversion section by introducing a new electrode configuration for connecting the solid-state scanning section and the photoelectric conversion section. shall be.

〔発明の概要〕[Summary of the invention]

本発明は、蓄積ダイオードと走査部を集積形成
した半導体基板上に絶縁膜を介して光電変換膜を
積層して構成される固体撮像装置を製造するに当
たつて、蓄積ダイオードと走査部が形成された基
板上に絶縁膜を堆積し、その表面にレジスト膜を
塗布して表面を平坦化した後、レジスト膜と絶縁
膜に対してエツチング速度が等しくなる条件に設
定されたドライエツチングにより全面エツチング
を行なつて絶縁膜表面を平坦化する。そして平坦
化した絶縁膜の各蓄積ダイオード上にコンタクト
孔を開け、このコンタクト孔に下部電極の一部と
なる垂直電極部を埋込み形成すると共に、各垂直
電極部と接続されて下部電極の残部となる平面電
極部を形成し、その後この上に光電変換膜を形成
し、更に上部電極となる透明導電膜を形成するこ
とを特徴とする。
The present invention provides a method for manufacturing a solid-state imaging device in which a photoelectric conversion film is laminated via an insulating film on a semiconductor substrate in which a storage diode and a scanning part are formed in an integrated manner. After depositing an insulating film on the substrate and flattening the surface by applying a resist film to the surface, the entire surface is etched by dry etching, which is set to have the same etching rate for the resist film and the insulating film. The surface of the insulating film is planarized by doing this. Then, a contact hole is formed on each storage diode in the flattened insulating film, and a vertical electrode part that will become a part of the lower electrode is buried in this contact hole, and is connected to each vertical electrode part and connected to the rest of the lower electrode. The method is characterized in that a planar electrode portion is formed, then a photoelectric conversion film is formed thereon, and a transparent conductive film that becomes an upper electrode is further formed.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、光電変換膜を設ける面を平坦
化して画像欠陥の発生を効果的に防止することが
できる。また電極構造、製造工程とも従来より簡
単になり、従つて歩留り向上も図られる。
According to the present invention, it is possible to flatten the surface on which the photoelectric conversion film is provided and effectively prevent the occurrence of image defects. Furthermore, the electrode structure and manufacturing process are simpler than conventional ones, and yields can therefore be improved.

〔発明の実施例〕[Embodiments of the invention]

第2図は本発明の一実施例のインタライン転送
形固体撮像素子の一画素部分を示す断面図であ
る。P型Si基板20を用い、これにn+層211を
形成し、その上にゲート酸化膜を介してポリSiか
らなる転送ゲート電極221,222を形成して埋
込みチヤネル型の垂直読出しCCDを構成し、こ
れに隣接してn+層212により蓄積ダイオードを
構成している点は従来と同じである。これら
CCDと蓄積ダイオードが形成された基板表面の
酸化膜23は表面が平坦化されている。この酸化
23のn+層212上にコンタクト穴があけられ、
ここに金属などの電機材料を表面が平坦になるよ
うに充填して垂直電極部241を形成し、更にこ
の垂直電極部241に接して酸化膜23上に平面
電極部242を形成して、各画素に対応する下部
電極24を構成している。そしてこの上に、光導
電体膜25を積層し上部電極として全面に透明導
電膜26を形成している。
FIG. 2 is a sectional view showing one pixel portion of an interline transfer type solid-state image sensor according to an embodiment of the present invention. A P-type Si substrate 20 is used, an n + layer 21 1 is formed thereon, and transfer gate electrodes 22 1 and 22 2 made of poly-Si are formed on it via a gate oxide film to perform buried channel type vertical readout. The structure is the same as the conventional one in that a CCD is formed and an n + layer 21 2 adjacent to this forms a storage diode. these
The surface of the oxide film 23 on the surface of the substrate on which the CCD and the storage diode are formed is flattened. A contact hole is made on the n + layer 21 2 of this oxide 23,
A vertical electrode portion 24 1 is formed by filling this with an electrical material such as metal so that the surface is flat, and a flat electrode portion 24 2 is further formed on the oxide film 23 in contact with the vertical electrode portion 24 1 . This constitutes a lower electrode 24 corresponding to each pixel. A photoconductor film 25 is laminated thereon, and a transparent conductive film 26 is formed over the entire surface as an upper electrode.

この構造を得る具体的な製造工程例を第3図を
参照して説明する。なお、第2図と対応する部分
には第2図と同一符号を付してある。第3図aは
従来と同様の工程で形成される。例えば、P型Si
電極20にまずn+層211,212を拡散形成し、
この上にゲート酸化膜を介してポリシリコンから
なる転送ゲート電極221,222を形成する。こ
の表面全体は熱酸化膜を含む第一酸化膜231で
おおわれるが、凹凸がある。そこで次に、同図b
に示すようにCVD法などにより第二酸化膜232
を厚く堆積し、更にレジスト膜27を塗布して表
面を略平坦化する。そして、レジスト膜27と第
二酸化膜232に対してエツチング速度が等しく
なる条件の反応性イオンエツチング(RIE)法に
より全面エツチングを行つて同図cの構造を得
る。こうして酸化膜23の表面を平坦化した後、
同図dに示すように、レジスト膜28をマスクと
してRIE法により蓄積ダイオードのn+層212上
にコンタクト穴をあけ、全面に金属膜29を薄く
被着する。この金属膜29は、コンタクト穴に電
気メツキにより電極を充填するために設けるもの
で、Ni、Cu、Pb、Al、Zn、Ti、Mo等から選ば
れる。そしてレジスト膜28を除去することでコ
ンタクト穴の内にのみ金属膜29を残し、同図e
に示すように電気メツキ法によつてこのコンタク
ト穴に垂直電極部241を充填し、更にAl等の金
属膜の蒸着、パターニングにより、平面電極部2
42を形成して、下部電極24を作る。
A specific example of the manufacturing process for obtaining this structure will be explained with reference to FIG. 3. Note that parts corresponding to those in FIG. 2 are given the same reference numerals as in FIG. 2. FIG. 3a is formed by the same process as the conventional one. For example, P-type Si
First, n + layers 21 1 and 21 2 are formed by diffusion on the electrode 20,
Transfer gate electrodes 22 1 and 22 2 made of polysilicon are formed thereon via a gate oxide film. This entire surface is covered with a first oxide film 23 1 including a thermal oxide film, but there are irregularities. Therefore, next,
As shown in FIG. 2, the second oxide film 23 2 is
A resist film 27 is further applied to substantially flatten the surface. Then, the entire surface is etched by reactive ion etching (RIE) under conditions such that the resist film 27 and the second oxide film 232 have equal etching rates to obtain the structure shown in FIG. After flattening the surface of the oxide film 23 in this way,
As shown in Figure d, a contact hole is made on the n + layer 21 2 of the storage diode by the RIE method using the resist film 28 as a mask, and a metal film 29 is thinly deposited on the entire surface. This metal film 29 is provided to fill the contact hole with an electrode by electroplating, and is selected from Ni, Cu, Pb, Al, Zn, Ti, Mo, etc. Then, by removing the resist film 28, the metal film 29 is left only inside the contact hole.
As shown in FIG. 2, this contact hole is filled with a vertical electrode portion 24 1 by electroplating, and then a flat electrode portion 2 is formed by vapor deposition and patterning of a metal film such as Al.
4 2 to form the lower electrode 24.

なお電気メツキは例えばニツケルメツキであ
り、次のように行う。まず、付着性を良くするた
めにダブルジンケート法による表面処理を行う。
次に通称ワツト浴と呼ばれるメツキ液で電気メツ
キを行うが、このとき微細な多くのコンタクト穴
に一様にメツキを行うために、ワツト浴の濃度を
通常の1/2に希釈し、またメツキ液を撹拌フアン
により十分に撹拌する。これらのメツキ条件は実
験的に求められたもので、これにより微細なコン
タクト穴に一様にニツケルを埋込むことができ
た。
The electric plating is, for example, nickel plating, and is carried out as follows. First, surface treatment is performed using a double zincate method to improve adhesion.
Next, electroplating is performed using a plating liquid commonly known as a Watto bath.In order to uniformly plate many fine contact holes, the concentration of the Watto bath is diluted to 1/2 of the normal concentration. Stir the liquid thoroughly using a stirring fan. These plating conditions were determined experimentally, and made it possible to uniformly embed nickel into the minute contact holes.

このようにして下部電極24を形成した後、第
3図fに示すように、a―Siなどからなる光導電
体膜25を全面に形成し、更に上部電極として透
明導電膜26を全面に形成して完成する。
After the lower electrode 24 is formed in this way, as shown in FIG. and complete it.

この実施例によれば、従来の第1図の固体撮像
素子におけるように二重の電極をはりめぐらすこ
となく、簡単な構成で蓄積ダイオードと光導電体
膜を直接結合する下部電極が形成できる。また工
程の短縮化により歩留り向上も期待でき、更に平
坦化面に平面電極部が形成されるため表面の凹凸
段差は平面電極部の厚みだけとなり、上部の光導
電体膜に対しても十分な平滑面を提供できる。従
来構造では段差を少なくするため、例えば光導電
体膜を必要以上に厚くして光導電体膜自身にも段
差解消の役割をもたせていた。このため光導電体
膜厚は例えば4μmにもなり、電界が十分に膜中
に印加されず、また光入射が透明導電膜側から行
われるため信号電荷が膜中を十分走行できずに消
滅する等の理由により、光電感度を損うことが多
い。これに対し本実施例では光導電体膜は2μm
又はこれ以下でもよく、大きな光電感度が得られ
る。
According to this embodiment, a lower electrode that directly connects the storage diode and the photoconductor film can be formed with a simple structure without having to wrap double electrodes as in the conventional solid-state imaging device shown in FIG. In addition, an improvement in yield can be expected due to the shortening of the process.Furthermore, since the planar electrode portion is formed on the flattened surface, the only unevenness level difference on the surface is the thickness of the planar electrode portion, and there is sufficient thickness for the photoconductor film on the top. Can provide a smooth surface. In the conventional structure, in order to reduce the level difference, for example, the photoconductor film was made thicker than necessary so that the photoconductor film itself also had the role of eliminating the level difference. For this reason, the photoconductor film thickness is, for example, 4 μm, and an electric field is not sufficiently applied to the film, and since light is incident from the transparent conductive film side, signal charges cannot travel sufficiently through the film and disappear. For these reasons, photoelectric sensitivity is often impaired. On the other hand, in this example, the photoconductor film is 2 μm thick.
Or it may be less than this, and high photoelectric sensitivity can be obtained.

そして本実施例によれば、上述のように段差が
少ないため、白キズや素地ムラなどと呼ばれるノ
イズが少なくなり、高画質の出画が可能となる。
According to this embodiment, since there are fewer steps as described above, noise called white scratches and unevenness on the substrate is reduced, and high-quality images can be output.

更に蓄積ダイオードへの垂直電極部の形成工程
は素子チツプ中の他のコンタクトホールの形成工
程、電極配線工程と同時にでき、この点でも工程
の短縮が図られる。
Furthermore, the process of forming the vertical electrode portion of the storage diode can be performed simultaneously with the process of forming other contact holes in the device chip and the process of wiring the electrodes, and in this respect as well, the process can be shortened.

次に上記実施例と同様の構造を得る別の製造工
程側を第4図a〜hを用いて説明する。第2図、
第3図と対応する部分にはやはり同一符号を付し
てある。第4図a〜cの工程は第3図a〜cと同
じである。本実施例では平坦化した酸化膜23の
表面に、第4図dに示すようにまず平面電極部2
42を先に形成する。この後同図eに示すように
レジスト膜30をマスクとしてRIE法によりn+層
212上にコンタクト穴を形成する。そして次に
同図fに示すように金属膜を十分厚く被着してコ
ンタクト穴を充填する垂直電極部241を形成す
る。この後、レジスト膜30をはくりして同図g
に示すように不要な金属膜をリフトオフし、この
上に同図hに示すように光導電体膜25、次いで
透明導電膜26を形成して完成する。
Next, another manufacturing process for obtaining a structure similar to that of the above embodiment will be explained using FIGS. 4a to 4h. Figure 2,
Portions corresponding to those in FIG. 3 are given the same reference numerals. The steps in FIGS. 4a to 4c are the same as those in FIGS. 3a to 3c. In this embodiment, a planar electrode portion 2 is first placed on the surface of the planarized oxide film 23 as shown in FIG. 4d.
4 Form 2 first. Thereafter, as shown in FIG. 5E, a contact hole is formed on the n + layer 21 2 by the RIE method using the resist film 30 as a mask. Then, as shown in FIG. 5F, a metal film is deposited sufficiently thickly to form a vertical electrode portion 24 1 filling the contact hole. After this, the resist film 30 is peeled off and
The unnecessary metal film is lifted off as shown in FIG. 2, and a photoconductor film 25 and then a transparent conductive film 26 are formed thereon as shown in FIG.

本実施例によつても、先の実施例と同様の効果
が得られることは明らかである。
It is clear that this embodiment also provides the same effects as the previous embodiment.

以上の各実施例では、表面平滑化のため第一酸
化膜上に第二酸化膜を重ねたが、第一酸化膜を十
分厚くしてこれだけ平坦化を行つてもよい。また
垂直電極部の形成方法は、上記各実施例に限ら
ず、無電解メツキ法やイオンプレーテイング法を
用いることができ、またコンタクト穴が大きい場
合にはハンダやCVDによる充填を行つてもよい。
In each of the above embodiments, the second oxide film was layered on the first oxide film to smooth the surface, but the first oxide film may be made sufficiently thick to achieve this level of planarization. In addition, the method for forming the vertical electrode portion is not limited to the above embodiments, and electroless plating method or ion plating method may be used, and if the contact hole is large, it may be filled with solder or CVD. .

また表面平坦化の方法として、例えばPSG膜
を堆積してN2ガス中、1100℃程で熱処理して
PSG膜をメルトさせる方法を用いることも可能
である。
In addition, as a method for surface flattening, for example, a PSG film is deposited and heat-treated at about 1100℃ in N2 gas.
It is also possible to use a method of melting the PSG film.

更に以上の実施例では、信号電荷走査部として
埋込みチヤネル型垂直読出しCCDをもつインタ
ライン転送形CCDを前提としたが、MOS形や
CPD形の走査部をもつものにも本発明を適用で
きる。また絶縁膜としてSiO2等の酸化膜を用い
た例を説明したが、Si3N4膜やこれらの複合膜を
用いることもできる。光導体膜としてもa―Siの
他、Sb2S3、Se―As―Te、CdSe、CdZnTeなど
を用い得ることは明らかであり、また光導電膜で
なく、当起電力を生ずる膜を用いてもよい。更に
下部電極材料としては、NiやAlの他、Au、Ag、
Pt、Al―Si、In、Snなどの金属あるいはポリSi
などを適宜組合せて用いることができることは明
らかである。
Furthermore, in the above embodiments, an interline transfer type CCD with an embedded channel type vertical readout CCD was used as the signal charge scanning section, but a MOS type or
The present invention can also be applied to those having a CPD type scanning section. Furthermore, although an example has been described in which an oxide film such as SiO 2 is used as the insulating film, it is also possible to use a Si 3 N 4 film or a composite film thereof. It is clear that in addition to a-Si, Sb 2 S 3 , Se-As-Te, CdSe, CdZnTe, etc. can be used as the photoconductive film, and it is also possible to use a film that generates the electromotive force instead of a photoconductive film. It's okay. In addition to Ni and Al, the lower electrode materials include Au, Ag,
Metals such as Pt, Al-Si, In, Sn or poly-Si
It is clear that these can be used in appropriate combinations.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の固体撮像素子の一画素部分を示
す断面図、第2図は本発明の一実施例の固体撮像
素子の一画素部分を示す断面図、第3図a〜fは
その製造工程例を示す図、第4図a〜hは他の製
造工程例を示す図である。 20…P型Si基板、211…n+層(埋込みチヤ
ネル部)、212…n+層(蓄積ダイオード部)、2
21,222…転送ゲート電極、23,231,2
32…酸化膜、241…垂直電極部、242…平面
電極部、24…下部電極、25…光導電体膜、2
6…透明導電膜。
FIG. 1 is a cross-sectional view showing one pixel portion of a conventional solid-state image sensor, FIG. 2 is a cross-sectional view showing one pixel portion of a solid-state image sensor according to an embodiment of the present invention, and FIGS. Figures illustrating process examples, FIGS. 4a to 4h are views showing other manufacturing process examples. 20...P-type Si substrate, 21 1 ...n + layer (embedded channel section), 21 2 ...n + layer (storage diode section), 2
2 1 , 22 2 ...transfer gate electrode, 23, 23 1 , 2
3 2 ... Oxide film, 24 1 ... Vertical electrode section, 24 2 ... Planar electrode section, 24 ... Lower electrode, 25 ... Photoconductor film, 2
6...Transparent conductive film.

Claims (1)

【特許請求の範囲】 1 半導体基板に複数の信号電荷蓄積ダイオード
とその信号電荷を読み出す走査部とを形成する工
程と、 前記蓄積ダイオードと走査部が形成された基板
上に絶縁膜を堆積する工程と、 前記絶縁膜上にレジスト膜を塗布して表面を平
坦化した後、レジスト膜と絶縁膜に対してエツチ
ング速度が等しくなる条件に設定されたドライエ
ツチングにより全面エツチングを行なつて絶縁膜
表面を平坦化する工程と、 前記絶縁膜の前記各蓄積ダイオード上にコンタ
クト孔を開け、このコンタクト孔に下部電極の一
部となる垂直電極部を埋込み形成する工程と、 前記絶縁膜上に前記各垂直電極部と接続されて
下部電極の残部となる平面電極部を形成する工程
と、 前記下部電極が形成された基板上全面に光電変
換膜を形成する工程と、 前記光電変換膜上に上部電極となる透明導電膜
を形成する工程と、 を備えたことを特徴とする固体撮像装置の製造方
法。
[Claims] 1. A step of forming a plurality of signal charge storage diodes and a scanning section for reading out the signal charges on a semiconductor substrate, and a step of depositing an insulating film on the substrate on which the storage diodes and the scanning section are formed. After applying a resist film on the insulating film to planarize the surface, the entire surface of the insulating film is etched by dry etching under conditions where the etching rate is equal for the resist film and the insulating film. A step of forming a contact hole on each of the storage diodes in the insulating film and embedding a vertical electrode portion that will become a part of a lower electrode in the contact hole; forming a planar electrode portion connected to the vertical electrode portion and serving as the remainder of the lower electrode; forming a photoelectric conversion film over the entire surface of the substrate on which the lower electrode is formed; and forming an upper electrode on the photoelectric conversion film. 1. A method for manufacturing a solid-state imaging device, comprising: a step of forming a transparent conductive film.
JP57232814A 1982-12-25 1982-12-25 Solid state image pickup device Granted JPS59119980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57232814A JPS59119980A (en) 1982-12-25 1982-12-25 Solid state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57232814A JPS59119980A (en) 1982-12-25 1982-12-25 Solid state image pickup device

Publications (2)

Publication Number Publication Date
JPS59119980A JPS59119980A (en) 1984-07-11
JPH0134509B2 true JPH0134509B2 (en) 1989-07-19

Family

ID=16945186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57232814A Granted JPS59119980A (en) 1982-12-25 1982-12-25 Solid state image pickup device

Country Status (1)

Country Link
JP (1) JPS59119980A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2290723A2 (en) 2009-08-28 2011-03-02 FUJIFILM Corporation Photoelectric conversion element and imaging device
US8686408B2 (en) 2010-02-25 2014-04-01 Fujifilm Corporation Photoelectric conversion device, imaging device and production methods thereof
US8809847B2 (en) 2010-03-24 2014-08-19 Fujifilm Corporation Photoelectric conversion device and imaging device

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05198787A (en) * 1991-11-08 1993-08-06 Canon Inc Solid-state imaging device and manufacturing method thereof
JP2011071481A (en) 2009-08-28 2011-04-07 Fujifilm Corp Solid-state imaging device, process of making solid-state imaging device, digital still camera, digital video camera, mobile phone, and endoscope
JP5637751B2 (en) 2009-08-28 2014-12-10 富士フイルム株式会社 Solid-state imaging device and manufacturing method of solid-state imaging device
JP2014225527A (en) * 2013-05-15 2014-12-04 キヤノン株式会社 Detection device and detection system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2290723A2 (en) 2009-08-28 2011-03-02 FUJIFILM Corporation Photoelectric conversion element and imaging device
US8686408B2 (en) 2010-02-25 2014-04-01 Fujifilm Corporation Photoelectric conversion device, imaging device and production methods thereof
US8809847B2 (en) 2010-03-24 2014-08-19 Fujifilm Corporation Photoelectric conversion device and imaging device

Also Published As

Publication number Publication date
JPS59119980A (en) 1984-07-11

Similar Documents

Publication Publication Date Title
US7791158B2 (en) CMOS image sensor including an interlayer insulating layer and method of manufacturing the same
US8169011B2 (en) Image sensor and method of manufacturing the same
JP2000012817A (en) Solid-state imaging device and method of manufacturing the same
JP2797984B2 (en) Solid-state imaging device and method of manufacturing the same
JPS6045057A (en) Manufacture of solid-state image pickup device
US8729650B2 (en) Solid-state imaging device and method of fabricating the same
JPH05206437A (en) Solid-state imaging device and manufacturing method thereof
JP3402429B2 (en) Solid-state imaging device and method of manufacturing the same
JPS59119980A (en) Solid state image pickup device
JP5706061B2 (en) Method for assembling two substrates using molecular bonds
JPS5861663A (en) Manufacture of solid-state image pickup device
JP2003188368A (en) Method for manufacturing solid-state imaging device
JPS6051376A (en) Solid-state image pickup device
JPH02262369A (en) Solid image pick-up device and manufacture thereof
JP2007188964A (en) Solid-state imaging device and manufacturing method thereof
JPH0669483A (en) Picture element of solid-state image pickup and its operation and production
JPS59151575A (en) Solid-state image pickup element
JP2008235516A (en) Solid-state imaging device and manufacturing method thereof
JP2525780B2 (en) Stacked solid-state imaging device
JPS6047574A (en) Solid-state image pickup device
JPS59119760A (en) Solid-state image pickup element
JPS6322469B2 (en)
TW594983B (en) Method for manufacturing photodiode and the structure thereof
JPH04240771A (en) Stacked solid-state image sensing element
JPH1126738A (en) Solid-state imaging device and method of manufacturing the same