JPH0135357B2 - - Google Patents

Description

4-4 Multiplying means for multiplying the absolute value from the subtracting means by a speed coefficient value corresponding to one of the speeds of attack, decay, and release of the envelope; and 4-5 Output from the multiplication means. 4-6 Complement means for converting the signal from the multiplication means into a complement based on the sign bit from the subtraction means when the sign bit represents a negative value, and outputting the signal without complementation when the sign bit represents a positive value; The output from the complement means for each sound channel,
A plurality of envelope waveforms corresponding to the plurality of sound generation channels are formed by time-division accumulation, and the accumulated value for each sound generation channel is output as the amplitude value of the envelope waveform, and the accumulated value is a counter means for supplying the second input of the subtracting means; 4-7, 4-8 storing level data corresponding to the attack level, sustain level and release level of the envelope waveform; 4-2 Envelope level storage means for supplying to the first input of the subtraction means; 4-2 storing speed coefficient values corresponding to the respective speeds of attack, decay and release in the envelope waveform; 4-3 maximum value detection means for detecting that the accumulated value from the counter means has reached the maximum value of the envelope; and A51 the accumulated value from the counter means. minimum value detection means for detecting that has reached the minimum value of the envelope and releasing the allocation of the corresponding pronunciation channel;
NOR40 Based on the key press signal from the key assigner, read the attack level data corresponding to the attack of the envelope from the envelope level storage means, and read the attack speed coefficient value corresponding to the attack part of the envelope from the envelope speed coefficient storage means. , reads the sustain level from the envelope level storage means on the condition that the maximum value is detected by the maximum value detection means, reads the decay speed coefficient value from the envelope speed coefficient storage means, and reads the decay speed coefficient value from the envelope speed coefficient storage means, based on the key release signal from the key assigner. readout means 4-1 for reading a release level from the envelope level storage means and a control to read a release speed coefficient from the envelope speed coefficient storage means; The electronic device is characterized by numerically controlling the generation of envelopes corresponding to the plurality of sounding channels by switching the level data and the speed coefficient value according to attack, decay, and release of the envelope based on a key release signal. musical instrument.

[Detailed description of the invention]

The present invention relates to a digitally processed electronic musical instrument that is equipped with an envelope waveform generation circuit that provides smooth attack and release with a small memory capacity.

Conventionally, in a device that has a large number of key switches, such as the keyboard of an electronic musical instrument, in order to transfer the information associated with the opening and closing of the switches to the required circuits, the amount of wiring would be enormous if you tried to connect each switch directly to the circuit. It is uneconomical. Furthermore, if a semiconductor integrated circuit or the like is to be used, the number of pins will be too large, making it difficult to use as is.

Currently, in view of these points, all switches are scanned for a predetermined period of time, and a pulse is generated at the time corresponding to the key switch turned on in the time sequence according to the scan, and a pulse is generated between many switches and the required circuit. A method to save wiring is being considered.
For example, a key code multiplexing method is generally used that scans each key switch in a time-division manner and transmits information about the switch turned on as a TDM (time division modulation) signal or a PCM (pulse code modulation) signal. However, since the time required to scan all the key switches is fixed, a fixed scanning time is required even when only a few key switches are turned on, resulting in waste.

When playing a normal keyboard instrument, the number of keys that are turned on at the same time is 11, considering both hands and feet. If we consider one block to be one octave unit, it is impossible to press keys for more than two octaves with one hand, so five blocks is the maximum number of blocks that can be occupied at the same time. Therefore, the keyboard switches are divided into a plurality of blocks and scanned, and if even one switch is turned on, scanning is stopped at that block to detect an on switch. Since a block without an on switch is passed through, it is possible to shorten the time required for one scan to obtain information about an on switch.

Recently, the applicant of the present invention has proposed a key code generation circuit and a key code detection circuit that shorten the scanning time, or a digitally processed electronic musical instrument using these circuits, in accordance with the above-mentioned idea. In such a digitally processed electronic musical instrument, when adding an envelope waveform, an analog or digitally controlled envelope generation circuit is used in conjunction with the key code detection circuit. However, analog control using a CR time constant circuit, etc. has a simpler circuit than digital control, but is inferior in terms of envelope waveform diversity and ease of control. In conventional digital control, an envelope waveform is generated as the key is closed, and when the envelope is added digitally, the quantization of the musical tone signal occurs when the musical tone amplitude is small, such as at the beginning of attack or the end of release. It becomes rough and the smoothness of the attack and release stages is lost. In contrast, it would be better to increase the number of quanta, but in that case, the memory capacity would increase, the number of processing bits would increase, and the configuration would become complicated.

The purpose of the present invention is to attack with a small memory capacity.
To provide an electronic musical instrument that generates an envelope waveform that provides smoothness at the time of release and is equipped with an envelope generation circuit of simple configuration.

In order to achieve the above object, the electronic musical instrument of the present invention has a plurality of sound generation channels smaller than the number of keys, detects key presses and key releases, and assigns them to any of the plurality of sound generation channels. An electronic musical instrument having a key assigner that generates key press and key release signals corresponding to the plurality of sounding channels in a divided manner, the electronic musical instrument having a first and a second input, and a connection between the first input and the second input. subtracting means for taking a difference and outputting a sign bit representing a positive value when the absolute value of the difference and the first input are greater than the second input; attacking the absolute value from the subtracting means with an envelope; Multiplying means for multiplying a speed coefficient value corresponding to one of the speeds of decay and release; and an output signal from the multiplication means based on the sine bit from the subtraction means, and when the sine bit represents a negative value, the multiplication means a complement means for complementing the output signal from the oscillator and outputting it without being complemented when the sign bit represents a positive value;
A plurality of envelope waveforms corresponding to the plurality of sound generation channels are formed by time-division accumulation, and the accumulated value for each sound generation channel is output as the amplitude value of the envelope waveform, and the accumulated value is counter means for supplying to the second input of the subtraction means; storing level data corresponding to the attack level, sustain level and release level of the envelope waveform; envelope level storage means for storing speed coefficient values corresponding to attack, decay, and release speeds in the envelope waveform, and supplying the speed coefficient values to the multiplication means. and maximum value detection means for detecting that the cumulative value from the counter means has reached the maximum value of the envelope; and maximum value detecting means for detecting that the cumulative value from the counter means has reached the minimum value of the envelope, and taking a corresponding action. minimum value detection means for releasing the assignment of a sounding channel to be played, and reading out attack level data corresponding to the envelope attack from the envelope level storage means based on the key press signal from the key assigner, and reading out attack level data corresponding to the envelope attack from the envelope speed coefficient storage means; reads the attack speed coefficient value corresponding to the attack portion of the attack part, reads the sustain level from the envelope level storage means on the condition that the maximum value is detected by the maximum value detection means, and reads the decay speed coefficient value from the envelope speed coefficient storage means. reading means for reading out a numerical value and controlling the release level to be read from the envelope level storage means and the release speed coefficient from the envelope speed coefficient storage means based on the key release signal from the key assigner; Envelopes corresponding to the plurality of sound generation channels are generated by switching the level data and the speed coefficient value according to attack, decay, and release of the envelope based on key press and key release signals supplied in a time-division manner from It is characterized by numerical control.

The present invention will be described in detail below with reference to examples.

First, an outline of an embodiment of a novel electronic musical instrument to which the present invention is applied will be explained, and then details of an envelope generation circuit, which is a main part of the present invention, will be explained.

An electronic musical instrument to which the present invention is applied does not use the conventional method of synthesizing pure sine waves, but uses a method of synthesizing square waves weighted by coefficients, and by combining this with a digital filter with appropriate coefficients. A desired musical tone can be realized with a small number of constituent waveforms.

To outline its principle and structure, if a musical tone is a periodic waveform h(t), it can be expressed by the Fourier series expansion equation h(t) _o=∞ 〓 ⁿ⁼¹ α _o sin n ωt. Here, if we take up to the 30th overtone and sample it every τ time, it is expressed as h(ωτ)= _o=30 〓 ⁿ⁼¹ α _o sin n ωτ. If you want to calculate the waveforms of up to 30 harmonics in time-division in synchronization with the musical tone, and also to produce 8 tones at the same time, a 2KHz musical tone will require at least a 28.8MHz clock. Therefore, by suppressing harmonics in the high frequency range, 7.2MHz
Although it is possible to reduce this to a certain degree, the circuit to achieve this is still complex and it is still difficult to integrate the circuit.

Therefore, although it is basically equivalent to a sine wave synthesis method, we thought of using a square wave synthesis method instead of a pure sine wave and utilizing harmonic distortion. In other words, to create a low-order sine wave, we apply a strong filter to the square wave, and to create a medium-order sine wave, we apply a weak filter to generate harmonic distortion, which creates a high-order sine wave. By supplementing it approximately, we are trying to synthesize it with a square wave with less than 1/2 of the conventional sine wave with up to 30 harmonics.

If the square wave is represented by SQU (NT), then
A ₁ SQU (ωT), A ₂ SQU (ωT), ..., A _N SQU
Generate a weighted waveform (ωT),
If we apply a filter that is stronger as the order is lower for each, the output wave will be F ₁ [A ₁ SQU (ωT)≒k ₁ sin ωT F ₂ [A ₂ SQU (ωT)]≒k ₂₁ sin 2ωT + k ₂₂
The following waveform is extracted: sin6ωT 〓 F _N [A _N SQU(ωT)]≒k _N1 sin NωT +k _N2 sin 3NωT +k _N3 sin 5NωT... For example, if synthesis using square waves up to N=10 is attempted, the waveforms from the 1st to the 10th overtones will be almost completely reproduced. Next, many harmonics are generated due to harmonic distortion, such as 12, 15, 18, ..., 30 harmonics, and the factors that determine the timbre of musical sounds are up to about 10 harmonics. The musical sound waveform can be approximately realized. In other words, whereas conventional sine wave synthesis required synthesis of up to 30 harmonics, it is now sufficient to synthesize up to 1/3 of the 10th harmonic. This requires a clock frequency of about 2.4MHz. It is clear that in order to further reduce this frequency, it is possible to reduce it to 1/2, 1/3, . . . by performing parallel processing.

FIG. 1 is an explanatory diagram showing the configuration of an embodiment of an electronic musical instrument of the present invention based on the above-mentioned principle. In the figure, reference numeral 1 denotes a keyboard, and the key switches with 61-key make contacts are divided into six blocks, each block consisting of 1 octave and 12 keys. i.e. 12
They are arranged in a matrix of rows and six columns. Each key information is scanned block by block by this key code generation circuit 2, and for a block in which a key is turned on, block scanning is temporarily stopped until the key information in that block is sent out. Furthermore, the key information in the block is also sequentially selected and output according to the priority order specified for the keys that are turned on, and the required time slots are limited to the number of turned-on key switches and the number of blocks; for example, when five keys are pressed, If so, one scan time slot is 5+6
= 11 only. This key-on information is output as a binary encoded key code corresponding to each key switch, and is given to the key code data assigner 3 together with a frame signal indicating the end of one scan. The key code data assigner 3 has a maximum simultaneous polyphony of 8 channels, and the key code data 1
It performs high-speed time division operation by dividing the time slot into eight parts. In addition, all control operations of the key code data assigner 3 are performed at the time of the frame signal, and the envelope control signal, that is, the content presence/absence signal BWS,
The release signal RS, high-speed release signal FRS, envelope end signal EES, etc. are sent to the envelope generation circuit 4, and the key code data KCD, which is frequency information, is sent to the envelope generation circuit 4.
are respectively applied to the N-order square wave generating circuit 7.
The envelope generating circuit 4 is composed of a cyclic digital filter, and outputs desired envelope waveform data by controlling an input signal and a filter constant that determines filter characteristics, and inputs the data to a multiplier 9. The square wave generation circuit 7 accumulates the angular velocity information read by the key code KCD, and generates a period T/10 of 1/10 from the square wave signal with the basic period T.
A square wave signal SQU(N) is generated in a time-division manner within one channel time slot. On the other hand, the square wave level memory section 6 that determines the sound is a tablet switch.
The square wave level specified by the drawbar switch 5 is calculated, and the level coefficient value A _N is read out from the square wave level memory section 6 in synchronization with the square wave signal. This level coefficient value A _N is the square wave signal SQU
The N-th square wave A _N SQU (N) which is inverted gated and weighted by (N) is input to the digital filter unit 8 in a time-divisional manner. This digital filter section 8
is composed of a cyclic digital filter, and the filter constant that determines the filter characteristics is read out and controlled by each scale and each order, and the input signal A _N SQU
A filter is applied to each of (N), and _N [A _N
SQU(N)] is output in a time-division manner and input to the multiplier 9. In this multiplier 9, an envelope is added independently to each channel and each order. The output of the multiplier 9 is accumulated for each order in an accumulator ACC10, and further accumulated for each channel, and the waveform h(t) for each sample is input to the D/A converter 11, and the audio system Musical tones are output via 12.

FIG. 2 shows the basic timing waveform of the electronic musical instrument shown in FIG. _φ0 is the master clock, 2.4MHz
It is. _φ101 to _φ110 are time slots for generating square waves, and square wave signals SQU1 to SQU10
It is time-divided into 10 time slots corresponding to 1/2400 ms (millisecond). φ ₂₁ to _{φ 28} are time-divided into eight channels corresponding to the time-division key code data TKCD output from the key code data assigner 3, and one time slot is 1/240 ms. Further, the operating speed of the key code generation circuit 2 is a time slot of 1/30 ms per key time, and all the circuits are time-divisionally operated at this timing.

FIG. 3 shows a clock generation circuit included in the square wave generation circuit 7 of FIG. 1 for generating the basic timing waveform of FIG. Master clock oscillator 7-1
outputs a 2.4MHz clock _φ0 , which is input to the decimal counter 7-2, and the decoder 6-2 outputs timing clocks _φ101 to _φ110 . Next, the output pulse φ ₁ of the counter 7-2 is output from the octal counter 7-3.
The decoder 7-4 outputs timing clocks _φ21 to _φ28 , and the counter 7-3 outputs a pulse _φ2, which is used for each function.

FIG. 4 is a detailed explanatory diagram of an embodiment of a key code data assigner that transmits an envelope waveform control signal, which is related to the main part of the present invention.

In the same figure, the key code data assigner 3 outputs 8 bits to the key code data KCD and frame signal FS sent from the key code generation circuit 2 in FIG. 1 at timings φ ₂₁ and φ ₂₃ as explained in FIG. It operates at twice the speed, and each channel is divided into eight time-division time slots, and outputs time-division key code data TKCD, content presence/absence signal BWS, release signal RS, and high-speed release signal FRS. Furthermore, changes in the output signal occur at the time slots of the frame signal FS.
The key code data KCD transferred from the key code generation circuit 2 is input to the new key code memory 3-1 and the comparison circuit 3-5. In addition, the key code memories 3-4 operate at eight times the speed, and the time-sharing key code data is processed by the clock _φ101 shown in Figure 2.
TKCD is output and input to comparison circuit 3-5. SR flip-flop FF1 has clock _φ101
Set by. Next, the key code data
When KCD and time-division key code data TKCD match, the comparator circuit 3-5 outputs "1" and passes through the AND circuit A31 to the flip-flop circuit at the timing of timing clock _φ101 .
FF1 is reset. If there is no match then
In other words, when new key code data KCD is received, the flip-flop FF is input to the AND circuit A33 at the timing of timing clock _φ109 .
Since the Q output of 1 is “1”, the AND circuit A33
The new key code data is written into the new key code memory 3-1 constituted by a FIFO memory via the OR circuit OR32. This new key code memory 3-1 can also be easily configured with a right/left shift register or a read/write memory RAM. In addition, the output of the OR circuit OR32 is connected to the AND circuits A32 and A so that these operations operate only when the output of the OR circuit OR32, that is, the key code data KCD is received.
33 is input. In this way, new key code data KCD is detected, sequentially written to the new key code memory 3-1, and temporarily stored. When one period of key code data KCD has been output, the frame signal FS becomes "1". This starts writing the new key code data. The OR circuit OR31 detects the presence or absence of key code data and outputs a content presence/absence signal BWS.
The inverted output of this output by the inverter, that is, the signal indicating an empty channel is the AND circuit A3.
4, and when the frame signal FS is "1", the select gate SG3-2 selects the output of the new key code memory 3-1, and the output is applied to the key code memory 3-4 via the gate G3-3. The output of the AND circuit A34 is input to the AND circuit A35, and the new key code memory 3-1 is read out at the timing of clock _φ101 . As a result, the newly keyed-on key code data KCD stored in the new key code memory 3-1 is sequentially written into empty channels of the key code memory 3-4 when the frame signal FS is "1". Further, the output of the comparison circuit 3-5 is inputted to the OR circuit OR3-7 via the AND circuit A31, and sequentially written to the on-shift register 3-12 via the gate G3-8.
This inverted output is input to the AND circuit A37. The content presence/absence signal BWS is also input to the AND circuit A37, and key-off is detected. This AND circuit A37
When the frame signal FS is “1”, the output of is selected by the select gate SG3-10 and the output is selected by the gate G3-11
is written to the off shift register 3-12 via. This output is designated as the release signal RS. Next, the envelope end signal EES sent from the envelope generating circuit 4 in FIG. 1 is sent to the OR circuit OR3-13.
The signal is input to gate G3-14 via. This gate G3-14 opens when the output signal RS of the off-shift register 3-12 is "1" and closes when it is "0".
As a result, when the signal RS is applied, the signal EES is written to the EE shift register 3-15. The output of the EE shift register 3-15 is input to the AND circuit A38 together with the frame signal FS, and the frame signal FS
When is “1”, gate G3-11, gate G3-
3. Input to flip-flop FF2. As a result, each channel is written with "0" and reset.

Next, when new keys are turned on more than the number of empty channels, all the key code data KCD may not be read out from the new key code memory 3-1 and some may remain. When an overflow occurs in this way, the OR circuit OR33 connected to the output of the new key code memory 3-1 outputs "1", and the inverted signal of the frame signal via the inverter is sent to the one-shot multivibrator 3. -6 and an AND circuit A36 to set the flip-flop FF2 and output an overflow signal TS. This signal TS starts the operation of overflow processing.

FIG. 5 is an explanatory diagram of an embodiment of an overflow control circuit that transmits an envelope waveform control signal, which is related to the main part of the present invention.

In the same figure, the envelope data ED is the first
The envelope generating circuit 4 shown in the figure inputs the inverted release signal as a time-division signal to the OR circuit OR34, and when there is no release signal RS, all "1"s are set, and when there is a release signal RS, the envelope data ED is latched. It is input in parallel to the circuit 3-16 and the comparison circuit 3-17. The latch circuit 3-16 writes the eighth time division channel data via the OR circuit OR35 in response to the timing clock _φ28 . Latch circuit 3-1
The output of 6 is input to the comparison circuit 3-17. If the next data is B and the output of the latch circuit 3-16 is A, then when A>B, the comparator circuit 3-17 outputs "1" and writes "1" to the flip-flop DF21 forming the shift register. . Further, the comparison output is input to the AND circuit A40, and the clock _φ101 is applied to the latch circuit 3-16 to rewrite the data from A to B. In this way, smaller envelope data ED are written to the latch circuit 3-16 one after another,
All channels are compared in order. On the other hand, the inverted output of the comparator circuit 3-17 is input to AND circuits A412 to A418 via an inverter _I10 . When "1" is output from the comparison circuit 3-17, "0" is written to flip-flops DF23 to DF28 by AND circuits A412 to A418, and "1" is written only to flip-flop DF21.
is written. The comparison data is sequentially shifted by the clock _φ101 , and the newly outputted comparison data is given priority.

The outputs of the flip-flops DF21 to DF28 are input to a parallel input/serial output type shift register 3-20. This shift register 3-20 is inputted in parallel by clock _φ101 when timing clock _φ28 ,
It is serially outputted by clock _φ101 . This output outputs “1” when the channel is at the minimum level during release, and when the overflow signal TS is received, A
Outputs a high-speed release signal FRS via 39,
Begin a fast release against the envelope.
This forcibly terminates the envelope and creates an empty channel, which quickly rewrites the overflowing key code data with the newly turned on key code data.

FIG. 6 is an explanatory diagram of an embodiment of an envelope generation circuit which is a main part of the present invention.

Envelope generation according to the invention is based on the input signal X _o ,
By numerically controlling the feedback amount of the cyclic digital filter and changing the transfer characteristics, which is expressed by the difference equation where Y _{o =} K (X _o - ₁ - _{Y o} - ₁ ) + Y _o - ₁ when the output signal is Y o The principle is to generate an envelope.

In the circuit of the embodiment shown in FIG. 6, the input signal X _o - ₁ is the output signal Y _o , and when the portion of the output signal Y _o used as envelope data, that is, the upper digit is Y' _o , Y _o = K(X This configuration uses a cyclic digital filter expressed by the difference equation: _o ― ₁ −Y′ _o ― ₁ ) + Y _o ― ₁ .

Input signal X _o - ₁ is ADSR (Attack, Decay,
The constant K is a digital coefficient value read out sequentially from the ADSR level memory 4-2 to control the envelope level according to each state of the envelope (sustain, release), and the constant K is a digital coefficient value read out from the ADSR speed memory 4-2 to control the speed of the envelope. This is a digital coefficient value that is read out sequentially from -3.

Furthermore, the state of ADSR is detected by the ADSR detector 4-1, and the state of ADSR is detected by the ADSR level memory 4-2.
Operates to read ADSR speed memory 4-3. As inputs to the ADSR detector 4-1, there are control signals supplied from the key code data assigner shown in FIG. 4 and the overflow control circuit shown in FIG. This is the most significant bit of the output of the adder 4-4, and is a signal representing the positive or negative sign.
An output signal MAX in which all envelope data are 1, that is, the maximum level is detected, is introduced through an AND circuit A51 of SB and envelope data.
These control signals are stored in an ADSR level memory 4-2 that stores levels corresponding to each state of the ADSR and coefficients of envelope speed.

Simultaneously controls the addresses of ADSR speed memory 4-3 and sets the digital coefficient value X _o - ₁ according to each state.
Output K.

The output X _o - ₁ of the ADSR level memory 4-2 is input to the adder 4-4. The main counter 4-8 is a counter that operates to add up the carry output of the auxiliary counter 4-7. Here, auxiliary counter 4-7
For example, if the main counter 4-8 has 8 channels, an 8-channel accumulator (counter) is configured by a combination of an 8-stage shift register and an adder, and the envelope waveform of each channel is calculated on a time-sharing basis. It works like this.

Here, the auxiliary counter 4-7 is replaced by the main counter 4-8.
The reason why it is provided before is to realize an envelope waveform with a long rise and fall time without increasing the precision of the multiplier (resulting in a large-scale multiplier).

The envelope data Y' _o - ₁ from the main counter 4-8 one count before is added to the adder 4-4 as -Y' _o - ₁ via the inverting circuit 4-9. As a result, the adder 4-4 outputs data X _o - ₁ - Y' _o - ₁ . At this time, the output is the absolute value |X _o ― ₁ ―
It is output as Y' _o - ₁ | and input to the multiplier 4-5. Bit SB indicating the sign is also applied to the complementer 4-6. Next, the multiplier 4-5 multiplies the ADSR speed coefficient K and outputs K|X _o − ₁ − Y′ _o − ₁ |.
The complementer 4-6 outputs K(X _o - ₁ - Y' _o - ₁ ).

This output is input to the auxiliary counter 4-7, and by the next accumulation clock, it is added to the value Y _o - ₁ currently held by the main counter 4-8 and the auxiliary counter 4-7, and after one count, the main counter 4 -8 and auxiliary counter 4-7, Y _o = K (X _o - ₁ - _Y ′ _o - ₁ )
+Y _o - ₁ is output. Furthermore, the output of the auxiliary counter 4-7 is discarded as envelope waveform data, and only the output of the main counter 4-8 is used as envelope data. Signal SB outputs "1" when the envelope is falling. Further, when the envelope reaches the highest level of all "1"s, the signal MAX="1" is outputted from the AND circuit A51.

Also, when the envelope signal becomes all "0", the signal MIN="1" is output from the NOR circuit NOR40, and the AND circuit A along with the release signal RS.
52, and an envelope end signal EES indicating that the envelope has ended is outputted and applied to the key code data assigner of FIG. 4 mentioned above.

Figure 7 shows the ADSR detection circuit 4-1 in Figure 6.
This is a detailed circuit example.

The content presence/absence signal BWS and release signal RS from the key code data assigner shown in FIG. 4 are used as attack A and release R control signals for memory reading via AND circuits A53 and A55, respectively. In addition, the signal SB from the adder 4-4 in Fig. 6 and the main counter 4-
OR circuit output from 8 through AND circuit A51
The Decay (D) control signal for memory reading is output through OR40 and the AND circuit A54, and the high-speed release signal is output from the overflow control circuit in FIG.
FRS is a high-speed release for reading memory as is.
Use as FR control signal. AND circuit A53 has three inputs other than BWS, the output of OR40, RS and FRS are inverted signals, AND circuit A54 has two inputs other than the output of OR40, RS and FRS, are inverted signals, and AND circuit A55 is the other input of RS FRS is used as an inverted signal.

Under these conditions, the output of the ADSR detection circuit 4-1 is input as the address of the ADSR level memory 4-2 and ADSR speed memory 4-3, and the digital coefficient values X _o - ₁ and K are read out and set to predetermined values. be done.

FIG. 8 shows an example of an envelope waveform generated by the envelope generating circuit of FIG. 6.

In FIG. 5A, attack A is started at a predetermined speed _A0 to the highest level (all "1" in this case) in response to the BWS signal indicating that sound is being generated.
Next, when the highest level is reached, the output of the AND circuit A51 becomes "1" and Decay D starts at Decay speed _D0 . The output of the AND circuit A51 becomes "0" immediately, but at this time the SB signal becomes "1" and the decay continues. Decay continues up to sustain level S.

Next time the key is turned off, the RS signal is output,
Release R is started at release speed _R0 .
When the release is finished (all “0” in this case),
An EES signal indicating the end of envelope generation is output, completing the envelope. In this way,
ADSR waveform is generated. Figure b shows the AR waveform of attack A at a predetermined speed, reaching the maximum value of all "1" and releasing R after a predetermined time, and figure c shows the decay D at the set level before attack A reaches the maximum value at a predetermined speed. This is an AD waveform that is decayed at a predetermined speed. ADSR like this
Various envelopes can be easily generated by reading the address and setting a predetermined level and speed. That is, it forms an envelope waveform consisting of a combination of curves for a combination of rectangular waveforms consisting of input signals A ₀ , D ₀ , S ₀ , and R ₀ , and has so-called filter characteristics.

As explained above, according to the present invention, the envelope waveform is
It is equipped with an envelope level storage device that sequentially controls the waveform level according to ADSR, and an envelope speed storage device that stores filter constants and sequentially controls the envelope speed according to ADSR. A desired envelope waveform can be generated by controlling the transfer characteristics of the digital filter. In this way, it is more versatile than the conventional analog envelope waveform generation method, and has less memory capacity than the digital envelope waveform generation method, simplifying the configuration and making control easier. It is something.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration explanatory diagram of an embodiment of the electronic musical instrument of the present invention, FIGS. 2 and 3 are basic timing waveforms and their generation circuits used in the electronic musical instrument of FIG.
5 is a detailed illustration of an embodiment of a key code data assigner and an overflow control circuit that send out an envelope waveform control signal, and FIG. 6 is a detailed implementation of an envelope generation circuit, which is the main part of the present invention. FIG. 7 is a circuit diagram of the main part of the embodiment shown in FIG. 6, and FIG. 8 is an explanatory diagram showing the effect of the embodiment shown in FIG. ), 2 is a key code generation circuit, 3 is a key code data assigner, 3-1 is a new key code memory, 3-4 is a key code memory, 3-
5 is a comparison circuit, 3-16 is a latch circuit, 3-17
is a comparison circuit, 3-20 is a shift register, 4 is an envelope generation circuit, 4-1 is an ADSR detector, 4
-2 is ADSR level memory, 4-3 is ADSR speed memory, 4-4 is adder, 4-5 is multiplier,
4-6 is a complementer, 4-7 is an auxiliary counter, 4-8
is a main counter, 4-9 is an inverting circuit, 5 is a tablet drawbar switch, 6 is a square wave level memory section, 7 is a square wave generation circuit, 8 is a digital filter section, 9 is a multiplier, 10 is an accumulator, 11 is D/A
A transducer, 12, indicates an acoustic system.

Claims (1)

[Scope of Claims] 1. It has a plurality of sound generation channels smaller than the number of keys, detects key presses and key releases, and assigns them to any of the plurality of sound generation channels, and time-divisionally assigns the plurality of sound generation channels. An electronic musical instrument having a key assigner that generates key press and key release signals corresponding to a channel has first and second inputs, calculates the difference between the first input and the second input, and calculates the difference between the first input and the second input. subtraction means for outputting an absolute value and a sign bit representing a positive value when the first input is greater than the second input; 4-9;