JPH0135542B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention utilizes the MH code (Modified Huffman code) defined as an international standard for high-speed facsimile.
Code) and/or MR code (Modified READ
This invention relates to a circuit that performs encoding and decoding. [Background of the Invention] Conventional encoding/decoding circuits input and output codes to and from external circuits in serial or parallel fashion. Also, when inputting and outputting codes to and from an external circuit in parallel, parallel-to-serial conversion and serial-to-parallel conversion were required. In other words, one word of the Encoding Table ROM used for encoding and decoding is 8.
It consists of bits or 16 bits, and the code is output in parallel. However, the length of the code word is variable from 2 to 12 bits in the case of the MH code. Therefore, only part of the parallel output of the Encoding Table ROM is valid. On the other hand, when performing parallel output to an external circuit, all outputs need to be valid as codes. Therefore, it is usually necessary to perform a conversion process to collect only valid bits from the parallel output of the Encoding Table ROM and output only the code in parallel to an external circuit. This conversion is typically
This can be achieved by latching the parallel output of the Encoding Table ROM, serially converting it, and then converting this serially converted code back to a parallel code. This is done using That is,
Only the valid bits of the parallel output of the Encoding Table ROM are taken out by the parallel-in/serial-out register, and the taken-out valid bits are converted into, for example, 8-bit words by the serial-in/parallel-out register. The encoding/decoding circuit according to the prior art operates as described above, but performs serial-to-parallel conversion of codes and ends encoding at the time of encoding, that is,
Of the parallel outputs of the Encoding Table ROM,
It is not possible to simultaneously detect that all bits that are valid as a code word have been taken out, and the operation of performing parallel-to-serial conversion of the code during decoding and the operation of decoding the code by performing parallel-to-serial conversion of the code, and the EOL is a code word that indicates the code break for a line.
There was a problem in that it was not possible to simultaneously detect (End of Line) and was not suitable for high-speed processing. [Object of the Invention] An object of the present invention is to provide a small-scale encoding/decoding circuit that can encode and decode MH codes and/or MR codes at high speed. [Summary of the Invention] In order to output codes in parallel during encoding, the present invention requires a parallel-in-serial-out register that latches the parallel output of a memory that stores an encoding table and converts it into serial data, and a parallel-in-serial out register that Focusing on the need for a serial-in-parallel out shift register that inputs the serial output of the out register and converts it back into parallel, we encoded it by making the parallel-in serial out shift register a parallel-in parallel out shift register. The end detection circuit has been miniaturized, and serial-to-parallel conversion and encoding end detection can be performed simultaneously. Also, during decoding, the code input in parallel is converted to serial, and the serial code is used as part of the address of the memory that stores the decoding information.The serial output of the parallel-in serial-out shift register is input, and the The feature is that the EOL can be detected at the same time as the memory address is created by converting it to . This type of encoding/decoding circuit is small and does not have a timing generation circuit such as a counter.
Suitable for LSI (Large Scale Integration). [Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an encoding/decoding circuit 20 of the present invention.
00 and the controller 1 that controls it
This shows the relationship with 000. The encoding/decoding circuit 2000 will be explained in detail using FIG. 2 and subsequent figures. The controller 1000 is configured using, for example, a microcomputer, and its operation will be explained using the flowcharts of FIGS. 3 and 4. FIG. 2 is a detailed block diagram of an encoding/decoding circuit 2000 according to an embodiment of the present invention. The MH code used by one embodiment of the present invention is the same as the commonly used MH code, and encodes run lengths from 0 to 63.
Run lengths are encoded by combining two types of codes: Terminating Code and Make Up Code, which encodes runs in 64 increments. For example, an MH code with run length = 65 has run length = 64 + 1, and 64 is Make
Terminating 1 after encoding with Up Code
The code that can be obtained by encoding with Code and represents one run length is always Terminating
End with Code. In addition, if the run length is 63 or less,
Encoded only by Terminating Code. This MH code is a variable length code with a maximum code length of 12 bits and is stored in the Encoding Table ROM, but it is used to indicate the valid bits as a code word among the fixed length read parallel output of the ROM. The code has a code format in which the bit following the valid bit in the code is set to "1", and all subsequent bits are set to "0". This code "100...0" is used to detect that all bits valid as a code word have been extracted from the parallel output of the Encoding Table ROM, that is, to detect the end of encoding (also referred to as termination detection). In one embodiment of the present invention shown in FIG.
In the Encoding Table ROM (hereinafter referred to as table ROM) 2040, one word consists of 8 bits, of which at least 1 bit is used for detecting the end of encoding as described above, so one word can contain up to 7 bits. Only code strings can be stored. On the other hand, as mentioned above, MH codes have codewords of up to 12 bits, so the table
In the ROM 2040, one MH code is divided into a first half and a second half, and stored using two words. Table 1 shows the relationship between the address generated by the encoding address generation circuit 2010 and the content of the data stored at that address in the table ROM 2040.
It is indicated as a note whether it is the first half or the second half of the code. Similarly, Table 2 also shows the decoding address generation circuit 2
Address where 020 occurs and table ROM2
The relationship with the contents of data stored at that address in 040 will be explained. Next, the meaning of the signals transmitted and received between the encoding/decoding circuit according to the embodiment of the present invention shown in FIG. 2 and the controller 1000 shown in FIG. 1 will be explained. c...A signal given to the decoding address generation circuit 2020 during decoding, and indicates the type of received code, i.e., white MH code, black MH code,
This is a signal that specifies one of the MR codes. The order in which the types of codes are received is uniquely determined by the encoding system of the MH code and the MR code, and the controller 1000 receives the signal c according to this encoding system.
Output. As a result, decoded address generation circuit 2020 outputs one of three types of addresses based on Table 2. d...A binary number indicating the consecutive number of white or black pixels measured by the controller 1000, that is, the run length, and is given to the encoding address generation circuit 2010 at the time of encoding. e...This is a signal given to the encoding address generation circuit 2010 during encoding, and is a signal indicating the type of code. For MH code, white Make Up
Code, Terminating Code in white, Make Up in black
There are four types: Code, and black Terminating Code. f...This is a signal for selecting whether the encoding/decoding circuit shown in FIG. 2 is used as an encoding circuit or a decoding circuit. When used as an encoding circuit, the MPX 2030 provides the encoding address g from the encoding address generation circuit 2010 to the table ROM 2040. k... is a shift pulse signal to the parallel-in/parallel-out shift register 2050. l...The output j of the table ROM is the signal latched in the parallel in/parallel out register 2050. The controller 1000 takes in this signal l during decoding, and uses it to determine whether decoding of a code word has ended or not, and to obtain a decoded result (for example, run length). n... All valid bits of the parallel output j of the table ROM are shifted out,
This is a signal indicating whether or not it has been output to the S/P 2080, and the controller 1000 can know from this signal n that the output of valid code word bits to the S/P 2080 has ended. o...This is a signal for selecting whether the encoding/decoding circuit shown in FIG. 2 is used as an encoding circuit or a decoding circuit. When used as a decoding circuit, MPX 2070 uses the most significant bit m of parallel-in/parallel-out shift register 2050 as input q to S/P 2080. p...This is a shift pulse signal to the S/P2080. At the time of encoding, it is given as a pair with signal k,
Only the valid sign bits of the parallel output from the table ROM are used to align into the S/P 2080. In addition, at the time of decoding, the code v is given as a pair with the signal t, and the code v is aligned in parallel, and the signal for detecting the EOL code is sent to the S/P2.
Used to generate within 080. r... is an 8-bit parallel-aligned code obtained during encoding. s...A signal indicating whether an EOL code is detected or not. The controller can know the detection of the EOL code at the time of decoding from this signal s. t... is a shift pulse signal to the P/S 2100. u...8 given from the controller 1000
This is the received bit code.

【table】

Claims (1)

[Claims] 1. Having a memory storing an encoding table and a decoding table of MH code and/or MR code,
By inputting the change point information of the image signal and accessing the memory, the MH code and/or MR
In an encoding/decoding circuit that inputs an MH code and/or an MR code and decodes it into change point information of an image signal by accessing the memory, the parallel output of the memory is used during encoding. A parallel-in parallel-out shift register that latches and shifts the parallel-in parallel-out shift register, and the first bit of the parallel output signal that is output to the output terminal every time the parallel-in parallel out shift register is shifted is sequentially taken in and serial-parallel converted to become an encoded signal. a serial-in-parallel out shift register; a termination detection circuit that receives the parallel output signal of the parallel-in-parallel out shift register and detects the end of encoding for each shift; and a termination detection circuit that shifts the code input in parallel at the time of decoding to the memory. a parallel-in serial-out shift register that serially outputs the address modification signal of the memory, a parallel-in parallel-out shift register that latches the parallel output of the memory and outputs it as a decoded signal, and outputs the memory address as the memory address; a circuit that generates the memory access address based on the serial output of the in-serial out shift register and the output of the parallel in-parallel out shift register; and a serial in parallel circuit that receives the serial output of the parallel in serial out shift register and converts it into parallel. An encoding/decoding device comprising an out shift register and an EOL detection circuit that receives the parallel output of the serial-in-parallel out shift register and detects EOL every time the parallel-in serial out shift register shifts. circuit. 2 In claim 1, a parallel-in-parallel-out register that latches the memory output during decoding is also used as a parallel-in-parallel-out shift register that latches the memory output during encoding, and the encoded signal is A single register is used as a serial-in-parallel-out shift register to obtain the output of the serial-in-parallel-out shift register and a serial-in-parallel-out shift register to convert the output of the parallel-in serial out shift register into parallel during decoding.
An encoding/decoding circuit characterized in that an input selection circuit is connected to the input circuit of this serial-in-parallel out shift register.