JPH0136139B2 - - Google Patents

Info

Publication number
JPH0136139B2
JPH0136139B2 JP56098798A JP9879881A JPH0136139B2 JP H0136139 B2 JPH0136139 B2 JP H0136139B2 JP 56098798 A JP56098798 A JP 56098798A JP 9879881 A JP9879881 A JP 9879881A JP H0136139 B2 JPH0136139 B2 JP H0136139B2
Authority
JP
Japan
Prior art keywords
transfer
arithmetic processing
packet
data
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56098798A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57212565A (en
Inventor
Masato Amamya
Tadashi Naruse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56098798A priority Critical patent/JPS57212565A/ja
Publication of JPS57212565A publication Critical patent/JPS57212565A/ja
Publication of JPH0136139B2 publication Critical patent/JPH0136139B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
JP56098798A 1981-06-25 1981-06-25 Data transferring device Granted JPS57212565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56098798A JPS57212565A (en) 1981-06-25 1981-06-25 Data transferring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56098798A JPS57212565A (en) 1981-06-25 1981-06-25 Data transferring device

Publications (2)

Publication Number Publication Date
JPS57212565A JPS57212565A (en) 1982-12-27
JPH0136139B2 true JPH0136139B2 (fr) 1989-07-28

Family

ID=14229368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56098798A Granted JPS57212565A (en) 1981-06-25 1981-06-25 Data transferring device

Country Status (1)

Country Link
JP (1) JPS57212565A (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661079B2 (ja) * 1984-12-27 1994-08-10 株式会社東芝 デ−タ処理装置
JPS6293743A (ja) * 1985-10-21 1987-04-30 Agency Of Ind Science & Technol 並列計算機システム

Also Published As

Publication number Publication date
JPS57212565A (en) 1982-12-27

Similar Documents

Publication Publication Date Title
US5175733A (en) Adaptive message routing for multi-dimensional networks
US4933933A (en) Torus routing chip
KR102803151B1 (ko) 시스템 온 칩의 인터커넥트 패브릭 내에서 소스 기반 라우팅을 구현하기 위한 절차
US4833468A (en) Layered network
EP0197103B1 (fr) Equilibrage de la charge pour noeuds de commutation par paquets
US5878227A (en) System for performing deadlock free message transfer in cyclic multi-hop digital computer network using a number of buffers based on predetermined diameter
JP2817770B2 (ja) パケットの経路指定デッドロック回避方法及び装置
US5675736A (en) Multi-node network with internode switching performed within processor nodes, each node separately processing data and control messages
US5502816A (en) Method of routing a request for a virtual circuit based on information from concurrent requests
KR100259276B1 (ko) 대역폭확장이 가능한 상호연결망
JPH08185380A (ja) 並列計算機
US4984237A (en) Multistage network with distributed pipelined control
US6065063A (en) Deadlock avoidance method in a computer network
CN111901257B (zh) 一种交换机、报文转发方法及电子设备
US6263415B1 (en) Backup redundant routing system crossbar switch architecture for multi-processor system interconnection networks
US6597692B1 (en) Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networks
EP0244443A1 (fr) Reseau de communications pour communications par paquets entre multiprocesseurs
US5825773A (en) Switching system for transferring broadcast packet held in broadcast buffer received from input port to output ports according to the state of each output port
CA2117506C (fr) Mecanisme d'addition d'adresses de retour pour systeme de traitement parallele
JPH0136139B2 (fr)
US5553078A (en) Communication control system between parallel computers
JPH06266684A (ja) プロセッサ間ルーティング方式
US8224987B2 (en) System and method for a hierarchical interconnect network
US6055607A (en) Interface queue with bypassing capability for main storage unit
JPS63257052A (ja) マルチプロセツサシステム