JPH0136342Y2 - - Google Patents
Info
- Publication number
- JPH0136342Y2 JPH0136342Y2 JP18591983U JP18591983U JPH0136342Y2 JP H0136342 Y2 JPH0136342 Y2 JP H0136342Y2 JP 18591983 U JP18591983 U JP 18591983U JP 18591983 U JP18591983 U JP 18591983U JP H0136342 Y2 JPH0136342 Y2 JP H0136342Y2
- Authority
- JP
- Japan
- Prior art keywords
- switch
- muting
- output terminal
- amplifier
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
【考案の詳細な説明】
本考案はオーデイオ増幅器の出力ミユーテイン
グ回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output muting circuit for an audio amplifier.
従来プリアンプのミユーテイングには増幅器と
出力端子間にリレー等のミユーテイングスイツチ
を直列に設置する直列型か、出力端子と接地間に
スイツチングトランジスタを並列に接続して出力
端子を接地しミユーテイング動作を行わせる並列
型が一般的であつた。 Conventionally, preamplifier muting has been done either in series, in which a relay or other muting switch is installed in series between the amplifier and the output terminal, or in parallel, a switching transistor is connected between the output terminal and ground, and the output terminal is grounded to perform the muting operation. The most common type was the parallel type.
しかしながら上述の直列型は増幅器の出力が完
全に安定しないうちにミユーテイングスイツチが
閉じてしまうとその時点でのDC変動等が電力増
幅器によつて増幅されてしまい不要なノイズが発
生することになる。この為充分なるミユーテイン
グ時間が必要となり、ミユーテイング時間が長く
なる欠点がある。又、ミユーテイング時間中は電
力増幅器の入力端子は開放状態となり、外部より
の誘導ノイズを受け易い不都合が生じる。 However, in the series type mentioned above, if the muting switch is closed before the output of the amplifier is completely stabilized, the DC fluctuations at that point will be amplified by the power amplifier, causing unnecessary noise. . For this reason, a sufficient mutating time is required, and there is a drawback that the mutating time becomes long. Furthermore, during the muting time, the input terminal of the power amplifier is in an open state, resulting in the inconvenience that it is susceptible to induced noise from the outside.
又、スイツチングトランジスタを用いた並列型
のミユーテイング回路では充分な減衰量が得られ
ない欠点がある。 Furthermore, a parallel type muting circuit using switching transistors has the disadvantage that sufficient attenuation cannot be obtained.
本考案の目的は、このような従来方法を改良す
ることにある。 The purpose of the present invention is to improve such conventional methods.
以下本考案を図面に従つて詳細な説明を行う。 The present invention will be described in detail below with reference to the drawings.
図においてプリアンプ１と出力端子２の間にミ
ユーテイングスイツチ３と抵抗５を直列接続し、
スイツチングトランジスタ６を出力端子２と接
地間に接続する。スイツチングトランジスタ６に
は時定数として抵抗１７及びコンデンサ１８がベ
ース側に接続されている。一点鎖線内の制御回路
４は、ミユーテイングスイツチ３と、スイツチン
グトランジスタ６を駆動する為の回路である。図
示せぬ電源スイツチの投入と連動してスイツチ７
を開放にすると、抵抗８及びコンデンサー９によ
る時定数により電源投入より数秒間遅れてトラン
ジスタ１０はONしミユーテイングスイツチ３を
ONさせる。この間トランジスタ６はオンのまま
である。つぎにトランジスタ１０はONしトラン
ジスタ１３はOFFし、トランジスタ１５はOFF
する。この結果トランジスタ６のベースへは電圧
は供給されなくなる為放電時定数によりトランジ
スタ６はON→OFFに変化する。この場合トラン
ジスタ６のON抵抗はコンデンサ１８の放電に従
つてゆるやかに変化する。 In the figure, a muting switch 3 and a resistor 5 are connected in series between the preamplifier 1 and the output terminal 2, and a switching transistor 6 is connected between the output terminal 2 and ground. A resistor 17 and a capacitor 18 are connected to the base side of the switching transistor 6 as time constants. A control circuit 4 within the dashed line is a circuit for driving the muting switch 3 and the switching transistor 6. In conjunction with turning on a power switch (not shown), switch 7
When the switch is opened, the transistor 10 turns on several seconds after the power is turned on due to the time constant of the resistor 8 and the capacitor 9, and the muting switch 3 is turned on.
Turn it on. During this time, transistor 6 remains on. Next, transistor 10 is turned on, transistor 13 is turned off, and transistor 15 is turned off.
do. As a result, no voltage is supplied to the base of the transistor 6, so the transistor 6 changes from ON to OFF due to the discharge time constant. In this case, the ON resistance of the transistor 6 changes slowly as the capacitor 18 discharges.
この様にミユーテイング時間中は出力端子がス
イツチングトランジスタ６により短絡される為に
電力増幅器４は不要な外部よりの誘導ノイズの影
響を防止出来る。又、ミユーテイングスイツチ３
の開放時間を短かくした場合、従来と同様にミユ
ーテイングスイツチ３がON時に出力側に増幅器
１のDCオフセツトのズレ等の直流変動によるノ
イズが伝達されるが、スイツチングトランジスタ
６が時定数をもつてゆつくりとOFFする為に上
記ノイズは低周波成分だけとなり聴感上ほとんど
問題がないノイズとなる。従つてミユーテイング
時間を従来より短縮出来る。 Since the output terminal is thus short-circuited by the switching transistor 6 during the muting time, the power amplifier 4 can be prevented from being affected by unnecessary external induced noise. Also, mutating switch 3
When the open time of the switching transistor 6 is shortened, noise due to DC fluctuations such as the deviation of the DC offset of the amplifier 1 is transmitted to the output side when the muting switch 3 is turned on, as in the conventional case. Since it turns off gradually, the above noise consists of only low frequency components, and is a noise that poses almost no problem to the audible sense. Therefore, the muting time can be shortened compared to the conventional method.
以上の様に本考案によると直列型のミユーテイ
ングスイツチによるミユーテイングが解除になつ
た直後に並列型のミユーテイングスイツチがゆつ
くりと開放になるので、ミユーテイング時間を短
縮しても出力端子には主として低周波成分ノイズ
だけとなり、聴感上問題が少いという優れた効果
を得ることが出来る。 As described above, according to the present invention, the parallel type muting switch is opened slowly immediately after the series type muting switch is released, so even if the muting time is shortened, the output terminal mainly It is possible to obtain an excellent effect in that there is only low frequency component noise and there are few problems in terms of hearing.
図は本考案の一実施例を示す回路図である。
１……増幅器、３……スイツチ、４……制御回
路。
The figure is a circuit diagram showing an embodiment of the present invention. 1...Amplifier, 3...Switch, 4...Control circuit.
Claims (1)
入直後はオフ状態である第１のスイツチと、上記
出力端子と接地間に並列接続され電源投入直後は
オン状態である第２のスイツチと、電源投入直後
の所定時間後に上記第１のスイツチをオン状態に
する手段と、上記所定時間後より上記第２のスイ
ツチを徐々にオフ状態にする時定数回路とからな
る増幅器のミユーテイング回路。 a first switch connected in series between the amplifier and the output terminal and in an off state immediately after power is turned on; a second switch connected in parallel between the output terminal and ground and in an on state immediately after power is turned on; A muting circuit for an amplifier, comprising means for turning on the first switch after a predetermined time immediately after turning on the switch, and a time constant circuit for gradually turning off the second switch after the predetermined time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18591983U JPS6093319U (en) | 1983-12-01 | 1983-12-01 | Amplifier muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18591983U JPS6093319U (en) | 1983-12-01 | 1983-12-01 | Amplifier muting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6093319U JPS6093319U (en) | 1985-06-26 |
| JPH0136342Y2 true JPH0136342Y2 (en) | 1989-11-06 |
Family
ID=30401719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18591983U Granted JPS6093319U (en) | 1983-12-01 | 1983-12-01 | Amplifier muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6093319U (en) |
-
1983
- 1983-12-01 JP JP18591983U patent/JPS6093319U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6093319U (en) | 1985-06-26 |
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