JPH0136711B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with a gate control pole, and more particularly to a gate turn-off thyristor.

A gate turn-off thyristor (hereinafter referred to as GTO) consists of four layers and three junctions of PNPN, and changes from a blocking state to a conductive state by applying a positive signal to the gate electrode placed around the cathode layer, and then turns into a conductive state by a negative signal. It is a static switch that turns off when the switch is turned off.

The characteristics required of a GTO are (1) to be able to turn on and off with a small signal gate current, (2) to have a fast turn-on time and a large load current rise (di/dt) when turned on with a small signal. (3) A large load current can be turned off in a short time using a small signal gate reverse current.

Turning the GTO on and turning it off are completely contradictory matters, and how to achieve this coordination is an important design issue.

Figure 1 is a plan view showing an example of a general GTO.
FIG. 2 is a sectional view taken along the line -.

In FIG. 1 and FIG. 2, 1 is P ₁ layer 2,
The wafer consists of an N ₁ layer 3, a P ₂ layer 4 and an N ₂ layer 5. 6 is a gate layer buried in the P ₂ layer, which is a high impurity concentration P ₂ ⁺⁺ layer. 7 forms an anode electrode A with a metal layer provided on the _P1 layer. 8
is a metal layer provided on the N ₂ layer 5 and forms a cathode electrode K. Reference numeral 9 denotes a metal layer provided on the surface of the _P2 layer 4, which forms the first gate electrode (on-gate electrode) _G1 . 10 is a metal layer similarly provided on the surface of the P ₂ layer 4 and forms a second gate electrode (off-gate electrode) G ₂ .

In the GTO shown in Figures 1 and 2,
High concentration impurity layer in _P2 layer 4 as gate electrode
A P ₂ ⁻ layer is formed in which P 2 ++ is embedded and has a high resistance on the P ₂ layer side in contact with the N ₂ layer 5, thereby increasing the reverse breakdown voltage V _GK between _the gate ^and cathode.

In the conventional GTO, the surface concentration distribution of each part was set as shown in Figure 3. In Figure 3,
The horizontal axis D indicates the thickness direction of the GTO, and the vertical axis C indicates the impurity concentration. According to experiments, it has been found that the concentration Cp ₂ of the P ₂ layer 4 in the region narrowed by the P ₂ ⁺⁺ layer greatly influences the operating characteristics. Figure 4 shows the concentration Cp ₂ of P ₂ layer 4.
These are the results of an experiment in which the turn-off time t _ON and turn-off time t _OFF were measured by changing only t ON and t OFF. Fourth
As is clear from the figure, increasing Cp ₂ makes it easier to turn off, but it has the disadvantage that it is difficult to turn on.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to make the concentration of the cathode region opposite to the cathode region near the gate electrode smaller than that of other regions, so that a conductive region is formed from this region at turn-on. It is an object of the present invention to provide a high-performance gate turn-off thyristor in which turn-on characteristics and turn-off characteristics can be coordinated by widening the gate turn-off thyristor.

A gate turn-off thyristor according to an embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 5 to 8.

The GTO according to this embodiment is shown in Figures 5 and 6.
As shown in the figure, a rectangular parallelepiped-shaped wafer 1 is composed of a P ₁ layer 2 , an N ₁ layer 3 , a P ₂ layer 4 , and an N ₂ layer 5 . The metal layer 7 provided on the exposed surface of the P ₁ layer 2 forms an anode electrode A, and the metal layer 8 provided on the N ₂ layer 5 forms a cathode electrode K.
A comb-shaped high concentration impurity P ₂ ⁺⁺ layer 6 is buried in the P ₂ layer 4, and the P ₂ ⁺⁺ layer 6 has a bridge portion 6a and a large number of strips 6b extending from the bridge portion 6a. have P ₂ located at the top near the tip of the strip 6b
A metal layer 9 is provided on the surface of the layer 4, and the metal layer 9 and the P ₂ ⁺⁺ layer 6 constitute a first gate electrode portion (on-gate electrode) G ₁ . Also
_P2 ^{layer 4 located above the bridge portion 6a of P2++} _layer 6
A metal layer 10 is disposed on the surface of the gate electrode, and the metal layer 10 and the P ₂ ⁺⁺ layer 6 constitute a second gate electrode portion (off-gate electrode) G ₂ .

The feature of the GTO according to the present invention is that the cathode region close to the P ₂ ⁺⁺ layer 6 (gate layer) has an impurity concentration that is lower than the impurity concentration of the P ₂ ⁺⁺ layer 6 and higher than the impurity concentration of the P ₂ layer 4. intermediate impurity layer 1 having
1 is provided in the P ₂ layer 4, and the conduction region at turn-on is expanded from a portion of the P ₂ layer 4 close to the gate layer.

Figure 7 specifically shows the actual manufacturing method of the GTO with the above structure.
The manufacturing method of the GTO according to the present application will be described based on the figures.

In this embodiment, for example, we are trying to obtain a GTO with a withstand voltage of 1200V and a turn-off current of 1000A, and first, as shown in Figure 7A, the specific resistance is 50
A single-side mirror-polished N-type silicon substrate with a thickness of 300 μm is prepared, and gallium is diffused from both sides of the substrate _N1 using the generally well-known closed tube method to form the P shown in Figure 7A. ₁ and _P2 layers are formed respectively. In this case, the diffusion state is such that the surface concentration is 5
×10 ¹⁷ atoms/cm ³ with a diffusion depth of 30 μm. The concentration profile in this state is the surface concentration in Figure 8.
Cp ₁ and Cp ₂ , which form P ₁ , N ₁ and P ₂ layers. Subsequently, an oxide film is formed on the entire surface, and windows are opened in the oxide film to form a high impurity concentration layer in a predetermined pattern. After forming an oxide film for selective diffusion using a predetermined method, as shown in FIG _{. 7B} , a surface concentration of 8×
Diffuse boron to 3 μm at 10 ¹⁷ atoms/cm ³ . At this time, boron is simultaneously diffused onto the back surface of the wafer 1 at a surface concentration of 8×10 ¹⁷ and a depth of 3 μm. Next, in order to form a low-resistance gate layer (Fig. 6), an oxide film is again formed on the entire surface, and as shown in Fig. 7c, it is narrowed by the boron diffusion layer performed in Fig. 7B. After opening a window in the oxide film at the location where the
A high concentration layer 6 is formed by selectively diffusing ×10 ²⁰ atoms/cm ³ to a depth of 7 μm. Under this diffusion condition, it spread first
The diffusion layer for Cp' ₂ and Cp' ₁ has a depth of 10 μm and a surface concentration of 5×10 ¹⁷ atoms/cm ³ as shown in Figure 7c.
It is pushed into and spread out. Subsequently, as shown in FIG. 7D, a P-type single crystal layer 14 with an impurity concentration of 5×10 ¹⁵ atoms/cm ³ is epitaxially grown on the entire surface to a depth of 25 μm, and then as shown in FIG. Cathode shown in
N 2x on the epitaxial layer with a 2 _- layer pattern
Selectively diffuse phosphorus to 10μm at a concentration of 10 to ²⁰ atoms/ ^cm3 .
Form _N2 layer 5. After this, the GTO is configured by performing lifetime control as necessary and bonding the electrodes. In this example, after performing gold diffusion treatment at 840°C for 30 minutes from the surface side of the _P1 layer, the main cathode electrode (not shown in Figure 5) and the off-gate electrode were formed in accordance with the surface pattern shown in Figure 5. 10. An anode electrode is connected to the on-gate electrode 9 and the surface of the _P1 layer using aluminum by a commonly practiced vapor deposition method or alloy method.

According to the GTO shown in Figures 5 and 6,
When a gate current is passed from the on-gate electrode G ₁ to the cathode N ₂ layer 5, this GTO changes from a blocking state to a conducting state. At this time, the on region of the cathode _N2 layer 5 is divided between the strip 6b of the gate layer 6 and the intermediate impurity layer 1.
Cathode _N2 layer 5 facing the _P2 area narrowed to 1
A portion 17 close to the on-gate electrode G ₁ 9 of 1 is turned on first, and then the on region expands in the direction shown by the long arrow 16a, as shown in FIG. In this process, as shown by a partially short arrow 16b, the on region also spreads to the intermediate impurity concentration layer 11, resulting in the cathode in the region surrounded by the strips 6b of the gate layer 6.
The entire _N2 layer 5 becomes conductive.

Therefore, in the GTO of this embodiment, the speed of expansion in the direction of the arrow 16a is high and it spreads from this region to the entire area, so that the initial conduction area becomes large. As a result, the turn-on time t _ON is short, and
Di/dt tolerance increases. In addition, in this example
In the GTO, by providing a portion with an impurity concentration of Cp ₂ and a portion with an impurity concentration of Cp ₂ ' in the narrowed part of the gate layer 6, _the gate firing current can be reduced by approximately It can be reduced by 30% (compared to the conventional example).
0.2~0.4A for 0.3~0.6A) Turn-on time t _ON
is reduced to approximately 50% (from 4 to 5 μs to 2 to 3 μs), and di/dt tolerance of 100 to 200 A/μs is reduced to 300 to 200 A/μs.
It was improved by more than 300% to 500A/μs.

In the turn-off process, from the cathode _N2 layer 5 to the off-gate electrode _G2 provided on the gate layer 6
Apply an off-gate signal so that the N ₂ P ₂ ^-junction is reverse biased. At this time, the conduction region becomes blocked from a place close to the gate layer 6, and the current is finally cut off at the intermediate impurity layer 11, which is easy to turn off.
GTO is completely blocked.

In this case, when characteristics were compared with and without a layer with an impurity concentration of Cp ₂ , the turn-off current slightly increased with the Cp ₂ layer under the same conditions, and the turn-off time was almost unchanged. This is because the conduction region has a good spread, and therefore the current density at the time of turn-off can be made small. In this way, the turn-on performance, which was a problem with conventional GTOs, has been significantly improved, and as a result, it has become possible to apply GTOs to equipment operating at high frequencies.

In the above embodiment, a buried gate structure was described, but the gate electrode was connected to the cathode N ₂
It can also be applied to GTOs arranged side by side on the surfaces of layer 5 and _P2 layer 4. Further, since the gate electrode is used in common for on and off, the same functions and effects as those described above can be obtained.

Furthermore, the present invention can also be applied to a semiconductor device consisting of N ₁ , P ₁ , N ₂ , and P ₂ layers.

In the above-mentioned embodiment, an example of the impurity concentration in each part was explained, but the impurity concentration range shown in FIG. 4 may be used.

As explained above, the present invention provides P ₁ , N ₁ , P ₂ ,
It consists of four layers of N ₂ and is constructed so that the impurity concentration in the thickness direction of the P ₂ layer is the highest in the intermediate region.The impurity concentration of the P ₂ layer in the cathode region near the gate electrode Since the concentration is lower than that in the region facing the layer, it is possible to obtain a gate turn-off thyristor with excellent turn-on characteristics, turn-off characteristics, and di/dt tolerance.

[Brief explanation of drawings]

Fig. 1 is a plan view of a general gate turn-off thyristor, Fig. 2 is a sectional view taken along the line - - of Fig. 1, and Fig. 3 is a plan view of a general gate turn-off thyristor.
The figure is an impurity concentration distribution diagram in the thickness direction of a conventional gate turn-off thyristor, Figure 4 is a characteristic diagram showing turn-on time characteristics and turn-off time characteristics, and Figure 5 is a main part of a gate turn-off thyristor according to an embodiment of the present invention. 6 is a sectional view thereof, FIGS. 7A to 7D are manufacturing process diagrams of the gate turn-off thyristor shown in FIGS. 5 and 6, and FIG.
The figure is an impurity concentration distribution diagram in the thickness direction of a gate turn-off thyristor according to an embodiment of the present invention. 1...wafer, 2...P ₁ layer, 3...N ₁ layer, 4...P ₂ layer,
5...N ₂ layer, 6...High impurity concentration layer, 11...Intermediate impurity concentration layer, _G1 ...On-gate electrode, _G2 ...Off-gate electrode.

Claims (1)

[Claims] 1. A semiconductor device consisting of a wafer of semiconductor material having four layers of alternating conductivity types forming three consecutively arranged junctions, a main electrode portion consisting of an anode electrode and a cathode electrode, and a layer adjacent to the cathode layer. In a gate turn-off thyristor provided with a control electrode portion having a high concentration impurity buried in the layer, an intermediate concentration impurity layer is provided adjacent to the high concentration impurity layer in the layer provided with the high concentration impurity; A gate turn-off thyristor characterized in that the concentration of the layer is lower than the concentration of the high concentration impurity layer and higher than the concentration of the layer provided with the high concentration impurity.