JPH0136722B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a frequency modulation wave detection device, especially an AM
This invention relates to a frequency modulation wave detection device with improved suppression ratio (referred to as AMR).

A detection device having the configuration shown in FIG. 1 is known as a conventional frequency modulation (hereinafter referred to as FM) receiver including an intermediate frequency amplification stage and an FM detector. In FIG. 1, a signal frequency-converted to an intermediate frequency by the FM front end (hereinafter referred to as an IF signal) is supplied to an input terminal 2 of an FM intermediate frequency amplifier (hereinafter referred to as FM IF) 1. The FM IF1 is composed of n stages of amplitude limiting amplifier circuits (hereinafter referred to as limiter amplifiers) connected in series, but generally, n=3, the first stage limiter amplifier 3, the second stage limiter amplifier 4, and the third stage limiter amplifier 5. Often configured. The IF signal amplified by the third-stage limiter amplifier 5 passes through a low-pass filter circuit 6 to attenuate frequencies above the fundamental wave of the IF signal, converts the signal into an audio signal by an FM detector 7, and outputs the signal to an audio signal output terminal 8. Output. Further, each of the above circuits is supplied with bias from a bias circuit 9.

FIG. 2 shows an example of a specific circuit of the one shown in FIG.
6 and 17, 2 is an input terminal, and the base of transistor 11 supplies bias to the base of transistor 10 from bias supply terminal 2' through resistor 18, and at the same time bypasses it with capacitor 19 to reduce the input impedance of FM IF1. It is determined by a resistance of 18.

The second stage limiter amplifier is transistor 2
0, 21, 22, 23, 24, 25 and resistance 26,
It is composed of 27, 28, 29, 30, 31, and 32.

The third stage limiter amplifier is transistor 33,
34, 35, 36 and resistors 37, 38, 39, 4
It is composed of 0, 41, and 42. Further, the third stage limiter amplifier is operated by providing a bypass terminal 43 and connecting a capacitor 44 so that the transistors 35 and 36 function as an amplifier.

The low-pass filter 6 includes a transistor 45 and a resistor 46,
47, 48, capacitors 49, 50, and a transistor 45
The emitter output of is guided to the output terminal 100 of the FM IF1, and the resistor 51, inductor 52, and capacitors 53 and 54 constitute a phase shifter. Both ends of the inductor 52 are connected to a first input terminal 101 and a second input terminal 102 of the detector 7 .

The FM detector 7 includes transistors 103, 104,
105, 106, 107, 108, 109 resistance 1
10, 111, 112, 113, 114 and capacitors 115, 116. The audio signal detected by the FM detector 7 is transmitted through transistors 117, 118,
A capacitor 123 is provided at the output terminal of the resistor 122, which is inverted by a current inverting circuit of resistors 120 and 121, and the resistor 122 and capacitor 123 provide a de-emphasis time constant for filtering high-frequency components. There is. 124 is an audio signal output terminal.

A bias circuit 9 that biases the FM IF1 and the FM detector 7 includes transistors 201, 202,
203, 204, 205, 206, 207, resistor 208, 209, 210 Zener diode 2
It consists of 11.

Important characteristics of FM IF1 and FM detector overall characteristics include FM limiting sensitivity and AMR. First, when setting the gain of the FM IF stage, this gain is determined from the required limiting sensitivity.
Normally, in the case of the peak detector shown in _FIG .
FM for −3dB input Vi at input saturation level of
It is determined by the difference between the gain and loss immediately before inputting the IF from the first stage to the third stage, and is given by the formula.

Vi ( _lin = Vi− (A _V1 − Gloss ₁ + A _V2 − Gloss ₂ − Gloss ₃ ) ... However, A _V1 : 1st stage limiter amplifier gain Gloss ₁ : 1st stage limiter amplifier level shift loss A _V2 : 2nd stage limiter amplifier gain Gloss ₂ : Level shift loss of 2nd stage limiter amplifier Gloss ₃ : 3rd stage limiter amplifier by resistors 41 and 42
Amplifier input matching loss Here, the value of Vi is determined by the formula from the differential saturation input level of transistors 35 and 36.

Vi=4kT/q/(√2・2√2)=92dBμv... However, k: Boltzmann's constant T: Absolute temperature
q: Coulomba The level shift losses Gloss ₁ and Gloss ₂ of each stage are the passing losses of the emitter follower and are small values, so they are ignored. The third stage limiter/amplifier/input matching loss Gloss ₃ cannot be set to a very small value because the resistors 41 and 42 normally act as a load for the emitter follower transistors 23 and 22, and a value of about 1K to 4KΩ is common. , since the input impedance of the third stage limiter amplifier is about 5KΩ.
Gloss ₃ has a large value of 2dB to 5dB. Normally, the limiting sensitivity of FM IF is 20~
A value of 40 dBμv is required, and even if we consider the case where the input limiting sensitivity is 40 dBμv, the limiter amplifier gains A _V1 and A _V2 of the first and second stages are as follows.

(A _V1 + A _V2 ) = Vi - Vi ( _lin ) + Gloss ... = 92 dBμ - 40 dB μ + 5 dB = 57 dB ... If the first and second stage limiter amplifier gains are made equal from the result of the formula, it will be approximately 30 dB from the following formula.

A _V1 = A _V2 ≒30dB... The gain in one stage of limiter amplifier is expressed by the formula.

A _V1 = A _V2 = 4kT/q・I ₀・R _L ... However, I _O : Differential common constant current R _L : Differential load resistance Differential load resistance R _L is the intermediate frequency of FM band 10.7MHz
There is an upper limit value of approximately 2KΩ due to stray capacitance. Even if the load resistance is 2KΩ, in order to obtain a gain of 30dB per stage, the common constant current must be I _O = 1.5m.
A: It is necessary. Also, the amplitude V ₀ as a voltage drop of the load resistance R _L per stage is V _O = R _L · I _O = 2KΩ x 1.5 mA = 3 V. This means that an amplitude as large as 3 V is driving the next stage.

Input signal level at one stage of limiter amplifier
Looking at the phase transition of Vi _(sig) , input signal, and output signal, as shown in Figure 3, there is little change in the input/output phase until Vi _(sig) is 300mv・rms, but at higher input signal levels Vi _{( sig)} , the input and output phases change significantly, and what was previously a delayed phase has now become a return phase. Focusing on this point, the load resistance of the first and second stages
Figure 4 shows the overall characteristics of the FM IF shown in Figure 2, where R ₁₄ and R ₂₆ are 2KΩ, and the differential constant current of each limiter amplifier is 1.5mA. In Figure 4, a is the detection output characteristic, b
indicates AMR characteristics. In particular, in the AMR characteristics, there is a region where two large peaks form and deteriorate.This is because, as mentioned above, the three-stage limiter amplifier applies the limiter sequentially from the third stage to the second stage to the first stage depending on the input level. In order to exceed the Vi _(sig) input level of 300mv・rms shown in Figure 3 and drive the next stage, phase modulation is added to the FM signal wave being amplified, and its components are also
Detected by FM detector, audio output terminal 12
This is due to the fact that it is output to 4.

The present invention eliminates these drawbacks of the prior art and improves the above-mentioned AMR and limiting sensitivity.

The frequency modulated wave detection device according to the present invention includes an amplitude limiting amplifier having a sub-connection circuit of n-stage amplitude limiting amplifier circuits, a low-pass filter circuit receiving the output of this amplifier, and a low-pass filter circuit for receiving the output of this amplifier. a frequency modulation wave detector receiving an output, each of the amplitude limiting amplifier circuits having a first and a second amplifier circuit connected in a differential manner;
transistors and collector loads of these transistors, and in the (n-1)th stage amplitude limiting amplifier circuit from the first stage, the collectors of the first and second transistors in the previous stage amplitude limiting amplifier circuit are connected to the second stage amplitude limiting amplifier circuit. The amplitude limiting amplifier circuit is directly connected to the bases of the first and second transistors in the limiting amplifier circuit, and the amplitude of the first to (n-1)th stage amplitude limiting amplifier circuits is the same as the amplitude limiting amplifier circuit of the nth stage. It is characterized by being set smaller than the amplitude of the circuit.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 5 is a circuit diagram of an embodiment of the present invention, and explanations of parts that are the same as those of the conventional example shown in FIG. 2 will be omitted.

FM IF1 has more stages than the conventional example in Figure 2, and the load is taken out from both differential outputs using a double-end output, and each limiter amplifier has a configuration without level shift. ing.

The first stage limiter amplifier is transistor 1
0 and 11 are differentially connected, resistors 130 and 131 are used as loads, transistors 128 and 129 and resistor 13
2, 133, and 134 constitute a constant current circuit.

The second stage limiter amplifier is a transistor 20,
21 are differentially connected, and is composed of load resistors 135, 136 and a constant current determining resistor 137. The third stage limiter amplifier is transistors 138 and 13.
9 are differentially connected, and is composed of load resistors 140, 141 and a constant current determining resistor 142. The fourth stage limiter amplifier has transistors 143 and 145 connected differentially, load resistors 145 and 146, and constant current determining resistor 147.The limiter amplifier in the fourth stage is the third stage in the conventional example. The drive for the third stage is transistors 148 and 149, and resistor 15.
It goes through an emitter follower consisting of 0.151. Also connected are resistors 152 and 153 that feed back bias from this emitter follower to the first stage.

To bias the limiters in the first to fourth stages, the bias circuit 9 includes transistors 215, 216, and a resistor 214 to create a bias potential lower than the bias in the fifth stage, and each stage has an independent transistor 20.
6,211,212,213. Terminals 126 and 125 are a power terminal and a ground terminal for supplying power to the circuit.

Now, if the gain of each limiter/amplifier stage is A _V1 ...A _V5 , then the limiting sensitivity Vi in Figure 5 is
(lim)′ is given by the formula Vi( _lin )′=Vi(A _V1 +A _V2 +A _V3 +A _V4 ) …… A _V1 =4kT/q・I _O・2R _L =A _V2 =A _V3 =A _V4 ... If R _L = 500Ω I _O = 0.5mA in common, then Vi ( _lin )' = Vi-4・A _V1 = 92 ^dB 〓-4×14 ^dB 〓 = 36 _dB 〓 ……Therefore, it is better than the conventional example. Low load resistance (approximately 1/4) and
Although the constant current is small (approximately 1/3), high limiting sensitivity can be obtained. The phase shift of the entire limiter amplifier due to the increase in the number of stages can be maintained at approximately the same level by reducing the load on each stage and by eliminating the conventional third stage input base resistance.

As shown in the characteristics of Figure 6, AMR
The peaks and valleys of are small and the absolute value is large. This means that the amplitude V ₀ of each stage of the limiter amplifier is V ₀ = R _L × I _O = 250 m
This has the effect of reducing the amplitude of v _pp and conventional 3v _pp to 1/12. Generally, AMR can be improved by selecting the output amplitude of each limiter/amplifier to be 1V _pp or less as shown in FIG.

Also, since the amplitude of each limiter/amplifier stage becomes smaller, the generation of odd harmonics of the intermediate frequency input signal that occurs when the limiter stage is saturated is reduced, and the FM IF
There is less unnecessary radiation from the stage, and therefore unnecessary radiation returning to the FM front end section can be reduced.

As for the operating current, the constant current value of the limiter amplifier in the 5th stage that drives the low-pass filter 6 is larger than that in the 1st to 4th stages, and therefore the output amplitude is also larger.
Since the limiter amplifier constant current value of the first to fourth stage limiter amplifiers can be configured to be about 1/3 of that of the conventional example, even if the number of limiter amplifier stages increases, there is no need for level shifting, so there is an effect of power saving.

According to the present invention, a frequency modulation wave detection device with improved AMR and limiting sensitivity can be obtained.

[Brief explanation of drawings]

Figures 1 and 2 are a block diagram and circuit diagram of an example of a conventional example, Figure 3 is a characteristic diagram of a differential limiter amplifier, Figure 4 is an explanatory diagram explaining the characteristics of a conventional example, and Figure 5. is a circuit diagram of one embodiment of the present invention, and FIG. 6 is a diagram explaining its characteristics. 1...FM IF, 3, 4, 5...Limiter amplifier, 6...Low pass filter, 7...FM detector, 9
...Bias circuit.

Claims (1)

[Claims] 1. An amplitude-limiting amplifier having a sub-connection circuit of n-stage amplitude-limiting amplifier circuits, a low-pass filter circuit that receives the output of this amplifier, and a frequency modulation wave detector that receives the output of this low-pass filter circuit. , each of the amplitude limiting amplifier circuits having a first circuit connected in a differential manner.
and a second transistor and a collector load of these transistors, and the (n-1)th transistor from the first stage.
In the amplitude-limiting amplifier circuit in the first stage, the collectors of the first and second transistors in the amplitude-limiting amplifier circuit in the preceding stage are directly connected to the bases of the first and second transistors in the amplitude-limiting amplifier circuit in the succeeding stage, respectively, A frequency modulated wave detection device, wherein the amplitudes of the first to (n-1)th stage amplitude limiting amplifier circuits are set smaller than the amplitudes of the nth stage amplitude limiting amplifier circuits.