JPH0137007B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Josephson timing signal generation circuit configured using Josephson switches.

Conventionally, as a Josephson timing signal generation circuit configured using a Josephson switch,
A device having the configuration described below with reference to FIG. 1 has been proposed.

That is, Josephson switches S1, S2,
S3' and S4, and inductors L1 and L2.

In this case, Josephson switches S1, S2,
Each of S3' and S4 has a Josephson junction element J, a bias current line B through which the Josephson junction element J is inserted, and a control line C, and the bias current line B has "1" and "1" in binary display. When the bias current that takes "0" is supplied as "1", and the control current that takes "1" and "0" in binary display as "0" is supplied to control line C, "1'', the Josephson junction element J has the function of converting from a zero voltage state to a voltage applied state.

Thus, a current path P1 is formed including the Josephson junction element J of the Josephson switch S1, and the control line C of the Josephson switch S3', the Josephson junction element J of the Josephson switch S2, the inductor L1, and the Josephson switch S3'. For example, as shown in the figure, the inductor L1, the Josephson junction element J of the Josephson switch S2, and the control line C of the Josephson switch S3' are connected in series to form a series circuit H1. Circuit H1
A current path P2 is formed including the current path P2. In this case, a load M1 is inserted in the current path P2.

The current paths P1 and P2 are connected in parallel to form a parallel circuit Q1, and the parallel circuit Q1 is inserted into the power supply line K1.

Further, a current path P3 is formed including the Josephson junction element J of the Josephson switch S3',
Further, the Josephson junction element J of the Josephson switch S4 and the inductor L2 are connected in series to form a series circuit H2, and a current path P4 is formed including the series circuit H2. In this case, a load M2 is inserted in the current path P4.

Then, current paths P3 and P4 are connected in parallel to form a parallel circuit Q2, and the parallel circuit Q2
is inserted into the power supply line K2.

Furthermore, the control line C of the Josephson switch S1
A current path P5 is formed including the current path P5.
is inserted into the input signal line W1.

Furthermore, the control line C of Josephson switch S2
A current path P61 is formed including the current path P61.
61 is inserted into the reset signal line R1.

Further, a current path P62 is formed including the control line C of the Josephson switch S4, and the current path P6
2 is inserted into the reset signal line R2.

The above is the configuration of the conventionally proposed Josephson timing signal generation circuit.

According to the Josephson timing signal generation circuit having such a configuration, the operation described below with reference to FIG. 2 can be obtained.

That is, a bias current of "0" that takes "1" and "0" in binary display is supplied to power supply lines K1 and K2, and a bias current that takes "1" and "0" in binary display is supplied to input signal line W1. ” is supplied as “0”, and the reset signal line R1 is
From the state in which the reset signals SR1 and SR2, which take ``1'' and ``0'' in the binary display to R2 and SR2, are both supplied as ``0'', the bias current is supplied as ``1'' to both power supply lines K1 and K2. For example, Josephson junction elements J of Josephson switches S1 and S3' both maintain a zero voltage state, while current path P
2 and P4 have inductors L1 and L2, respectively.
is inserted in the current paths P1 and P3,
Currents that take a binary value of 1 flow through the Josephson junction elements J of the Josephson switches S1 and S3', respectively, but currents that take a binary value of 1 flow through current paths P2 and P4. does not flow.

From this state, input signal SW1 is input to input signal line W1 at time t1, as shown in FIG. 2A.
If "1" is supplied from the time to the time t5, the control line C of the Josephson switch S1 is connected to the current path P5.
Since a current that takes "1" on the binary display flows through the switch, the Josephson junction element J of the Josephson switch S1 changes from the zero voltage state to the voltage state, and based on this, the current The current flowing in path P1 that takes "1" on the binary display is now flowing through current path P1.
Instead of the current flowing to the current path P2, the current flowing to the current path D
As shown in , when the timing signal ST1 takes “1” and “0” in binary display as “1”, the load M
Start flowing through 1. However, in this case, since the inductor L1 is inserted in the current path P2, the timing signal ST1 changes from the state of "0" in the binary display to the binary display over time from time t1 to time t3. Therefore, the timing signal ST1 is obtained as "1" in binary representation from time t3.

In this way, if the timing signal ST1 that takes "1" in the binary display flows through the current path P2, the current that takes "1" in the binary display does not flow in the current path P1, so the timing signal ST1 After time t1, the Josephson junction element J of the Josephson switch S1 returns from the voltage-carrying state to the zero-voltage state.

In addition, since the timing signal ST1 which takes "1" in the binary display flows through the current path P2, the Josephson junction element J of the Josephson switch S3'
From time t2, which is after time t1 and before time t3, the zero voltage state is switched to the voltage state, and based on this,
The current that has been flowing through current path P3 and takes a value of "1" on a binary display is now flowing through current path P4, as shown in Figure 2E, instead of flowing through current path P3.
It starts flowing through the load M2 as the timing signal ST2 takes "1" and "0" in binary representation as "1". In this case, since the inductor L2 is inserted in the current path P4, the timing signal ST2 changes from the state of "0" in the binary display to "1" in the binary display over time from time t2 to time t4. ” state, therefore, the timing signal
ST2 is obtained as "1" in binary representation from time t4.

In this way, if the timing signal ST2 that takes "1" in the binary display flows through the current path P4, the current that takes "1" in the binary display does not flow in the current path P2, so the timing signal ST2 After time t3, the Josephson junction element J of the Josephson switch S3' returns from the voltage-applied state to the zero-voltage state.

Furthermore, as mentioned above, the timing signal ST
After 1 is obtained as "1" in the binary representation from time t3, a reset signal SR1 which takes "1" and "0" in the binary representation is applied to the reset signal line R1, as shown in FIG. 2B. , from time t6 after t3 to time t9
If "1" is supplied in the binary display until then, a current that shows "1" in the binary display will flow through the current path P61 through the control line C of the Josephson switch S2, so Josephson The Josephson junction element J of the son switch S2 switches from the zero voltage state to the voltage state from time t6, and based on this, the timing signal ST1 which has been showing "1" in the binary display on the current path P2 is used. The current that has been flowing and takes "1" on the binary display starts to flow through the current path P1 instead of flowing through the current path P2.

Therefore, the timing signal ST1 is applied to the current path P2.
starts to change from "1" on the binary display to "0" on the binary display. In this case, since the inductor L1 is inserted in the current path P2,
The timing signal ST1 varies from time t6 to time t
7, the state of "1" on the binary display changes to the state of "0" on the binary display, and therefore,
The timing signal ST1 is obtained as "0" in binary representation from time t7.

In addition, as described above, the timing signal ST2
After is obtained as "1" in binary representation from time t4,
As shown in FIG. 2C, the reset signal SR2 which takes "1" and "0" in binary display is applied to the reset signal line R2 at the time t7 when the timing signal ST1 becomes "0" in binary display. If "1" is supplied in the binary display from time t8 to time t11, Josephson switch S4 is applied to current path P62.
Since a current that takes "1" in the binary display flows through the control line C of Based on the above, the current that takes the value "1" in the binary display, which was previously flowing as the timing signal ST2 that takes "1" in the binary display, is now flowing in the current path P4. The current begins to flow through path P3.

Therefore, the timing signal ST2 is applied to the current path P4.
starts to change from "1" on the binary display to "0" on the binary display. In this case, since the inductor L2 is inserted in the current path P4,
The timing signal ST2 varies from time t8 to time t
10, the state of "1" on the binary display changes to the state of "0" on the binary display, and therefore, the timing signal ST2 is obtained as "0" on the binary display from time t10. It will be done.

From the above, it can be seen that according to the conventional Josephson timing signal generation circuit shown in FIG. W1
If input signal SW1 is supplied as "1" in binary display for the scheduled time, based on this, timing signal ST1 can be supplied as "1" in binary display to load M1, and the load The timing signal ST2 can be supplied to M2 as "1" in binary representation from a time later than the time when timing signal ST1 becomes "1" in binary representation.

In addition, if the reset signal SR1 is supplied to the reset signal line R1 as "1" in binary display for the scheduled time from such a state, based on this, the load M1 will be reset to "1" in binary display as before. The timing signal ST1, which was being supplied by the
ST1 is no longer supplied in the state of "1" in binary display.

Furthermore, a reset signal is sent to the reset signal line R2.
If SR2 is supplied as "1" in binary display for the scheduled time after timing signal ST1 becomes "0" in binary display, based on this, the load M2 will be displayed in binary display. The timing signal ST2, which was supplied as "1", becomes "0" in binary display, and therefore, the timing signal ST2 is supplied to the load M2 as "0".
2 is displayed as a binary value and is no longer supplied in the state of "1".

In addition, after such a state is reached, as described above, the input signal SW is connected to the input signal line W1 again.
If 1 is supplied as "1" in binary display at the scheduled time,
Similarly to the above, a timing signal is applied to load M1.
ST1 can be supplied with "1", and
The timing signal ST2 can be supplied to the load M2 as "1" in binary representation from a time later than the timing signal ST1 becomes "1" in binary representation.

Therefore, according to the conventional Josephson timing signal generation circuit shown in FIG.
Each time the input signal SW1 is supplied as "1" in the scheduled time binary representation, the timing signal ST1 can be supplied as "1" in the scheduled time binary representation to the load M1, and the timing signal ST1 can be supplied as "1" in the scheduled time binary representation. The timing signal ST2 can be supplied as "1" in binary representation from a time later than the time when timing signal ST1 becomes "1" in binary representation.

However, in the case of the conventional Josephson timing signal generation circuit shown in FIG.
1 and form a current path P62 including the control line C of the Josephson switch S4,
If the current path P62 is not inserted into the reset signal line R2 and the reset signals SR1 and SR2 are supplied to the reset signal lines R1 and R2 as "1" in binary display at the scheduled time, it will be reset again. , input signal SW1 to input signal line W1
By supplying "1" in the scheduled time binary display, the effect of sequentially supplying the timing signals ST1 and ST2 to the loads M1 and M2, respectively, cannot be obtained. Josephson timing signal generation circuits become complicated and large in size, and two reset signal lines R1 and R2 and two reset signals SR1 and SR2 to be supplied to them, respectively, are not provided. The drawback was that the circuit could not be activated.

Furthermore, in the case of the Josephson timing signal generation circuit shown in FIG.
From the point in time after ST1 changes to the state of "0" in binary representation due to the reset signal SR1 being "1" in binary representation, it is necessary to supply it as "1" in binary representation.
Therefore, when the reset signal SR2 is supplied to the reset signal line R2, the reset signal SR2
2 must be supplied as "1" in binary representation from a time later than the time when the reset signal SR1 supplied to reset signal line R1 becomes "1" in binary representation.

Therefore, the input signal SW1 is connected to the input signal line W1.
is supplied as "1" in the binary display for the scheduled time, and after sequentially supplying the timing signals ST1 and ST2 to the loads M1 and M2, respectively, the input signal line W
1, the input signal SW1 is supplied as "1" in the scheduled time binary display, and the timing signals ST1 and ST
By the time 2 is supplied to the loads M1 and M2 in sequence again, the time when the reset signal SR2 becomes "1" in the binary display is delayed from the time when the reset signal SR1 becomes "1" in the binary display. You will need extra time for the time you spend there.

Therefore, in the case of the conventional Josephson timing signal generation circuit shown in FIG.
Then, the input signal SW1 is sequentially supplied as "1" in binary display for the scheduled time, and the load M1 is
and M, 2 are sequentially provided with timing signals ST1, respectively.
It has a drawback that there is a certain limit to speeding up the operation of supplying ST2 and ST2 as "1" in binary representation for the scheduled time.

Therefore, the present invention aims to propose a novel Josephson timing signal generation circuit free from the above-mentioned drawbacks, which will become clear from the detailed description below with reference to the drawings from FIG. 3 onwards. Dew.

First, an embodiment of the Josephson timing signal generation circuit according to the first invention of the present application will be described with reference to FIG.

In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. 3 has the same configuration as the conventional Josephson timing signal generation circuit shown in FIG. 1, except for the following points.

That is, the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. 3 is different from the Josephson switch S in the conventional Josephson timing signal generation circuit shown in FIG.
3' is the Josephson junction element J and the bias current line B which inserts the Josephson junction element J.
and control lines C1 and C2, and when a bias current of "1" is supplied to the bias current line B, which takes "1" and "0" in binary display, the control lines C1 and C2 are supplied with a bias current of "1". When the control lines that take "1" and "0" in the binary display are both supplied with "1", the Josephson junction element is replaced by a Josephson switch S3 that changes from the zero voltage state to the voltage state. It has the following configuration.

Further, the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. 3 is different from the conventional Josephson timing signal generation circuit shown in FIG. The Josephson junction element J of the Josephson switch S2, the inductor L1, and the control line C of the Josephson switch S3' are connected in series. and the control line C2 of the Josephson switch S3 are connected in series.

Furthermore, the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG.
In the conventional Josephson timing signal generation circuit shown in the figure, the current path P5 is formed to include the control line C of the Josephson switch S1;
and the control line C1 of the Josephson switch S3 are connected in series.

Furthermore, the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG.
In the conventional Josephson timing signal generation circuit shown in FIG.
is omitted, and therefore, instead of the current paths P61 and P62 being inserted into the reset signal lines R1 and R2, respectively, the control line C of the Josephson switch S2 and the control line C of the Josephson switch S4 are inserted.
are connected in series to form a series circuit H4,
A current path P6 is formed including the series circuit H4, and the current path P6 is connected to the reset signal line R.
It has a configuration in which it is inserted into.

The above is an example of the configuration of the Josephson timing signal generation circuit according to the first invention of the present application.

According to the configuration of the Josephson timing signal generation circuit according to the first invention of the present application, the operation described below with reference to FIG. 4 can be obtained.

That is, bias currents that take "1" and "0" in binary display are supplied to power supply lines K1 and K2 at "0", and input signal line W1 is supplied with "1" and "0" in binary display. The input signal SW1 which takes ``0'' is supplied as ``0'', and the reset signal line R is supplied with a reset signal which takes ``1'' and ``0'' in binary display.
If SR is supplied at "0" and bias current is supplied at "1" to both power supply lines K1 and K2, Josephson junction elements J of Josephson switches S1 and S3 will both maintain a zero voltage state. , on the other hand, since inductors L1 and L2 are inserted in the current paths P2 and P4, respectively, the current paths P1 and P3 pass through the Josephson junction elements J of the Josephson switches S1 and S3, respectively, and both display binary values. A current that takes "1" flows through the current paths P2 and P4, but a current that takes "1" in the binary display does not flow through the current paths P2 and P4.

In this state, input signal line SW1 is
As shown in FIG. 4A, if "1" is supplied from time t1 to time t5, the control line C of Josephson switch S1 and the control line C1 of Josephson switch S3 are connected to current path P5. Since a current that takes "1" on the binary display flows through the switch, the Josephson junction element J of the Josephson switch S1 changes from the zero voltage state to the voltage state, and based on this, the current The current that was flowing through path P1 and which shows "1" on the binary display is now flowing through current path P2 instead of flowing through current path P1, as shown in Figure 4C.
The timing signal ST1, which takes "1" and "0" in binary representation, starts to flow through the load M1 as "1". However, in this case, the current path P
The timing signal ST1 changes from the state of "0" to 2 on the binary display over time from time t1 to time t3.
The state changes to "1" in the value display, and accordingly, the timing signal ST1 changes to "1" in the binary display from time t3.
It can be obtained with

In this way, if the timing signal ST1 that takes "1" in the binary display flows through the current path P2, the current that takes "1" in the binary display does not flow in the current path P1, so the timing signal ST1 After time t1, the Josephson junction element J of the Josephson switch S1 returns from the voltage-carrying state to the zero-voltage state.

Further, a timing signal ST1 that takes "1" in binary display flows through the current path P2, while the current path P5,
Therefore, since a current that shows "1" in the binary display is flowing through the control line C1 of the Josephson switch S3,
The Josephson junction element J of the Josephson switch S3 switches from the zero voltage state to the voltage state from time t2 after time t1 and before time t3, and based on this, the current that has been flowing to path P3 until now Instead of the current flowing through current path P3, which takes the value ``1'' in the binary representation, the current takes ``1'' and ``0'' in the binary representation, as shown in Figure 2D, in the current path P4. As the timing signal ST2 is "1", it starts flowing through the load M2. In this case, since the inductor L2 is inserted in the current path P4, the timing signal ST2 changes from the state of "0" in the binary display to "1" in the binary display over time from time t2 to time t4. Therefore, the timing signal ST2 is obtained as "1" in binary representation from time t4.

In this way, if the timing signal ST2 that takes "1" in the binary display flows through the current path P4, the current that takes "1" in the binary display does not flow in the current path P2, so the timing signal ST2 After time t2, the Josephson junction element J of the Josephson switch S3 returns from the voltage-applied state to the zero-voltage state.

Furthermore, as mentioned above, the timing signal ST
1 and ST2 from time t3 and t4, respectively.
After "1" is obtained on the value display, the reset signal line R receives "1" on the binary display as shown in Figure 2B.
If the reset signal SR, which assumes "0" and "0", is supplied as "1" in binary display from time t6 after t4 to time t8, the control lines of Josephson switches S2 and S4 will be connected to current path P6. Through C, 2
Since a current flows that takes "1" in the value display, the Josephson junction elements J of the Josephson switches S2 and S4 switch from the zero voltage state to the voltage state from time t6, and based on this, the Current path P
The current that flows as the timing signal ST1 which takes "1" in the binary display to 2 and P4 respectively, and which takes "1" in the binary display, flows to the current paths P2 and P4, respectively.
4, the currents start flowing through current paths P1 and P3, respectively. Therefore, timing signal ST1 is applied to current paths P2 and P4, respectively.
And ST2 was displayed as "1" in binary display,
It starts to become "0" on the binary display. In this case, inductors L are connected to current paths P2 and P4, respectively.
1 is inserted, the timing signal ST1
and ST2 change from the state of "1" in binary display to the state of "0" in binary display over time from time t6 to time t7, and therefore, the timing signals ST1 and ST2 are Both values are obtained as "0" on a binary display from time t7. From the above,
According to the Josephson timing signal generation circuit of the first invention of the present application shown in FIG. 3, as in the case of the conventional Josephson timing signal generation circuit shown in FIG. If the input signal SW1 is supplied to the input signal line W1 as "1" in the binary display for a scheduled time while the current is being supplied as "1" in the binary display, based on this,
As in the case of the conventional Josephson timing signal generation circuit shown in FIG.
2, the timing signal ST1 is "1" in binary display.
"1" in binary display from the time later than the time when
can be supplied with

In addition, if the reset signal SR is supplied to the reset signal line R1 as "1" in binary display for the scheduled time from this state, based on this, the loads M1 and M2 will be changed to the binary display respectively. Timing signals ST1 and ST2 that were supplied at "1" are now
Both are in the state of "0" in binary display, therefore,
Timing signals ST1 and ST1 are applied to loads M1 and M2.
ST2 is no longer supplied in the state of "1" in binary display.

In addition, after such a state is reached, as described above, the input signal SW is connected to the input signal line W1 again.
If 1 is supplied as "1" in binary display at the scheduled time,
In the same way as described above, the timing signal ST1 can be supplied to the load M1 again at "1", and the timing signal ST2 can be supplied to the load M2 at a higher value than when the timing signal ST1 becomes "1" in binary display. From the time of delay, it is possible to supply "1" on a binary display.

Therefore, in the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. 3, as in the case of the conventional Josephson timing signal generation circuit shown in FIG. W1
Each time the input signal SW1 is supplied as "1" in the scheduled time binary representation, the timing signal ST1 can be supplied as "1" in the scheduled time binary representation to the load M1, and the timing signal ST1 can be supplied as "1" in the scheduled time binary representation. The timing signal ST2 can be supplied as "1" in binary representation from a time later than the time when timing signal ST1 becomes "1" in binary representation.

However, in the case of the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. 3, the control line C of the Josephson switch S2,
The control line C of Josephson switch S is connected in series to form a series circuit H4.
The current path P6 is inserted into the reset signal line R, and the reset signal SR is supplied to the reset signal line R as "1" in binary display at a scheduled time. Once the input signal SW is connected to the input signal line W1 again,
By supplying "1" as "1" in the binary display for the scheduled time, it is possible to supply the timing signals ST1 and ST2 to the loads M1 and M2 again. The configuration of the signal generation circuit is simpler and more compact than the conventional Josephson timing signal generation circuit shown in FIG. It has the great feature of being able to operate the Josephson timing signal generation circuit just by preparing the SR.

Furthermore, in the case of the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. By supplying the input signal SW1 as "1" in the scheduled time binary display to the signal line W1, it becomes possible to supply the timing signals ST1 and ST2 to the loads M1 and M2 again.
The input signal SW1 is supplied to the input signal line W1 as "1" in the scheduled time binary display, and the timing signal is
After supplying ST1 and ST2 to loads M1 and M2, input signal line W1 is supplied again as "1" in the scheduled time binary display, and timing signals ST1 and ST2 are supplied to loads M1 and M2 again. The time taken to generate the timing signal can be made shorter than that of the conventional Josephson timing signal generation circuit shown in FIG.

Therefore, in the case of the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG.
The input signal SW1 is sequentially supplied to the input signal line W1 as "1" in the scheduled time binary representation, and the timing signals ST1 and ST2 are sequentially supplied to the loads M1 and M2 as "1" in the scheduled time binary representation. 1" can be made faster than in the case of the conventional Josephson timing signal generation circuit shown in FIG.

Next, an embodiment of the Josephson timing signal generation circuit according to the second invention of the present application will be described with reference to FIG.

In FIG. 3, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

The Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. 3 has the same configuration as the first invention of the present application shown in FIG. 3 except for the following matters.

That is, the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. 5 is the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. It has a configuration including a Josephson switch S5 having a Josephson junction element J, a bias current line B interposed therebetween, and a control line C, similar to S2 and S4.

Further, the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. 5 is different from the current path P1 in the Josephson timing signal generation circuit according to the first invention of the application shown in FIG.
is formed including the Josephson junction element J of the Josephson switch S1, and the Josephson junction element J of the Josephson switch S1 is formed to include the Josephson junction element J of the Josephson switch S1.
and the Josephson junction element J of the Josephson switch S5 are connected in series.

Furthermore, the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG.
In the Josephson timing signal generation circuit according to the first invention of the present application shown in the figure, a current path P7 is formed including the control line C of the Josephson switch S5 described above, and the current path P7 is connected to the input signal line W2. It has a configuration in which it is inserted into.

The above is an example of the configuration of the Josephson timing signal generation circuit according to the second invention of the present application.

According to this configuration, it has the same configuration as the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. 3, except for the above-mentioned matters.

The Josephson switch S5 itself has the same function as the Josephson switch S1 itself.

For this reason, regarding the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. Assuming that an input signal SW2 that takes "1" and "0" is supplied, as long as the input signal SW2 is "0" in binary representation, the first application shown in FIG.
The Josephson timing signal generation circuit according to the third invention operates in exactly the same manner as described above.

Therefore, although detailed explanation is omitted, FIGS.
Figure 6 A, corresponding to B, C and D, respectively;
As is clear with reference to the left half of C, D, and E, if the input signal SW1 is supplied to the input signal line W1 as "1" in the binary display for the scheduled time, based on this, the As in the case of the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. The timing signal ST1 can be supplied as "1" in binary display from a time later than the time when it becomes "1" in binary display.

In addition, in this way, both timing signals ST1 and ST2 are displayed as "1" in binary display for loads M1 and M2.
The reset signal line R
If the reset signal SR is supplied as "1" in the scheduled time binary display, the load M1 will be From the state where the timing signals ST1 and ST2 were being supplied to M2 and M2 in the state of "1" in binary display, the load M1
The timing signals ST1 and ST2 are in the state of "1" in binary display and are not supplied to M2.

However, according to the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG.
1 and ST2 are respectively "1" in binary display and are not being supplied, the input signal line W2
In addition, as shown in FIG. 6B, if the input signal SW2, which takes "1" and "0" in binary display, is supplied as "1" from time t21 to time t23, the current path P7 becomes Josephson switch S5 control line C
Since a current that takes a binary value of 1 flows through Josephson junction element J of series circuit S5.
changes from a zero voltage state to a voltage state, and based on this, the current that had been flowing through current path P1, which was ``1'' on the binary display, was now flowing through current path P1 instead. , the current path P2 starts flowing through the load M1 with the timing signal ST1 set to "1" in binary representation, as shown in FIG. 6D.
However, in this case, inductor L1 is connected to current path P2.
is inserted, the timing signal ST1 is
Over time from time t21 to time t23, the state of "0" on the binary display changes to the state of "1" on the binary display, and therefore the timing signal
ST1 is obtained as "1" in binary representation from time t23.

In this way, if the timing signal ST1 that takes "1" in the binary display flows in the current path P2, no current that takes "1" in the binary display flows in the current path P1, so Joseph After time t21, the Josephson junction element J of the switch S5 returns from the voltage-applied state to the zero-voltage state.

In addition, since the timing signal ST1 that takes "1" in the binary display flows through the current path P2, a current that takes "1" in the binary display flows in the Josephson switch S3 control line C2. Since no current indicating "1" in the binary display is flowing through the control line C1 of the Josephson switch S3, the Josephson junction element J of the Josephson switch S3 maintains a zero voltage state.

Furthermore, as mentioned above, the timing signal ST
After 1 is obtained as "1" in binary display from time t23, the reset signal SR is applied to the reset signal line R from time t24 after time t23 to time t26, as shown in the right half of FIG. 6C. If "1" is supplied in the binary display until then, a current that indicates "1" in the binary display will flow through the current path P6 through the control line C of the Josephson switch S2, so Josephson Josephson junction element J of son switch S2 at time t
24, the state changes from zero voltage state to voltage state, and based on this, the current path P2 changes to "1" in the binary display, which had been flowing as the timing signal ST1 which took "1" in the binary display. The current starting to flow through the current path P1 instead of flowing through the current path P2. Therefore, the timing signal SR1 that was flowing through the current path P2 as "1" in binary representation starts to become "0" in binary representation.

In this case, since the inductor L1 is inserted in the current path P2, the timing signal ST1 is 2
The state of "1" in the value display changes to the state of "0" in the binary display, and therefore, the timing signal ST1 is obtained as "0" in the binary display from time t25.

Therefore, according to the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. If the input signal SW2 is supplied to the input signal line W2 as "1" in binary display at the scheduled time, the load M1 will be changed based on this.
Alternatively, the timing signal ST1 can be supplied as "1" in binary format.

In addition, if the reset signal SR is supplied to the reset signal line R as "1" in binary display for the scheduled time from such a state, based on this, the load M1 will be changed to "1" in binary display for the scheduled time. The timing signal ST1, which was being supplied by
1 is no longer supplied in the state of "1" in binary display.

From the above, it can be seen that according to the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. in,
If the input signal SW1 is supplied to the input signal line W1 as "1" in the scheduled time binary representation, based on this, the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. As in the case of , the timing signals ST1 and ST2 can be sequentially supplied to the loads M1 and M2 as "1" in binary display, and the input signal SW2 can be supplied to the input signal line W2 at the scheduled time 2. If "1" is supplied in the value display, based on this, the timing signal ST1 can be supplied as "1" in the binary display only to the load M1.

Also, a state in which timing signals ST1 and ST2 are supplied as "1" in binary display to loads M1 and M2, respectively, or a state in which timing signal ST1 is supplied as "1" in binary display only to load M1. Therefore, if the reset signal SR is supplied to the reset signal line R as "1" in binary representation at the scheduled time, the timing signals ST1 and ST1, which were previously supplied as "1" in binary representation to loads M1 and M2, will be reduced.
"1" in binary display only for ST2 or load M1
The timing signal ST1, which was supplied at , becomes "0" in binary display.

Furthermore, after such a state is reached, the input signal is input to the input signal line W1 again as described above.
If SW1 is supplied as "1" in binary display for the scheduled time, the loads M1 and M2 will be
The timing signals ST1 and ST2 can be sequentially supplied as "1" in binary display to
If the input signal SW2 is supplied to the input signal line W2 again as "1" in binary display at the scheduled time, again,
As described above, the timing signal ST1 can be supplied as "1" in binary format only to the load M1.

The Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. 5 is similar to the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. It has the same characteristics as the case.

Next, an embodiment of the Josephson timing signal generation circuit according to the third invention of the present application will be described with reference to FIG.

In FIG. 7, parts corresponding to those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

The Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. 7 has the same configuration as the second invention of the present application shown in FIG. 5 except for the following matters.

That is, in the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. 7, in the Josephson timing signal generation circuit according to the second invention of the application shown in FIG. It has a configuration including a Josephson switch S6 having a Josephson junction element J, a bias current line B interposed therebetween, and a control line C, similar to S4.

Further, the Josephson timing signal generation circuit according to the third invention of the present application shown in FIG. 7 is different from the current path P3 in the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG.
is formed by including the Josephson junction element J of the Josephson switch S3, and the Josephson junction element J of the Josephson switch S3.
and the Josephson junction element J of the Josephson switch S6 are connected in series.

Furthermore, the Josephson timing signal generation circuit according to the third invention of the present application shown in FIG.
In the Josephson timing signal generation circuit according to the second invention of the present application shown in the figure, a current path P8 is formed including the control line C of the Josephson switch S6 described above, and the current path P8 is connected to the input signal line W3. It has a configuration in which it is inserted into.

The above is an example of the configuration of the Josephson timing signal generation circuit according to the third invention of the present application.

According to this configuration, it has the same configuration as the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. 5, except for the above-mentioned matters.

The Josephson switch S5 itself has the same function as the Josephson switch S tertiary body.

For this reason, regarding the Josephson timing signal generation circuit according to the first invention of the present application shown in FIG. Assuming that an input signal SW3 taking "1" and "0" is supplied, as long as the input signal SW2 is "1" in binary representation, the first application shown in FIG.
The Josephson timing signal generation circuit according to the third invention operates in exactly the same manner as described above.

Therefore, although detailed explanation is omitted, FIGS.
As can be seen with reference to the left half of FIG.
If you supply "1" in the scheduled time binary display,
Based on this, as in the case of the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. Load M2
The timing signal ST2 can be supplied as "1" in binary representation from a time later than the time when timing signal ST1 becomes "1" in binary representation.

In addition, in this way, both timing signals ST1 and ST2 are displayed as "1" in binary display for loads M1 and M2.
The reset signal line R
Then, if the reset signal SR is supplied as "1" in the scheduled time binary display, the load M1 is From the state where the timing signals ST1 and ST2 were being supplied to M2 and M2 in the state of "1" in binary display, the load M1
The timing signals ST1 and ST2 are in the state of "1" in binary display and are not supplied to M2.

In addition, the input signal SW2 is connected to the input signal line W2,
If the scheduled time is supplied as "1" in the binary display, based on this, as in the case of the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. , timing signal ST1
can be supplied.

However, according to the Josephson timing signal generation circuit according to the third invention of the present application shown in FIG. 7, the timing signal ST is applied to the loads M1 and M2.
1 and ST2 are respectively in the binary display state of "1" and are not being supplied, the input signal line W3
As shown in FIG. 8C, if the signal is supplied to "1" from time t31 to time t33, which takes "1" and "0" in the binary display, Josephson switch S6 is applied to current path P8. Since a current that takes a binary value of 1 flows through the control line C of ,
The current that has been flowing through current path P3 and which takes a binary value of 1 is now flowing through current path P4, as shown in Figure 6F, instead of flowing through current path P3.
As "1" in the binary display of timing signal ST2,
begins flowing through load M2. However, in this case, since the inductor L1 is inserted in the current path P4, the timing signal ST2 is
The state of "0" in the value display changes to the state of "1" in the binary display, and therefore, the timing signal ST2 is obtained as "1" in the binary display from time t33.

In this way, if the timing signal ST2 that takes "1" in the binary display flows in the current path P4, the current that takes "1" in the binary display does not flow in the current path P3, so Joseph After time t31, the Josephson junction element J of the switch S6 returns from the voltage-applied state to the zero-voltage state.

Furthermore, as mentioned above, the timing signal ST
2 is obtained as "1" in binary display from time t33, the reset signal SR is applied to the reset signal line R from time t34 after time t33 to time t36, as shown in the right half of FIG. 8D. If "1" is supplied in the binary display until then, a current that shows "1" in the binary display will flow through the current path P6 through the control line C of the Josephson switch S4. Josephson junction element J of son switch S4 at time t
34, the zero voltage state changes to the voltage state, and based on this, the current path P4 changes to "1" in the binary display, which had been flowing as the timing signal ST2 which took "1" in the binary display until now. The current starting to flow through current path P3 instead of flowing through current path P4.

Therefore, the timing signal SR2 is applied to the current path P4.
starts to change from "1" on the binary display to "0" on the binary display. In this case, since the inductor L1 is inserted in the current path P4,
The timing signal ST2 changes from the state of "1" in the binary display to the state of "0" in the binary display over time from time t34 to time t35, and therefore the timing signal ST2 changes to the state of "0" in the binary display. t35 to 2
Obtained as "0" in the value display.

Therefore, according to the Josephson timing signal generation circuit according to the third invention of the present application shown in FIG. If the input signal SW3 is supplied to the input signal line W3 as "1" in binary display at the scheduled time, then the load M2 will be
Additionally, the timing signal ST can also be supplied as "1" in binary format.

In addition, if the reset signal SR is supplied to the reset signal line R as "1" in binary display for the scheduled time from this state, based on this, the load M2 will be changed to "1" in binary display. The timing signal ST2, which was being supplied with
2 is displayed as a binary value and is no longer supplied in the state of "1".

From the above, according to the Josephson timing signal generation circuit according to the third invention of the present application shown in FIG. 7, the bias current is supplied to the power supply lines K1 and K2 as "1" in binary display. in,
If the input signal SW1 is supplied to the input signal line W1 as "1" in the scheduled time binary representation, based on this, the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. As in the case of , the timing signals ST1 and ST2 can be sequentially supplied to the loads M1 and M2 as "1" in binary display, and the input signal SW2 or SW3 can be supplied to the input signal line W2 or W3. If the scheduled time is supplied as "1" in binary display, the timing signal will be sent only to load M1 or M2 based on this.
ST1 can be supplied as "1" in binary display.

In addition, timing signals ST1 and ST2 are supplied as "1" in binary display to loads M1 and M2, respectively, or timing signal ST1 is supplied as "1" in binary display only to load M1 or M2. from the state where the control line is connected to the reset signal line R.
If SR is supplied as "1" in binary display for the scheduled time,
Timing signals ST1 and ST1, which were previously supplied to loads M1 and M2 as "1" in binary display, respectively.
Timing signal that was supplied as "1" in binary display only to ST2 or load M1 or M21
ST1 becomes "0" in binary display.

Furthermore, after such a state is reached, the input signal is again input to the input signal line W1 as described above.
If SW1 is supplied as "1" in binary display for the scheduled time, the loads M1 and M2 will be
The timing signals ST1 and ST2 can be sequentially supplied as "1" in binary display to
Again, input the input signal to the input signal line W2 or W3.
If SW2 is supplied as "1" in binary display for the scheduled time, the load M1 or M
2, the timing signal ST1 can be supplied as "1" in binary form.

The Josephson timing signal generation circuit according to the third invention of the present application shown in FIG. 7 is similar to the Josephson timing signal generation circuit according to the second invention of the present application shown in FIG. It has the same characteristics as the case.

[Brief explanation of drawings]

FIG. 1 is a connection diagram showing a conventional Josephson timing signal generation circuit. FIG. 2 is a signal waveform diagram for explaining the operation. Figure 3 shows
1 is a connection diagram showing an embodiment of a Josephson timing signal generation circuit according to the first invention of the present application; FIG. FIG. 4 is a signal waveform diagram for explaining the operation. FIG. 5 is a connection diagram showing an embodiment of the Josephson timing signal generation circuit according to the second invention of the present application. FIG. 6 is a signal waveform diagram for explaining the operation. FIG. 7 is a connection diagram showing an embodiment of the Josephson timing signal generation circuit according to the third aspect of the present invention, and FIG. 8 is a signal waveform diagram for explaining its operation. S1 to S3... Josephson switch, J...
Josefson junction element, B...bias current line,
C... Control line, L1, L2... Inductor, P1
~P7, P61~P62...Current path, H1~H6
...Series circuit, Q1, Q2...Parallel circuit, K1,
K2...power supply line, W1, W2...input signal line, R, R1, R2... Josephson junction element.

Claims (1)

[Claims] 1. It has a Josephson junction element, a bias current line through which the Josephson junction element is inserted, and a control line, and the bias current line has "1" and "0" in binary display. When the bias current to take is "1" and the control current is "1" and "0" in binary display on the above control line, it is supplied as "1" from the state where the control current is supplied as "0". first, second, and fourth Josephson switches, in which the Josephson junction element changes from a zero voltage state to a energized state when the Josephson junction element is turned on; a current line, and first and second control lines;
While the bias current that takes "1" and "0" in the value display is supplied at "1", the above-mentioned first and second control lines take "1" and "0" in the binary value display, respectively. a third Josephson switch in which the Josephson junction element changes from a zero voltage state to a voltage-applied state when both the first and second control currents are supplied at "1"; an inductor, a first current path is formed including the Josephson junction element of the first Josephson switch, and the Josephson junction element of the second Josephson switch and the first inductor. , and the second control line of the third Josephson switch are connected in series to form a first series circuit, and a second current path is formed including the first series circuit, The first and second current paths are connected in parallel to form a first parallel circuit, and the first parallel circuit is inserted into a power supply line, and the Josephson junction element of the third Josephson switch is connected to the first parallel circuit. a third current path is formed, the Josephson junction element of the fourth Josephson switch and the second inductor are connected in series to form a second series circuit; A fourth current path is formed including a series circuit, the third and fourth current paths are connected in parallel to form a second parallel circuit, and the second parallel circuit is inserted into the power supply line. and a control line of the first Josephson switch,
A third series circuit is formed by connecting the first control line of the third Josephson switch in series, and a fifth current path is formed including the third series circuit; 5 is inserted into the input signal line, and the control line of the second Josephson switch,
A fourth series circuit is formed by connecting the control line of the fourth Josephson switch in series, a sixth current path is formed including the fourth series circuit, and the sixth current path is connected in series with the control line of the fourth Josephson switch to form a fourth series circuit. A Josephson timing signal generation circuit characterized in that a reset signal line is inserted into the reset signal line. 2 It has a Josephson junction element, a bias current line that inserts the Josephson junction element, and a control line, and the bias current that takes "1" and "0" in binary display on the bias current line is "1". ”, and when the control current that takes “1” and “0” in the binary display on the control line is supplied from “0” to “1”, the Josephson first, second, fourth, and fifth Josephson switches whose junction elements switch from a zero voltage state to a voltage state; a Josephson junction element; and a bias current line through which the Josephson junction element is inserted; , first and second control lines, and the bias current line has two
While the bias current that takes "1" and "0" in the value display is supplied at "1", the above-mentioned first and second control lines take "1" and "0" in the binary value display, respectively. a third Josephson switch in which the Josephson junction element changes from a zero voltage state to a voltage-applied state when both the first and second control currents are supplied at "1"; an inductor, the Josephson junction element of the first Josephson switch and the Josephson junction element of the fifth Josephson switch are connected in series to form a fifth series circuit; A first current path is formed including a series circuit of 5 in series, the Josephson junction element of the second Josephson switch, the first inductor, and a second control of the third Josephson switch. A first series circuit is formed by connecting the lines in series, a second current path is formed including the first series circuit, and the first and second current paths are connected in parallel. a first parallel circuit is formed, the first parallel circuit is inserted into the power supply line, a third current path is formed including the Josephson junction element of the third Josephson switch, and a third current path is formed including the Josephson junction element of the third Josephson switch; The Josephson junction element of the Josephson switch and the second inductor are connected in series to form a second series circuit, and a fourth current path is formed including the second series circuit, The third and fourth current paths are connected in parallel to form a second parallel circuit, and the second parallel circuit is inserted into the power supply line and connected to the control line of the first Josephson switch. ,
A third series circuit is formed by connecting the first control line of the third Josephson switch in series, and a fifth current path is formed including the third series circuit; A seventh current path is inserted into the first input signal line, a seventh current path is formed including the control line of the fifth Josephson switch, and the seventh current path is connected to the second input signal line. a control line of the second Josephson switch inserted in the signal line;
A fourth series circuit is formed by connecting the control line of the fourth Josephson switch in series, a sixth current path is formed including the fourth series circuit, and the sixth current path is connected in series with the control line of the fourth Josephson switch to form a fourth series circuit. A Josephson timing signal generation circuit characterized in that a reset signal line is inserted into the reset signal line. 3 It has a Josephson junction element, a bias current line through which the Josephson junction element is inserted, and a control line, and the bias current that takes "1" and "0" in binary display on the bias current line is "1". ”, and when the control current that takes “1” and “0” in the binary display on the control line is supplied from “0” to “1”, the Josephson first, second, fourth, fifth, and sixth Josephson switches whose junction elements change from a zero voltage state to a voltage state; a Josephson junction element; and a bias interposed with the Josephson junction element. a current line, and first and second control lines;
While the bias current that takes "1" and "0" in the value display is supplied at "1", the above-mentioned first and second control lines take "1" and "0" in the binary value display, respectively. a third Josephson switch in which the Josephson junction element changes from a zero voltage state to a voltage-applied state when both the first and second control currents are supplied at "1"; an inductor, the Josephson junction element of the first Josephson switch and the Josephson junction element of the fifth Josephson switch are connected in series to form a fifth series circuit; A first current path is formed including a series circuit of 5 in series, the Josephson junction element of the second Josephson switch, the first inductor, and a second control of the third Josephson switch. A first series circuit is formed by connecting the lines in series, a second current path is formed including the first series circuit, and the first and second current paths are connected in parallel. A first parallel circuit is formed, and the first parallel circuit is inserted into a power supply line, and connects a Josephson junction element of the third Josephson switch and a Josephson junction element of the sixth Josephson switch. are connected in series to form a sixth series circuit, a third current path is formed including the sixth series circuit, and the Josephson junction element of the fourth Josephson switch and the second are connected in series with the inductor to form a second series circuit, a fourth current path is formed including the second series circuit, and the third and fourth current paths are connected in parallel. a second parallel circuit is formed, the second parallel circuit is inserted into a power supply line, and the control line of the first Josephson switch,
A third series circuit is formed by connecting the first control line of the third Josephson switch in series, and a fifth current path is formed including the third series circuit; A seventh current path is inserted into the first input signal line, a seventh current path is formed including the control line of the fifth Josephson switch, and the seventh current path is connected to the second input signal line. The eighth current path is inserted into the signal line and includes the control line of the sixth Josephson switch, and the eighth series circuit is inserted into the third input signal line. 2 Josephson switch control line,
A fourth series circuit is formed by connecting the control line of the fourth Josephson switch in series, a sixth current path is formed including the fourth series circuit, and the sixth current path is connected in series with the control line of the fourth Josephson switch to form a fourth series circuit. A Josephson timing signal generation circuit characterized in that a reset signal line is inserted into the reset signal line.