JPH0137778B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an information processing system having a plurality of central processing units and a dual memory, in which the plurality of central processing units can equally access the memory, and data in one memory can be transferred to the other memory. The present invention relates to a common memory contention control method that allows copying to memory to be performed without interfering with the processing of a central processing unit.

Conflict control methods for access requests to common memory include methods in which a time slot is allocated to each central processing unit and the central processing unit that has issued an access request is permitted access only in the corresponding time slot, or a method in which the central processing unit issuing the access request is allowed access only in the corresponding time slot, or in principle Conventionally, a method is known in which an access request generated at a time is accepted, and if there is a conflict of access requests, one access request is accepted according to a fixed priority order. However, in the former method, access by each central processing unit is made to wait until the allocated time slot arrives, so even if access requests do not overlap and there is no contention, the memory cannot be accessed immediately, and in effect The disadvantage is that the access time becomes longer. Furthermore, in the latter fixed priority system, there are always some access times with long access times and some with short access times.

Incidentally, an information processing system is known in which memory is duplicated, writing is performed to both memories, and reading is performed from the master side memory. In this type of information processing system, when a fault occurs in one memory, the faulty memory is isolated from the system, the faulty memory is repaired, and after the repair is completed, the data in the other memory is transferred to the other memory. Need to make a copy. Making the priorities variable makes it impossible to give a predetermined priority to memory access requests for data copying. If the memory access for data copying is high, a situation occurs in which the central processing unit's memory access request is made to wait, and the processing capacity of the system is reduced.

The present invention is based on the above invention, and includes:
To provide a contention control method for a common memory in which a central processing unit can access the memory equally and data can be copied without interfering with the processing of the central processing unit in an information processing system having dual memory. The purpose is to

Therefore, the common memory contention control method of the present invention is based on a plurality of central processing units 1-0 to 1-n and 2.
memories 3-0 and 3-1, memory controllers 2-0 and 2-1 each having a one-to-one correspondence with one memory, and each central processing unit 1-0 to 1-n and 2. A bus 4 provided between two memories 3-0 and 3-1, and two memory controllers 2-
0, 2-1, and the copy data is read from one memory by one memory controller, and the copy data is transferred to the other memory via the copy bus 5. In an information processing system having a dual memory where data is transferred to one controller and written to the other's memory, each memory controller 2-0, 2-1 has a memory access request in which multiple memory access requests compete in order of priority. An access request selection circuit 9 that selects one of them and a copy control circuit 10 that controls data copying are provided. One counter 22 whose numerical value is updated is provided, and the access request selection circuit 9 always gives the lowest priority to the memory access request from the copy control circuit 10, and the central processing unit 1-0 The memory access requests from 1 to 1-n are characterized in that they are given priorities that change according to the value of the counter 22.

FIGS. 1 to 3 explain an information processing system having a duplex memory to which the present invention is applied, in which FIG. 1 is a diagram showing an overview of the information processing system having a duplex memory, and FIG. A block diagram of one embodiment of the memory controller of FIG.
FIG. 3 is a diagram illustrating the flow of copy data in the information processing system of FIG. 1. In addition, FIGS. 4 to 7 are for explaining the present invention, and
FIG. 4 is a diagram showing an outline of one embodiment of the present invention, and FIG.
The figure shows the relationship between the value of the counter in Figure 4 and the priority order, Figure 6 is a block diagram of one embodiment of the main part of the present invention, and Figure 7 is a timing diagram explaining the operation of the device in Figure 6. It's a chat.

In Figures 1 to 3, 1-0 to 1
-n is the central processing unit, 2-0 and 2-1 are the memory
controller, 3-0 and 3-1 are memories, 4 is a common bus, 5 is a copy bus, 6-0 to 6-n are common bus control circuits, 7 is an error detection/correction circuit, 8
9 is a mode control circuit; 9 is an access request selection circuit;
10 is a copy control circuit, 11 is a memory control circuit, 1
2-0 to 12-n are signal buses, 13-0 to 13-n are access request signal lines, 14 is a bus,
15 to 19 are signal lines, 20 is a bus, 21-0
and 21-1 indicate memory buses, respectively.

In FIG. 1, central processing units 1-0 to 1
-n performs online processing using memories 3-0 and 3-1. For example, when the central processing unit 1-0 issues a write request, the same data is written to memories 3-0 and 3-1, and when it issues a read request, either memory 3-0 or 3-1 writes the same data. The data read from the CPU 1-0 is sent to the central processing unit 1-0. The selection from which memory data should be read depends on the state of the memory controllers 2-0 and 2-1 at that time. For example, memory
If the controller 2-0 is the master and the memory controller 2-1 is the slave, the memory controller 2-0 on the master side is selected. The states of the memory controllers, such as master and slave, are held in the mode control circuit 8. If an error is detected in the data read from memory 3-0 or 3-1, the master,
After replacing the slave, disconnect the faulty memory from the system and repair the faulty memory. Now, if a failure occurs in the memory 3-1, the central processing units 1-0 to 1-n will continue to use the normal memory 3-n even during the repair period of the memory 3-1.
0 to continue the original online processing.
When the repair of memory 3-1 is completed, memory 3-0
, and sends it to the memory 3-1 via the memory controller 2-0, the copy bus 5, and the memory controller 2-1.
Write to 1. The above data can be copied from memory 3-
This is done after confirming that 0 and 3-1 are not busy and that there is no access request from the central processing unit.

FIG. 2 is a block diagram of one embodiment of a memory controller. Note that memory controller 2
-0 and 2-1 have exactly the same configuration. Each of the common bus control circuits 6-0 to 6-n controls data transfer with the central processing unit. The error detection/correction circuit 7 not only detects and corrects errors, but also generates error correction codes. The mode control circuit 8 may be accessed by the central processing unit or copying data while being accessed by the central processing unit.
It stores the status of the memory controller, such as master or slave.
The access request selection circuit 9 performs a busy check and selects access requests according to priority. Access request selection circuit 9
can select a copy request on signal line 16 or 18 only if the memory is not busy and there are no access requests on signal lines 13-0 through 13-n. The copy control circuit 10 controls data copying, and when the system becomes a normal system (copy data sending side), it reads data from the memory and sends the read data, and performs the repair system (copy data receiving side). side), it receives data and writes the received data to memory. The memory control circuit 11 sends a write start signal, address information, and write data when writing memory, and sends a read start signal and address information, and receives read data when reading memory. .

When one of the central processing units 1-0 to 1-n sends out a memory access request, the access selection circuit 9 performs a busy check and selects the access request. When an access request is accepted, reading or writing to the memory is performed.

Data copying is performed as follows. Now, assuming that the contents of memory 3-0 are to be transferred to memory 3-1 as shown in Figure 3, the memory
A copy command is issued to controller 2-1. Upon receiving the copy command, the memory controller 2-1 enters the data copy mode. When the data copy mode is entered, a copy request is generated and sent to the memory controller 2-0 via the copy control circuit 10 and the copy bus 5. When the copy request is accepted by the memory controller 2-0, the copy control circuit 10 of the memory controller 2-0 reads one block of data from the memory 3-0. Note that the data is composed of pure data and an error correction code.
Copy control circuit 10 of memory controller 2-0
sends the read data to the memory controller 2-1 via the copy bus 5. The copy control circuit 10 of the memory controller 2-1 writes the received data to the memory 3-1. After this writing is completed, the same data is read from the memory 3-1, and the memory controller 2-1 detects an error.
It is checked by the correction circuit 7. At this time, when an uncorrectable error is detected, this is notified to the central processing unit by an interrupt.
By repeating the above process, memory 3-0
The entire contents of are copied to memory 3-1.

As described above, the access request selection circuit 9 gives the lowest priority to the copy request.
However, central processing units 1-0 to 1-n
It is desirable that each of them be able to access memory equally. The present invention meets these demands. 4 to 7 illustrate one embodiment of the present invention. In FIGS. 4 to 7, A to E are access request sources, 22 is a quaternary counter, and 23 is a priority order determination source. circuit, 24, priority encoder, 25 to 29;
indicates each gate. Access request sources A, B, C, and D are central processing units 1-0, 1-1,
1-2 and 1-3, and the access request source E corresponds to the data copy request source. In addition, a counter 22 and a priority determination circuit 23
exists in the access request selection circuit 9. As shown in FIG.
3 rotates the priorities of access request sources A, B, C, and D according to the contents of the quaternary counter 22, and always maintains the priority of access request source E at the lowest level. For example, when the value of the quaternary counter 22 is the numerical value "0", the highest ranking is given to the access request source A,
The priority is lowered in the order of B, C, D, and E. Furthermore, when the value of the quaternary counter 22 is the numerical value "3", the highest priority is given to the access request source D, and the priority is given lower in the order of A, B, C, and E.

FIG. 6 shows the priority determination circuit 23 of FIG. 4 in detail. In Figure 6, REQA,
B, C, D, and E are access request sources A and B, C, D, and E, respectively.
Access requests from B, C, D, and E.
CPC0 and CPC1 identify the selected access request, and CUAV is a signal indicating that the processing of the access request has been completed.

As shown in FIG. 7, when the content of the quaternary counter is "0", signals A, B, and C all become low level. Under this condition, gates 25, 2
The output states of 6 and 27 are signals *REQA and
Can be changed by *REQB and *REQC.

Under this state, the signal *REQA can be input to the input pin number 7 of the priority encoder 24, which has a high priority, and the input pins 6, 5, 4, 3, 2, 1, etc. Signal * in order of 0
REQB, *REQC, *REQD, *REQA, *
REQB, *REQC, *REQE can be input.
Under this state, for example, when *REQA and *REQB become low levels, the access request of access request source A is selected. Also, *REQA does not exist,
If *REQB, *REQC, *REQD, and *REQE exist, the access request of access request source B is selected.

When the content of the quaternary counter 22 becomes "1", the signal A goes high, the output of the gate 25 is fixed at a high level, and the input pin 7 of the priority encoder remains at a high level. The priority encoder ignores high level input signals. Signal B, C
remains at a low level, so gates 26 and 27
The output can be changed by the signals *REQB and *REQC, and the priority in this case is the order of access request sources B, C, D, A, and E, as shown in FIG. Under this condition, for example *REQB and *REQC
When the level becomes low, the access request of access request source B is selected. Under the same conditions, *
If only REQA is at a low level, the request of access request source A is selected.

When the content of the quaternary counter 22 becomes "2", the signals A and B go high and only the signal C remains low, so that only the output of the gate 27 can change. Then, the priority order is C, D, A, B,
The order is E.

When the content of the quaternary counter 22 becomes "3", all of the signals A, B, and C become high level, and the gate 2
The outputs of 5, 26, and 27 are all fixed at a high level state, so that the highest priority is given to the access request source D, and the priority is lowered in the order of A, B, C, and E thereafter. From now on, quaternary counter 2
The contents of 2 cycle through 0, 1, 2, and 3, but the priority of access request source E is always the lowest, and only the priority of access request sources A, B, C, and D is as shown in FIG. It circulates like this.

As is clear from the above description, according to the present invention, in an information processing system having dual memory, a rotating priority is assigned to time-limited memory access requests from the central processing unit. Processing can be done within the specified time,
Memory access requests for data copying with no time limit are always assigned the lowest priority and access is permitted only when there are no other memory access requests, so information processing systems with dual memory It is possible to meet the requests of each access source without degrading the processing of the access source.

[Brief explanation of drawings]

FIGS. 1 to 3 explain an information processing system having a duplex memory to which the present invention is applied, in which FIG. 1 is a diagram showing an overview of the information processing system having a duplex memory, and FIG. A block diagram of one embodiment of the memory controller of FIG.
FIG. 3 is a diagram illustrating the flow of copy data in the information processing system of FIG. 1. In addition, FIGS. 4 to 7 are for explaining the present invention, and
FIG. 4 is a diagram showing an outline of one embodiment of the present invention, and FIG.
The figure shows the relationship between the value of the counter in Figure 4 and the priority order, Figure 6 is a block diagram of one embodiment of the main part of the present invention, and Figure 7 is a timing diagram explaining the operation of the device in Figure 6. It's a chat. A to E... access request source, 22... quaternary counter, 23... priority determination circuit, 24...
Priority encoder, 25 to 29...gate.

Claims (1)

[Claims] 1. A plurality of central processing units 1-0 to 1-n,
Two memories 3-0, 3-1, memory controllers 2-0, 2-1 each having a one-to-one correspondence with one memory, and each central processing unit 1-0 to 1-n. A bus 4 provided between two memories 3-0 and 3-1 and two memory controllers 2
-0, 2-1, and the copy data is read from one memory by one memory controller, and the copy data is read from the other memory via the copy bus 5. - In an information processing system that has a dual memory that is transferred to one controller and written to the other memory, each memory controller 2-0, 2-1 has a system that follows the priority order when multiple memory access requests conflict. An access request selection circuit 9 that selects one of the access requests and a copy control circuit 10 that controls data copying are provided. One counter 22 whose count value is updated is provided, and the access request selection circuit 9 is always given the lowest priority to the memory access request from the copy control circuit 10, and the central processing unit 1- 1. A contention control system for a common memory, characterized in that memory access requests from 0 to 1-n are given priorities that vary according to the value of the counter 22.