JPH0139011Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an automatic black level correction circuit for a television receiver, and is intended to ensure that the black level of a reproduced image is always constant regardless of the broadcast content.

The black level of a television broadcast signal is set up within 5 to 10% of the difference between the pedestal level and the white level, but this standard is not necessarily strictly followed for each broadcast. Not yet. In other words, the setup values described above differ depending on each broadcast station, or even within the same broadcast station, depending on whether the video signal source is a VTR or a video camera. Currently, the level varies between 0 and 15%.

Such changes (variations) in the black level affect the floating of the reproduced image (the black shifts towards the gray side) and the sinking (the black level falls below the cut-off of the picture tube and the gradation on the black side cannot be reproduced). . In other words, even if the receiver is adjusted to provide the best contrast for a certain channel without any fluctuations,
When receiving other channels, a situation occurs in which the image becomes a black-out or black-out image.

Therefore, the present invention proposes an automatic black level correction circuit that eliminates such drawbacks, and the details thereof will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an automatic black level correction circuit according to the present invention. In the same figure, 1
1 is a reference pulse generating circuit, and this circuit is composed of circuits 2 to 8 which receive the composite video signal A and perform the operations described in each block. Further, 9 is an adder circuit for superimposing the reference pulse on the original composite video signal, and 10 is a DC clamp circuit for performing DC reproduction on the output signal.

The circuit of the present invention is generally configured as described above.
Next, the operation will be explained with reference to the waveforms of each part shown in FIG.

First, a composite video signal A obtained by detecting a television signal is inverted and amplified by a buffer amplifier circuit 2 to become a negative polarity signal B, and this signal is supplied to a video signal sampling circuit 3.

The video signal sampling circuit 3 obtains a sampling pulse D having a pulse width corresponding to the video signal period, and extracts only the video signal portion from the signal B. and,
This output signal is introduced into the black level hold circuit stage 4, and the black peak of the video signal portion is held.
At this time, the hold operation of the hold circuit 4 is set so that it is held over several to several tens of fields on the television screen.

A pedestal portion is also extracted from the output signal B of the buffer amplifier circuit 2 by a pedestal extraction circuit 5 which uses the burst gate pulse C generated within the receiver as an extraction pulse. This extracted pedestal portion is held by the next pedestal hold circuit 6, and this holding operation is also set to be held over several fields to several tens of fields as described above.

The outputs of the hold circuits 4 and 6 are introduced as two inputs to a level comparison circuit 7, and an output signal proportional to the level difference between the two inputs is derived from the comparison circuit 7 and sent to the next pulse conversion circuit 8. will be introduced in This circuit 8 derives a reference pulse E having a timing corresponding to the pedestal portion of the composite video signal A by extracting the output signal of the comparison circuit 7 using the burst gate pulse C. Therefore, the magnitude (pulse height) of this pulse E is proportional to the difference between the blackest level of the video signal and the pedestal level. That is, for example, if a black level with a setup of 0% (see _L1 in FIG. 2A) is held in the hold circuit 4 in a certain number of fields to several tens of fields, a low reference pulse height is generated. If a pulse (see E ₁ in Figure 2 E) is generated repeatedly every 1H and a black level of 20% setup (see L ₂ in Figure 2) is held, a reference pulse with a high pulse height is generated. (The same E
(see E ₂ ) will be generated in the same way.

Such a reference pulse E is introduced into the next adder circuit 9, and is superimposed on the pedestal portion of each corresponding 1H period of the original composite video signal A, which is separately introduced into this circuit, thereby becoming a signal F. This signal F is introduced into the next DC clamp circuit 10. This clamp circuit performs DC reproduction on the signal F so that the tips of each reference pulse E ₁ and E ₂ are fixed at a predetermined level L ₀ . At this time, the clamp level _L0 is set so that the black level _L1 of the video signal F at 0% setup matches the cut-off level of the picture tube. Therefore, in the composite video signal G derived from the clamp circuit 10, the blackest level always matches the cutoff level of the picture tube as shown in the figure, regardless of variations in setup at the broadcasting station. This solves the problem of fluctuations in black level.

Next, a description will be given of FIG. 3 showing a specific embodiment of the reference pulse generating circuit 1. In the circuit of FIG. 3, the same symbols are attached to corresponding parts to those in FIG. 1.

In FIG. 3, the buffer amplifier circuit 2 consists of a transistor _TR1 to which a composite video signal A is applied to the base from an input terminal _T1 via a coupling capacitor _C1 , and its output signal is connected to a high-pass capacitor _C2 . After high-frequency noise is removed, the signal is applied to the base of the transistor _TR2 constituting the black level hold circuit 4.

On the other hand, the video signal sampling circuit 3 includes a switching transistor TR ₈ connected between the base of the transistor TR ₂ and the ground, and a circuit 3' that supplies the following three switching pulses to the base of this TR ₈ . ing. First, the first switching pulse converts the horizontal flyback pulse H introduced into one input terminal _T2 of the circuit 3' into _C7 ,
This is a positive pulse with a pulse width corresponding to the horizontal blanking period created by shaping with R ₁₄ and R ₂₀ and slicing with D ₁ . The second switching pulse is created by slightly delaying the pulse part of the vertical output voltage I introduced into the other input terminal _T3 of the circuit 3' with _R22 and _C8 , and then slicing it with _D2. This is a positive pulse with a pulse width that includes a vertical synchronization signal period, a subsequent equivalent pulse period, and a subsequent 20H blanking period. Further, the third switching pulse is a positive pulse generated by TR ₇ which is turned on at the end of the scanning period of the vertical output voltage r and has a pulse width corresponding to the equivalent pulse period before the vertical synchronization signal. It is. . That is, instead of directly extracting the video signal part by the sampling pulse D in FIG. 2, the video signal sampling circuit 3 converts the output signal of the buffer amplification transistor _TR1 into the first to third switching pulses. Therefore, the ground fault is caused only during the horizontal and vertical braking periods.

The black level hold circuit 4 is an emitter follower.
It is configured as a peak hold circuit using the current amplification factor of TR ₂ and a capacitor C ₃ , and its output signal is applied to the base of one transistor TR ₄ of the differential pair forming the level comparison circuit 7. It's summery. Note that the emitter resistor R ₆ operates to discharge the capacitor C ₃ mentioned above, and this C ₃ ,
As mentioned above, the discharge time constant due to _R6 is selected to be a time corresponding to several fields to several tens of fields.

Next, the pedestal extracting circuit 5 includes a switching transistor TR10 connected between the base of a transistor TR3 to which the collector output signal of the buffer amplifying transistor _TR1 is applied via a resistor _R13 and the ground, and a switching transistor _TR10 connected between the base of the transistor _TR3 and the ground. The main element is a transistor TR ₉ for inverting the polarity of the burst gate pulse C of positive polarity introduced into the terminal T ₄ to supply a sampling pulse of negative polarity to the base of the transistor TR ₁₀ .
That is, the switching transistor _TR10 is turned off only during the burst gate pulse period, and leads the composite video signal from the buffer amplification transistor _TR1 to the base of the transistor _TR3 . Note that the aforementioned resistor _R13 and the resistor _R5 in the black level hold circuit 4 are selected to have the same resistance value, so that no level error occurs during the sampling operation.

Further, the pedestal hold circuit 6 is configured as a peak hold circuit consisting of the emitter follower type transistor TR ₃ and the capacitor C ₄ like the black peak hold circuit, and its output signal is transmitted to the other transistor TR ₅ of the differential pair. is applied to the base of the Note that the emitter resistance R ₁₄ of this circuit is also selected to have the same value as R ₆ in the black peak hold circuit 4 described above.

The differential pair transistors TR ₄ and TR ₅ constituting the level comparison circuit 7 perform linear operation until the black peak applied here reaches a set-up of 20%, and performs a switching operation when the set-up exceeds 20% (that is, TR ₄ is off and TR ₅ is on)
The values of R ₁₀ and R ₁₁ are set. Therefore, up to the black peak of 20% setup, an output voltage that decreases in proportion to the difference between the black peak, that is, the blackest level, and the pedestal level is taken out from the collector of TR ₅ of the differential pair. For black peaks with a set-up of 20% or more, the output voltage is fixed to the value when the set-up is 20%. At that time, the base of the constant current transistor TR ₆ of the above differential pair is
Since the aforementioned negative burst gate pulse is applied via D ₃ , this differential pair becomes inactive (that is, both TR ₄ and TR ₅ are off) during the burst pulse period, and therefore, as a result, TR ₄ The collector has a magnitude proportional to the difference between the blackest level and the pedestal level, and its tip is clamped to the power supply voltage Vcc, and the amplitude varies from 1/2 IOR ₉ (when the blackest level and pedestal level are equal) to IOR ₉ (the blackest level). When the level is 20%, a reference pulse E is derived which varies up to (Io is the collector current of the transistor _TR6 ). And this pulse connects the coupling capacitor C ₆
This leads to the adder circuit 10 in FIG. That is, in this embodiment, the pulse conversion circuit 8 is constituted by the constant current transistor _TR6 .

As explained above, according to the present invention, a reference pulse proportional to the difference between the blackest level and the pedestal level in the composite video signal is created and superimposed on the original composite video signal, and the reference pulse in the composite video signal is Since DC reproduction is performed so that the leading edge of the alignment pulse is clamped at a constant level, the black level of the video signal can always be set to a constant level regardless of variations in the setup at the broadcasting station, and therefore the reproduced video The best contrast can always be achieved without phenomena such as floating blacks or sinking blacks.

In addition, when creating a reference pulse, the circuits that hold the blackest level and the pedestal level are both configured as peak hold circuits that utilize the current amplification factor of the transistor.
Moreover, since the circuit that receives the outputs of both hold circuits and creates a reference pulse is configured using a differential pair transistor and its constant current transistor, it can be realized at a relatively simple circuit configuration and at low cost. There is also an advantage.

[Brief explanation of the drawing]

The drawings all relate to the automatic black level correction circuit of the present invention, and FIG. 1 is a block diagram showing its schematic configuration;
FIG. 2 is a signal waveform diagram of each part, and FIG. 3 is a circuit diagram showing one embodiment of the reference pulse generating circuit. 4...Black level hold circuit (black level hold means), 6...Pedestal hold circuit (pedestal hold means), 7, 8...Comparison circuit,
Pulse conversion circuit (reference pulse creation means),
9...Addition circuit (superimposition means), 10...DC clamp circuit (DC clamp means), 1...Reference pulse generation circuit, _TR2 , _TR3 ...Emitter follower transistor, _TR4 , _TR5 ... ...Differential pair transistor, TR ₆ ... Constant current transistor.

Claims (1)

[Claims for Utility Model Registration] (1) Black level holding means 4 for holding a black peak level value in a composite video signal; pedestal holding means 6 for holding a pedestal level in the composite video signal; and the black level. Reference pulse creation means 7 and 8 obtain the output of the hold means 4 and the output of the pedestal hold means 6 and create a reference pulse of a level corresponding to the level difference between these two outputs.
a superimposing means 9 for applying this reference pulse to the pedestal portion of the composite video signal; An automatic black level correction circuit for a television receiver, comprising: DC clamp means 10 for regeneration; and an automatic black level correction circuit for a television receiver. (2) The video signal part and pedestal part extracted from the composite video signal are respectively supplied to the bases of two emitter-whistle transistors whose emitters are connected to hold capacitors, and the output signal obtained at each emitter of both transistors is obtained. is applied to each base of the differential pair transistors, and a gate pulse is applied to the base of the constant current transistor of this differential pair, so that the reference pulse is taken out from the collector of one of the differential pair transistors. An automatic black level correction circuit according to claim 1.