JPH0139251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an integrating AD converter for converting analog voltage to digital data with high precision.

Prior art and its problems Double-integration type AD converters are widely used as AD converters that perform AD conversion at relatively low speed and with high precision. A double integration type AD converter uses an integrator to integrate the input voltage for a predetermined period of time, and then starts integration using a reference power supply with the opposite polarity to the input voltage. AD conversion is performed by opening the gate circuit for a certain period of time and counting the number of pulses of the clock signal during the integration period during that period. In this double integration type AD converter, the input signal and reference voltage are integrated by an integrator using the same capacitor, so as long as the values of the integration capacitor and input resistance are stable, it will not affect conversion accuracy. Furthermore, if the integration time of the input voltage is obtained by frequency-dividing the clock signal, the frequency of the clock signal itself does not affect the measurement accuracy. Further, by selecting the input voltage integration time to be an integer multiple of the power supply period, normal mode noise can be effectively removed, which is why it is widely used. However, in the case of such a double integration type AD converter, there is a problem in that measurement errors due to the offset of the integrator cannot be eliminated. Therefore, several methods have been proposed to eliminate this error, and these can be classified into analog methods and digital methods.

FIG. 1 is a circuit diagram showing the basic configuration of a double-integration AD converter equipped with an auto-zero circuit that reduces offset errors using an analog system. In this figure, analog switches S1 and S2
and S3 are for switching the inverting input given to the integrator 4 to the input voltage Vi, the reference voltage source 5 having the reference voltage Vref, and the ground side, respectively. connected to the inverting input terminal of An integrating capacitor C7 is connected between the input and output terminals of the integrator 4, and its non-inverting input terminal is grounded via a capacitor C8. The output of the integrator 4 is applied to a comparator 9, and the output of the comparator 9 is applied to the non-inverting input terminal of the integrator 4 via an analog switch S10.
The signal is applied to the control logic circuit 11. The control logic circuit 11 controls these switches S1, S2, S3 and S10, and
A gate signal is formed based on the output of the comparator 9 and is provided to the counter 12. The counter 12 counts the clock signal, and its output is given to the latch circuit 13 as an AD converted signal. As shown in the waveform diagram of each part in FIG. 2, this AD converter switches S3 and S10 at time t0 in the initial state.
Turn on. In this way, the output of the comparator 9 is connected to the non-inverting input terminal of the integrator 4, so the whole becomes a buffer amplifier with an amplification factor of 1.The input impedance of the integrator 4 is extremely high, and the input resistance R
Only a very small current, about the same as the input bias current of an operational amplifier, flows through the input terminal 6, and since one end thereof is grounded by the switch S3, the input terminal is also at zero volts. On the other hand, if the offset voltage of the operational amplifier of the integrator 4 is Vos, the voltage at the non-inverting input terminal is charged to the correction capacitor C8 by the output of the comparator 9, and becomes -Vos after a certain period of time. Next, at time t1, the switch S1 is closed and the input voltage Vi is integrated for a certain period of time by the integrator 4, as in a normal double-integration AD converter. Then, Figure 2 a
As shown by the solid line in , the output of integrator 4 is equal to the input voltage.
The control logic 11 closes the switch S1 and opens the switch S2 at time t2 after a predetermined period of time has elapsed. Then, the reference voltage source 5 of the reference voltage Vref having the opposite polarity to the input voltage Vi is connected to the inverting input terminal of the integrator 4, so that the output of the integrator 4 has a slope in the opposite direction corresponding to the reference voltage Vref. Then, at time t3 when the voltage rises and reaches a predetermined level, the comparator 9 outputs an output and provides a signal to the control logic circuit 11. The time from time t2 to time t3 is measured by the counter 12, and the count value at the end of the measurement is held by the latch circuit 13 as an AD conversion value. In such an auto-zero double integration circuit, the voltage applied to the non-inverting input terminal when integrating the input voltage is higher than the voltage of the correction capacitor C8.
Since only Vos is high, the offset of the integrator has been canceled. In this way, the offset voltage is temporarily held in the correction capacitor C8 during one AD conversion cycle, and when integrating the input voltage, the integration is performed with the offset voltage canceled, making it possible to eliminate the input offset. Become. However, since the offset voltage is held by a capacitor in an analog way, there is a droop peculiar to the hold circuit, and the offset voltage of capacitor C8 gradually discharges, making it impossible to maintain the voltage at the inverting input terminal at completely zero volts. The drawback was that it was difficult. In addition, as shown in Figure 2a, if there is spike noise during input voltage integration, such as when switching a switch, the integral value will differ as shown by the broken line, and the spike noise will directly become an error in the output of the integrator. appear. Errors caused by such spike noise can be eliminated by analog double integration AD.
There was a problem in that it could not be removed using a converter.

On the other hand, an AD converter has also been proposed in which the offset error is reduced using a digital method in order to eliminate the error caused by the offset of the integrator. FIG. 3 is a circuit diagram showing an example of such an AD converter. In this figure, the same parts as in FIG. 1 are given the same reference numerals. In this AD converter, the reference voltage sources are configured as two reference voltage sources 5a and 5b connected in series, each having a voltage of 1/2 Vref, the midpoint of which is connected to the non-inverting input terminal of the integrator 4. Connected. Also provided is a switch S155 for shorting the capacitor C7 of the integrator 4, which is controlled by the control logic circuit 16. Further, the output of the comparator 9 is given only to the control logic circuit 16. In the integrating AD converter having such a configuration, during operation, the switch S15 that short-circuits the capacitor C7 of the integrator 4 is first turned on. Then, at the same time as the charge stored in the capacitor C7 is discharged, the integrator 4 becomes a buffer amplifier, and its output voltage becomes almost equal to the voltage 1/2Vref of the reference voltage source 5b connected to the non-inverting input terminal. .
Then, when the switch S2 is turned on at time t4, the reference voltage source 5a is connected to the inverting input terminal of the integrator 4.
5b total voltage Vref is given,
The output of the integrator 4 drops to the comparator belt of the comparator 9, and at time t5 when the comparator 9 outputs an output, the control logic circuit 16 turns on the switch S3 to turn on the integrator 4. Ground the inverting input terminal. Then, the reference voltage 1/2 Vref of the non-inverting input terminal including the offset and the value of the offset voltage Vos are given to the integrator 4, and the voltage is integrated. This integration time is defined as a constant time KT seconds,
At time t6 after KT seconds, the discharge cycle begins. In this discharge cycle, switch S2 is turned on, reference voltage Vref is connected to the inverting input terminal of integrator 4, and integration is performed in the reverse direction until time t7 when the comparator 9 reaches the comparison level. Then, if there is no offset voltage Vos, the phase from time t5 to t6
PH1 and the phase PH2 from t6 to t7 are the same, but if there is an offset as shown by the broken line in FIG. 4a, time t7 becomes a long integration time shifted by nT. Here, the integrator output at phase PH1 is ΔV ₁ = KT/CR (Vref/2+Vos) ...(1), and the integrator output at PH2 is ΔV' ₁ = (K+n ₎ T/CR (Vref /2−Vos)=−ΔV ₁ ...(2). From these equations, n=2K/Vref/2Vos-1...(3) Vos=Vref/2・n/2K+n...(4) can be obtained. Now, at time t7, when the output of the comparator 9 is inverted, the switch S1 is turned on and the input voltage Vi is integrated. The end time of this integration is set at 3KT from time t6, and the phase PH3
The integration time of the input voltage Vi at varies depending on the time of phase PH2, that is, the offset voltage (2K
-n) becomes T. Then, at time t8, switch S2
is turned on, the integrator 4 integrates in the opposite direction, and the capacitor C7 is discharged. Then, as shown in Figure 4a, integration is performed until the comparator level of comparator 7 is reached, and the integration time at this time is
Set it to PH4. Here, the integral value ΔV ₂ at phase PH3 has an integration time of (2K-n)T, so ΔV ₂ =-(2K-n)T/CR・(-Vref/2+Vi-Vos)...(5) Yes, the integration time in PH4 is (2K+n+N), where n is the count difference due to offset, and the output of integrator 4 is ΔV' ₂ =-(2K+n+N)T/CR(Vref/2-Vos)...(6) becomes. Therefore, when Vos is eliminated from equations (3), (5), and (6) and expressed in terms of N, N=-Vi/VrefK[1-(n/2K) ² ]-n ² /K ₁ ...( 7) Therefore, as shown in FIG. 4g, the time of phase PH4 is counted by the input clock output by the totalizing counter 17, and the counted value is held in the latch circuit 18 to obtain the AD conversion value.

In this quadruple integration method, offset errors are digitally processed as count differences n, and scaling errors based on the integrator gain (n/
2K) ² has decreased significantly. However, the offset error that remains when the input voltage Vi is zero
n ² /K still exists, and the error cannot be completely reduced. In addition, this quadruple integration type AD converter uses two accurate reference voltage sources Vref and 1/
There are practical problems in that 2Vref is required, errors are likely to occur, and adjustment is difficult. Furthermore, since the integration time of the input voltage Vi varies depending on the input offset voltage, there is a drawback that the integration time cannot be accurately fixed to an integral multiple of the cycle of the power supply frequency, resulting in an error caused by the power supply. Furthermore, since the integration time between phase PH1 and the integration time between phase PH3 shown in Fig. 4 are different, there is a problem that the count difference n due to the offset in phase PH1 is not accurately reflected in phase PH3. .

Furthermore, these conventional AD converters are both AD
There was a problem in that it was impossible to correct offset errors and scaling errors of the preamplifier placed upstream of the converter.

Purpose of the Invention The present invention solves the problems of the conventional integral type AD converter, and corrects the offset error and scaling error including the preamplifier, thereby achieving stable AD converter with high accuracy. The present invention provides an AD converter capable of performing conversion.

Structure and Effects of the Invention The first invention of the present application includes an integrator that includes an integrating capacitor and integrates an input signal, and an integrator that switches the input to the integrator to a voltage signal to be measured and a reference voltage source having a constant reference voltage Vref, respectively. 1. A second switch, a comparator that compares the output voltage of the integrator with a predetermined level and stops discharging the integrating capacitor of the integrator when it reaches the predetermined level, and a counter that counts the discharge time of the reference voltage source. and an integral type with
a third switch which is an AD converter and switches the input of the integrator to the ground side by a control input; a clock signal generator having a constant clock period T;
Close the third switch for a time KT that is an integral multiple of the clock period T of the clock signal generator, ground the input end of the integrator, and integrate the input offset voltage.
After that, the second switch is closed and the reference voltage Vref is
At the same time, the discharge time is set as the first gate signal, the first switch is closed for the same time as the offset voltage integration time (KT), and the voltage to be measured is applied to the integrator.
A control means for closing a switch to cause discharge by a reference voltage Vref and using the discharge time as a second gate signal, and controlling the number of clock pulses of the clock signal generator by the first and second gate signals obtained from the control means. and a counting means that calculates the counted values n ₀ and N, respectively, and calculates the following formula Vin=-Vref/K+n ₀ (N-n) using the counted values of the counting means, and sets Vin as the AD conversion value. means. Further, the second invention of the present application is an AD converter having a preamplifier that amplifies the input voltage with an amplification factor A, and in addition to the first invention, there is a fourth invention in which the input of the integrator is switched to the ground side by a control input. The third switch is closed for a time KT that is an integral multiple of the clock period T of the clock signal generator, the input end of the integrator is grounded, and the input offset voltage is integrated. is closed and discharged by the reference voltage Vref,
The discharge time is used as the first gate signal, the fourth switch is closed for the same time as the offset voltage integration time (KT), the input terminal of the preamplifier is grounded, the input offset voltage is integrated, and then The second switch is closed to discharge the reference voltage Vref, the discharge time is used as the second gate signal, and the first switch is closed for the same time as the offset voltage integration time (KT). A control means applies a measured voltage to an integrator, then closes a second switch to cause discharge by a reference voltage Vref, and uses the discharge time as a third gate signal, and first and second gate signals obtained by the control means. , a counting means that counts the number of clock pulses of the clock signal generator by a third gate signal to obtain counted values n ₀ , n ₁ , and N, respectively, and the following equation Vin=-Vref/A(K+n ₀ )(N-n ₁ ) and uses Vin as an AD conversion value.

According to the first invention of the present application having such characteristics, it is possible to obtain a correct AD conversion value without the influence of offset voltage based on the above-mentioned formula. Furthermore, since the integration time of the integrator offset AD conversion cycle and the input voltage AD conversion cycle are the same, the effects of spike noise generated during integration and leakage current of the integrator 4 are the same. Furthermore, if the circuit constants, spike noise, droop, etc. are stable during these two AD conversions, the errors associated with these will be canceled out, making it possible to completely eliminate their influence. Furthermore, by selecting the integration time to be an integral multiple of the period of the power supply frequency, it is also possible to reduce periodic noise caused by the power supply. Furthermore, according to the second invention of the present application, even if a preamplifier is provided before the integrator, the overall error including the offset voltage of the amplifier can be corrected, so that accurate AD conversion values can be obtained. It becomes possible to obtain.

DESCRIPTION OF EMBODIMENTS FIG. 5 is a circuit diagram showing an embodiment of an AD converter according to the first invention of the present application. This embodiment shows an AD converter in which no preamplifier is added before the integrator, and the same parts as in the conventional example shown in FIGS. 1 and 3 are denoted by the same reference numerals. This AD converter is similar to the conventional example shown in FIG.
It has switches S1, S2, and S3, which are the switches of the following. The switches S1 to S3 are analog switches that are opened and closed by control input. The input signal of the integrator 4 is selected by these switches and applied to the inverting input terminal of the integrator 4 via the input resistor R6, and the reference signal having a constant voltage Vp is applied to the non-inverting input terminal of the integrator 4. Power source 20 is connected. This AD converter is also provided with a switch S15 that initializes the integrator by shorting both ends of the integrating capacitor C7, and the output of the integrator 4 is given to the comparator 9. The comparator 9 compares the output of the integrator 4 with a predetermined threshold level and outputs an output when they match, and the output is sent to the control logic circuit 21.
is applied to stop the discharging of the integrating capacitor C7 of the integrator 4. The control logic circuit 21 is a control means for controlling each switch S1, S2, S3, and S15 in predetermined processing steps, as will be described later, and forms a gate signal based on the output of the comparator 9 and outputs the gate signal to the counter 22.
give to A clock generator 23 is connected to the control logic circuit 21 and the counter 22, which generates a clock signal with a constant period T (seconds). The counter 22 counts the number of clocks while the gate is open based on the clock signal from the clock generator 23, and the counted value is once held in the latch circuit 24 and then sent to the arithmetic processing unit 25. Given. Here, the counter 22 and the latch circuit 23 constitute a counting means for counting the number of pulses obtained from the control logic circuit 21. The arithmetic processing unit 25 is an arithmetic means that outputs a correct AD conversion value by a predetermined process to be described later based on the count value of the counter 22, and is
and a storage means for storing a processing program.

Next, the operation of this AD converter will be explained with reference to the waveform diagram in FIG. First, at time t11, switch S15 is turned on to short-circuit both ends of integrating capacitor C6 of integrator 4. Then, the integrating capacitor C6 is discharged and the output of the integrator 4 becomes a value determined by the voltage Vp applied to the non-inverting input terminal. Subsequently, at time t12, the switch S2 is closed under control from the control logic circuit 21. Then, the reference voltage Vref is applied to the integrator 4 via the input resistor R6, and the output voltage of the integrator 4 drops at a slope corresponding to the reference voltage as shown in FIG. reach the level. After completing the initialization cycle of the integrator 4, the comparator 9 provides an output to the control logic circuit 21. Then, the switch S3 is turned on and one end of the input resistor R6 is grounded. Therefore, after time t13, as shown in FIG. 6a, integration is started by the voltage Vs that is the sum of the offset voltage Vos of the integrator 4 and the voltage Vp of the bias power supply connected to the non-inverting input terminal of the integrator 4. The integration time is assumed to be KT (K is a constant positive integer). And the integration time KT (seconds) of this phase PH11
At time t14, when , the switch S2 is turned on again as shown in FIG. 6d, and the reference voltage Vref is connected to the inverting input terminal of the integrator 4. Then, the output of the integrator 4 falls at a predetermined slope as shown in FIG. 6a, and the integrating capacitor C7 is discharged. The control logic circuit 21 applies the first gate signal during this period to the counter 22, and the counter 22 counts the number of clock pulses of the clock generator 23 as shown in FIG. 6g. Then, at time t15 when the output of the integrator 4 reaches the comparison level of the comparator 9, this counting is stopped based on the output of the comparator 9, and the switch S2 is turned off and the switch S15 is turned on, so that the integrating capacitor C
Short-circuit both ends of 6. At this time, time t14
Assuming that the count value of the counter 22 obtained during the phase PH12 from t15 is _n0 , that value is temporarily held in the latch circuit 24. Then, at time t16 after a predetermined period of time has elapsed, the switch S2 is turned on to enter an integrator initialization cycle in which the integrator 4 is initialized. The integrator initialization cycle from time t15 to t17 is the same as the integrator initialization cycle from time t11 to t13 described above.
If it is not necessary to strictly perform the conversion, there is no need to insert it, and the next cycle can be started from time t15. In this embodiment, at time t17 when the initialization cycle ends, the switch S1 is turned on, and the input voltage Vi is applied to the inverting input terminal of the integrator 4 for integration. Then, as shown in FIG. 6a, the output of the integrator 4 rises with a slope corresponding to the input voltage Vi.
The integration time of this phase PH13 is from time t13 to t14.
Assuming that KT (seconds) is the same as the integral time of phase PH11 as shown in FIG. 6a, at time t18 when this time has elapsed, switch S2 is turned on and the discharge cycle begins. Then, from time t18 when the discharge cycle starts, the second gate signal is again applied to the counter 22 to cause the clock generator 23 to count the number of clock pulses. Then, at time t19 when the output of the integrator 4 reaches a predetermined comparator level, this counting is stopped by the output of the comparator 9, and the counted value is held in the latch circuit 24. Here time t
Let N be the count data obtained during phase PH14 from 18 to t19. Then, the arithmetic processing unit 25 calculates a correct AD conversion value by removing the influence of the offset of the integrator 4 through the next calculation. That is, the voltage of the integrator 4 at time t14 when the phase PH11 from time t13 to t14 ends is ΔV01, and time t
If the output voltage of the integrator 4 at time t14 is used as a reference and the voltage of the integrator 4 at time t15 is -ΔV02, these voltages are expressed by the following equations (11) and (12), respectively.

ΔV01=-KT/CR(Vs-0)...(11) -ΔV02=-n ₀ T/CR(Vref-Vs)...(12) And the potential difference is the same as shown in Figure 6a. Therefore, ΔV01 is equal to −ΔV02, and Equations (11) and (12)
From this, the following equation (13) is derived.

Vs=n ₀ Vref/K+n ₀ ...(13) On the other hand, the voltage of the integrator 4 at time t18 when the phase PH13 that integrates the input voltage from time t17 to t18 ends is ΔVoi, and time t is set from time t18 as a reference.
When the output voltage of the integrator 4 after completion of integration using the reference voltage Vref of 19 is -ΔVor, these voltages are expressed by the following equations (14) and (15), respectively.

ΔVoi=−KT/CR(Vs−Vin) ……(14) −ΔVor=−NT/CR(Vref−Vs) ……(15) In this case as well, since the respective potential differences are the same, Equation (14), ( 15), N is expressed by the following equation (16).

N=Vs-Vin/Vref-Vs (16) Then, by substituting the value of offset voltage Vs in equation (13) into equation (16), the following equation (17) is derived.

Vin=-Vref/K+ _n0 (N _{- n0} )...(17) In this way, equation (17) is expressed as Therefore, by keeping these values at predetermined values, a correct AD conversion value Vin that is not affected by the offset voltage Vs can be provided. Also, since the integration times of phases PH11 and PH13 are KT seconds and the same, the influence of spike noise caused by integration during the integration of the integrator offset AD conversion cycle (PH11) and the input voltage AD conversion cycle (PH13). , the influence of the leakage current of the integrator 4, etc. are the same, and it is possible to eliminate these regardless of the magnitude of the error. Also, if the circuit constants, i.e., resistance values, capacitor values, clock frequency period T, spike noise, droop, etc. are stable during these two AD conversions, these errors will be canceled out. It can be completely removed. Furthermore, the integration time KT
By selecting (seconds) to be an integral multiple of the period of the power supply frequency, it is also possible to suppress periodic noise caused by the power supply to a very low level.

FIG. 7 is a circuit diagram showing an embodiment of the second invention of the present application. In the present invention, when a preamplifier is provided before the integrator 4 of an AD converter, correction is made including the offset of the preamplifier to ensure correct AD.
I am trying to get the converted value. In this embodiment, the same parts as in the embodiment of FIG. 5 will be described using the same reference numerals. In this figure, the AD converter 30 is an amplifier with an amplification factor of A, and at its input terminal there are switches S31 and S31 that switch the input to the input voltage Vi and the ground side.
32 are connected. The amplified output terminal of the preamplifier 30 is then connected to the switch S33. The input resistor R6 of the integrator 4 has switches S33, S34, and S35 for switching the integral input to the output voltage of the preamplifier 30, a reference power supply 5 having a reference voltage Vref, and the ground side, respectively, as in the embodiment described above. provided. Here, switch 31 constitutes a first switch, and switches 34, 35, and 32 constitute second, third, and fourth switches, respectively. The configuration of the integrator 4 and below is almost the same as that of the embodiment shown in FIG.
5 is controlled by a control logic circuit 36 as described later, and the obtained data is operated by an arithmetic processing unit 37 and converted into a correct AD conversion value.

FIG. 8 is a block diagram showing details of the control logic circuit 36 and the arithmetic processing unit. The control logic circuit 36 is as shown in the figure.
It has a counter 40 that stores each phase of AD conversion, and the counting output of the counter 40 is given to a decoder 41. The decoder 41 decodes the count output and provides the output to the gate circuit 42. The gate circuit 42 includes each switch S31 to S35 and S15.
It generates a signal for driving the counter 43, and also provides a reset signal to the counter 43. counter 43
is a K-ary counter for performing integration over a fixed time (KT), and is supplied with a clock signal from a clock generator 23, and its overflow output is supplied to the counter 40 via an OR circuit 44. The counter 40 is a counter whose count value is incremented as the phase advances, and receives a system reset pulse from the arithmetic processing unit 37 and detects the AD conversion start pulse and the rising edge of the comparator 9 at its input terminal. Output of edge detection circuit 45 and K-ary counter 43
The overflow output of is applied to the counter 40 through an OR circuit 44 as a counting input signal. Further, the output of the decoder 41 is applied via the gate circuit 42 to the counter 22 and latch circuit 24 described above as a reset signal and a clock signal. The output of latch circuit 24 is applied to input port 50 of arithmetic processing unit 37. The arithmetic processing unit 37 connects to a central processing unit (hereinafter referred to as
Read-only memory (hereinafter referred to as ROM) 5 that stores system programs in CPU (hereinafter referred to as CPU) 52
3 and a storage means consisting of a random access memory (hereinafter referred to as RAM) 54 that holds count data of the counter 22 and temporary data of calculations, and an output port that transmits the output from this calculation processing unit 37 to an external circuit. 55 are provided.
Output port 55 is connected to control logic circuit 36
It provides a system reset pulse to the counter 40 and an AD conversion start pulse to the OR circuit 44.

Next, the operation of this embodiment will be explained with reference to the waveform diagram of FIG. 9. First, at time t20
The CPU 52 outputs a system reset pulse from the output port 55, turns on the switch S15 via the gate circuit 42, and short-circuits both ends of the integrating capacitor C7. Then, the switch S34 is closed to apply the reference power Verf to the integrator 4, and the integrator initialization cycle is completed by integrating up to the comparator level of the comparator 9 in the same manner as in the embodiment described above. Next, at time t21, the CPU 52 advances to phase PH15, outputs the AD conversion start pulse, and switches the switch S.
35 is closed and the inverting input terminal of the integrator 4 is grounded. At the same time, the K-ary counter 43 starts counting the clocks, and after integrating for the time KT (seconds) as in the above-mentioned embodiment, the counter 4
Increment 0. Then proceed to phase PH16,
The output of the decoder 41 closes the switch S34 and connects the reference power source 5 to the integrator 4. The comparator 9 uses the time required to reach the comparator level as the first gate signal to the clock generator 2.
Give to 3. The clock generator 23 counts the number of clocks during that period and obtains a count value n ₀ . The counted value of the counter 22 at this time is temporarily held in the latch circuit 24 as shown in FIG. After the integrator initialization cycle after time t22,
At time t23, advance to phase PH17 and switch S3
1 and 33 are turned on at the same time, the input voltage Vi is amplified by the preamplifier 30, and integrated by the integrator 4 by KT (seconds). and time t2
4, the switch S34 is turned on and the integrator 4
Connect the reference power supply Verf to and enter the discharge cycle.
At this time, as shown in Fig. 9 k and m, the output of the integrator 4 reaches the predetermined comparator level.
The time of the gate signal is counted by the counter 22 and the counted value is held in the latch circuit 24. Here, count data obtained during phase PH18 from time t24 to t25 is assumed to be N. Then, the integrator initialization cycle is performed again from time t25, and the switches S32 and S33 are activated from time t26, as shown in FIG.
is turned on, the input of the preamplifier 30 is grounded, and the output offset voltage is integrated by KT (seconds) using the counter 43. Then, at time t27, the counter 43 is reset and the switch S34 is turned on to connect the reference power source Verf to the integrator 4 and discharge it. At this time, the 9th
Since the reset signal to the counter 22 is stopped as shown in FIG. It is held at 24. This phase
Let n ₁ be the count data obtained during PH20. These data N, _n1 are similarly stored in the RAM 54 at a predetermined timing. And time t28
The integrator initialization cycle is performed again from time t2.
9, the same input voltage AD as time t23 to t25
Perform a conversion cycle. In this way, the integrator offset AD conversion cycle and the preamplifier offset AD
AD conversion of the input voltage is performed by combining an AD conversion cycle of the input voltage between the conversion cycles, and data N of the AD conversion value and correction data n ₀ and n ₁ are obtained and used in the calculations shown below. Therefore, a correct AD conversion value is obtained by excluding the influence of the offset voltage Vof of the integrator 4 and preamplifier 30.

That is, the offset voltage Vs of the integrator 4 can be determined by equation (13) in the same manner as in the above-mentioned embodiment, and on the other hand, the offset voltage Vs of the integrator 4 can be obtained using the equation (13). If the voltage of the integrator 4 is ΔVoi, and the output voltage of the integrator 4 after the completion of integration at time t25 is -ΔVor with time t24 as a reference, these voltages are expressed by the following equations (18) and (19), respectively. be done.

ΔVoi=-KT/CR {Vs-A(Vin+Vof)}...(18) -ΔVor=-NT/CR(Verf-Vs)...(19) However, Vof is the offset voltage of the preamplifier 30. In this case as well, since the respective potential differences are the same, N is expressed by the following equation (20) from equations (18) and (19).

N=Vs-A(Vin+Vof)/Verf-VsK...(20) Further, let ΔV03 be the voltage of the integrator 4 at time t27 when the phase PH19 of integrating the offset voltage of the preamplifier 30 from time t26 to t27 ends, Time t
27 as a reference, the output voltage of the integrator 4 after the completion of integration using the reference voltage Verf at time t29 is -ΔV04
Then, these voltages are expressed by the following equations (21) and (22), respectively.
It is expressed as

ΔV03=-KT/CR (Vs-AVof)...(21) -ΔV04=-n ₁ T/CR(Verf-Vs)...(22) And the potential difference is the same as shown in Figure 9a. Therefore, ΔV03 is equal to −ΔV04 and formula (21),
From (22), the following equation (23) is derived.

n ₁ = Vs-AVof/Verf-VsK...(23) Then, substitute the value of Vs obtained from equation (13) into equations (20) and (23), and obtain equations (20) and (23).
By eliminating the offset voltage Vof of the preamplifier 30, the following equation (24) is obtained.

AVin=-Verf/K+n ₀ (N-n ₁ ) ...(24) In this way, even if the preamplifier 30 is added to the integrator 4, the total cost of the AD converter including its offset can be reduced. It becomes possible to correct the offset and obtain a correct AD conversion value.

In this embodiment, an integrator initialization cycle is inserted for each AD conversion cycle, but this integrator initialization cycle can be omitted if strict AD conversion is not required.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional integral type AD converter, Figure 2 is a waveform diagram showing the waveforms of each part,
Figure 3 is a circuit diagram showing an example of another conventional AD converter, Figure 4 is a waveform diagram showing the waveforms of each part, and Figure 5 is a circuit diagram showing an example of another conventional AD converter.
The figure is a circuit diagram showing an embodiment of an integrating AD converter according to the first invention of the present application, Fig. 6 is a waveform diagram showing waveforms of each part thereof, and Fig. 7 is a circuit diagram showing an embodiment of the integral type AD converter according to the second invention of the present application. 8 is a block diagram showing details of the control logic circuit 36 and the arithmetic processing unit 37, and FIG. 9 is a waveform diagram showing waveforms of each part thereof. S1, S2, S3, S15, S31-S35...
...Switch, 4...Integrator, 5, 5a, 5b...
Reference power supply, R6... Input resistance, C7... Capacitor, 9... Comparator, 11, 16, 21, 3
6...Control logic circuit, 12, 22,
40, 43... Counter, 13, 18, 24...
Latch circuit, 23...Clock generator, 25,3
7... Arithmetic processing unit, 30... Preamplifier,
42...Gate circuit, 52...CPU, 54...
RAM.

Claims (1)

[Scope of Claims] 1. An integrator that includes an integrating capacitor and integrates an input signal, and a first and second integrator that switches the input to the integrator to the voltage signal to be measured and a reference voltage source having a constant reference voltage Vref, respectively. a switch, a comparator that compares the output voltage of the integrator with a predetermined level and stops discharging the integrating capacitor of the integrator when the output voltage reaches the predetermined level, and a counter that counts the discharge time of the reference voltage source. integral type with
In the AD converter, a third switch which switches the input of the integrator to the ground side by a control input, a clock signal generator having a constant clock period T, and a clock signal generator having a clock period T which is an integral multiple of the clock period T of the clock signal generator. Close the third switch for a time KT to ground the input end of the integrator to integrate the input offset voltage, then close the second switch to discharge by the reference voltage Vref,
The discharge time is used as the first gate signal, the first switch is closed for the same time as the offset voltage integration time (KT), the voltage to be measured is applied to the integrator, and then the second switch is closed. control means for discharging by the reference voltage Vref and using the discharge time as a second gate signal, and controlling the clock pulse of the clock signal generator by the first and second gate signals obtained from the control means. A counting means that counts the numbers to give counted values n ₀ and N, respectively, and calculates the following formula Vin=-Vref/K+n ₀ (N-n ₀ ) using the counted values of the counting means, and converts Vin to an AD conversion value. An integral type AD converter, characterized in that it is equipped with arithmetic means that performs. 2. The integrating AD converter according to claim 1, wherein the integrator has initialization means for initializing the integrator by short-circuiting an integrating capacitor. 3. A preamplifier that amplifies the input voltage with an amplification factor A, an integrator that includes an integrating capacitor and integrates the amplified signal by the preamplifier, and inputs to the integrator are connected to the voltage signal under test and a constant reference voltage Vref. a comparator that compares the output voltage of the integrator with a predetermined level and stops discharging the integrating capacitor of the integrator when the output voltage reaches the predetermined level;
a counter for counting the discharge time of the reference voltage source; a third switch for switching the input of the integrator to the ground side according to a control input; and a third switch for switching the input of the preamplifier to the ground side according to the control input. a fourth switch for switching the clock to the ground side; a clock signal generator having a constant clock period T; and closing the third switch for a time KT that is an integral multiple of the clock period T of the clock signal generator. The input end of the integrator is grounded to integrate the input offset voltage, and then the second switch is closed to discharge by the reference voltage Vref,
The discharge time is used as the first gate signal, the fourth switch is closed for the same time as the offset voltage integration time (KT), the input end of the preamplifier is grounded, and the input offset voltage is turned off. Then, the second switch is closed to discharge the reference voltage Vref, and the discharge time is used as a second gate signal, and the first voltage is applied for the same time as the offset voltage integration time (KT). control means that closes a switch to apply the voltage to be measured to the integrator, then closes the second switch to cause discharge by the reference voltage Vref, and uses the discharge time as a third gate signal; , a counting means for counting the number of clock pulses of the clock signal generator using first, second, and third gate signals obtained from the control means to obtain count values n ₀ , n ₁ , and N, respectively; and the counting means An integral type AD conversion characterized by comprising a calculation means for calculating the following formula Vin=-Vref/A(K+n ₀ )(N-n ₁ ) using the count value and using Vin as an AD conversion value. vessel. 4. The integrating AD converter according to claim 3, wherein the integrator has initialization means for initializing the integrator by short-circuiting an integrating capacitor.