JPH0140530B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to improvements in interface circuits used in input/output portions of digital circuits, such as A/D conversion circuits and sample-and-hold circuits.

[Prior art]

Here, an A/D converter will be described as an example of a conventional interface circuit.

FIG. 1 shows a 1-bit A/D converter used in a conventional cascade type A/D converter. When the input signal V _IN is applied to the input terminal 1, it is sampled and held in the sample and hold circuit (hereinafter referred to as S/H circuit) 2, and this held voltage V _H (=V _IN ) and the reference voltage V _R /2 is compared in the comparator circuit 3. V _H
When <V _R /2, the output V _0D of the comparison circuit 3 becomes low level L, the switch S1 is closed, the switch S2 is opened, and the operational amplifier 4 outputs V _0A =2V _H =2V _IN . V _H ＞
When V _R /2, the output V _0D of comparator circuit 3 is high level
(H), the switch S1 is opened, the switch S2 is closed, and the operational amplifier 4 outputs V _OA =2V _H -V _R =2V _IN -V _R . FIG. 2 illustrates the relationship between the residual output V _OA from the operational amplifier 4 and the input signal V _IN . That is, the input signal V _IN is compared with the reference voltage V _R /2, 1-bit conversion is performed, and the "remainder" from the comparison voltage is output. Bit A/D shown in Figure 1
If a plurality of converters are connected in series and the residual output of the previous stage is used as the input of the latter stage, the combination of 1-bit outputs (comparison outputs) from each stage constitutes a multi-bit A/D conversion output.

However, in the case of a 1-bit A/D converter as shown in Figure 1, the offsets of the S/H circuit 2, comparator circuit 3, and operational amplifier 4, and the on-resistances of switches S1 and S2 are all dependent on the A/D converter. This is a factor that limits accuracy. For this reason, it has the disadvantage that good performance cannot be obtained without using complex and expensive components, and it is difficult to integrate it into an IC.

Another drawback is that as the number of bits of output data increases, the number of constituent elements increases and the configuration becomes complex.

The situation is similar in the case of the successive approximation type, which is the most common A/D conversion method.The sample-and-hold circuit and comparator are required to have small offsets, and the ladder-shaped resistor circuit and As the number of output bits increases, the number of weighted current sources increases, and high accuracy is required.

As exemplified by high-precision A/D converters, interface circuits often require many high-precision and expensive key components, making it difficult to integrate them into ICs. There was a problem.

〔the purpose〕

The present invention has been made to solve the above problems, and aims to realize an interface circuit that uses fewer high-precision parts and can be easily integrated into an IC.

〔overview〕

In order to achieve the above object, the first gist of the interface circuit according to the present invention is that first and second capacitors are connected to each other at one end, and a connection between the first and second capacitors is provided. a first capacitor connected between the reference voltage and the other end of the first capacitor;
a second switch connected between the input voltage and the other end of the first capacitor; a third switch connected between the common and the other end of the first capacitor; and the other end of the second capacitor;
a fifth switch connected between the output terminal of the inverting amplifier and the other end of the first capacitor; a sixth switch connected between the input terminal and the output terminal of the inverting amplifier; a seventh switch connected between the output terminal of the second capacitor and the other end of the second capacitor, and a control circuit that controls opening and closing of each of the switches, and the second and fourth switches are connected by opening and closing signals from the control circuit. , turn on the sixth switch to maintain the input voltage in the first capacitor, turn on the third and seventh switches to transfer the charge in the first capacitor to the second capacitor, and Switch No. 7 is turned on to maintain the reference voltage in the first capacitor, the third and sixth switches are turned on to reset the first capacitor, and the fourth and fifth switches are turned on to reset the second capacitor. Let the charge of the capacitor be the first
The present invention is characterized in that the input voltage is added or subtracted between the input voltage and the reference voltage by transferring the input voltage to the capacitor.

The second gist of the interface circuit according to the present invention is that the interface circuit is configured as shown in (a) below.
A bit A/D conversion circuit and an input signal or the above-mentioned 1
It consists of a sample and hold circuit that inputs a signal related to the residual output of the bit A/D conversion circuit and whose output signal becomes the input voltage of the A/D conversion circuit, and converts it by repeating it a number of times corresponding to the number of output bits. Accordingly, a plurality of bits of A/D conversion output can be obtained from each comparison output.

(a) first and second capacitors whose ends are connected to each other; an inverting amplifier whose input terminal is connected to the connection point of the first and second capacitors; and a reference voltage and the first capacitor. a first switch connected between the input voltage and the other end of the first capacitor, and a second switch connected between the common and the other end of the first capacitor. a fourth switch connected between the common and the other end of the second capacitor, and a fourth switch connected between the output terminal of the inverting amplifier and the other end of the first capacitor. a fifth switch connected between the input terminal and the output terminal of the inverting amplifier; and a seventh switch connected between the output terminal of the inverting amplifier and the other end of the second capacitor. switch, and a control circuit for controlling the opening and closing of each of the above-mentioned switches, and the second, fourth, and sixth switches are turned on by the opening/closing signal from the control circuit to maintain the input voltage in the first capacitor, 3rd, 7th
switch is turned on to transfer the charge of the first capacitor to the second capacitor, the second and sixth switches are turned on to maintain the input voltage in the first capacitor, and the fourth and fifth switches are turned on to transfer the charge of the first capacitor to the second capacitor. is turned on to transfer the charge of the second capacitor to the first capacitor, a first switch is turned on to generate a comparison output from the inverting amplifier, and a different switch is turned on corresponding to said comparison output to transfer the charge of the second capacitor to the first capacitor. A 1-bit A/D conversion circuit configured to generate an output.

The third gist of the interface circuit according to the present invention is the following 1-bit A/D conversion in which the residual output of each stage is used as the input voltage of the next stage and a number of them are connected in cascade corresponding to the number of output bits. circuit, and a control circuit for controlling opening/closing of each switch of each of the 1-bit A/D conversion circuits, so as to obtain a plurality of bits of A/D conversion output from the comparison output of the first bit A/D conversion circuit. It is characterized by the following.

(a) first and second capacitors whose ends are connected to each other; an inverting amplifier whose input terminal is connected to the connection point of the first and second capacitors; and a reference voltage and the first capacitor. a first switch connected between the input voltage and the other end of the first capacitor, and a second switch connected between the common and the other end of the first capacitor. a fourth switch connected between the common and the other end of the second capacitor, and a fourth switch connected between the output terminal of the inverting amplifier and the other end of the first capacitor. a fifth switch connected between the input terminal and the output terminal of the inverting amplifier; and a seventh switch connected between the output terminal of the inverting amplifier and the other end of the second capacitor. The second, fourth and sixth switches are turned on by the open/close signal from the control circuit to hold the input voltage in the first capacitor, and the third and seventh switches are
switch is turned on to transfer the charge of the first capacitor to the second capacitor, the second and sixth switches are turned on to maintain the input voltage in the first capacitor, and the fourth and fifth switches are turned on to transfer the charge of the first capacitor to the second capacitor. is turned on to transfer the charge of the second capacitor to the first capacitor, a first switch is turned on to generate a comparison output from the inverting amplifier, and a different switch is turned on corresponding to said comparison output to transfer the charge of the second capacitor to the first capacitor. A 1-bit A/D conversion circuit configured to generate an output.

[Description of Examples]

The present invention will be explained below using the drawings.

FIG. 3 is an electrical circuit diagram showing an embodiment of the interface circuit according to the present invention. In the main circuit 30, 31 is a reference voltage terminal to which a reference voltage V _R is applied, S31 is a switch whose one end is connected to this reference voltage terminal 31, 32 is an input terminal to which an input signal V _1N is applied, and S32 is this input terminal. S33 is a switch whose one end is connected to common, C1 is a capacitor whose other end of each of the switches S31, S32, and S33 is connected to one end, and S34 is a switch whose one end is connected to common. The switch C2 is a capacitor whose other end is connected to one end of the switch S34, and 33 is an inverting amplifier whose input terminals are connected to the other ends of the capacitors C1 and C2. For example, an inverter can be used. S35 connects the output terminal of the inverting amplifier 33 to one end of the capacitor C1.
A switch whose one end is connected to the other end, S36 is a switch whose one end is connected to the output terminal of the inverting amplifier 33 and the other end is connected to the input terminal of the inverting amplifier 33, and S37 is a switch whose output terminal of the inverting amplifier 33 is connected to the input terminal of the inverting amplifier 33. Connected to one end of the capacitor C2
A switch 34, one end of which is connected to the other end, is an output terminal for sending out the residual output V _O from the inverting amplifier 33 to the outside. Reference numeral 35 denotes a control circuit which inputs an external clock and the comparison output Vc from the inverting amplifier 33 and generates a control signal for controlling the opening and closing of each of the switches S31 to S37.

FIG. 4 is an explanatory diagram showing the operation of the interface circuit having the above structure as a 1-bit A/D converter. The operation will be explained below based on FIGS. 4A to 4J showing each operation step.

(A) Initially, only switches S32, S34, and S36 are turned on. Input voltage Va of inverting amplifier 33
is equal to the offset (or threshold voltage) V _T of the inverting amplifier 33, so the capacitor C
The terminal voltages V ₁ and V ₂ of C1 and C2 are as follows (charged), respectively.

V ₁ =V _IN -V _T V ₂ =V _T (B) Next, only switches S33 and S37 are turned on. Since V ₁ becomes −V _T , the charge V _IN ·C1 is transferred to the capacitor C2, and V ₂ =V _T −V _I C1/C2.

(C) Only switches S32 and S36 are turned on.
Here, the input V _IN is applied to the capacitor C1 again, and V ₁ =V _IH -V _T. Capacitor C2 enters a hold state and holds the value at (B) as it is.

(D) Only switches S34 and S35 are turned on.
Since V ₂ becomes V _T again, the charge transferred in (B) returns to the capacitor C1, and v ₁ =2V _IH −V _T.

(E) Only switch S31 is turned on. At this time, the inverting amplifier A operates as a comparator, and its input voltage Va becomes Va=V _R −V ₁ =V _R −2V _IN +V _T . When Va is larger than the offset voltage V _T , that is, when V _IN < V _R /2, the output V _O (=
Vc) is L, and in the opposite case, the output V _O (=Vc) is H, and a 1-bit A/D conversion output is obtained.

When V _IN <V _R /2, step (F) below is executed, and when V _IN ≧V _R /2, steps (G) to (J) are executed.

(F) In the case of V _IN <V _R /2, only switch S35 is turned on. As a result, a residual output of V _O =V _T +v ₁ =2V _IN is obtained.

(G) When V _IN ≧V _R /2, in the process that continues up to (J), first only switches S33 and S37 are turned on. Since v ₁ = -V _T , capacitor C1
The charge 2V _IN C1 is transferred to the capacitor C2,
v ₂ =V _T −2V _IN C1/C2.

(H) Next, only switches S31 and S37 are turned on.

Since V ₁ =V _R -V _T , charge C1V _R is transferred from capacitor C2. This result v ₂ =V _T −
(2V _IN −V _R )C1/C2.

(I) Turn on only switches S33 and S36.
Capacitor C1 is reset and v ₁ =-V _T . The capacitor C2 enters a hold state and holds the charge at (H) as it is.

(J) Turn on only switches S34 and S35.
Since v ₂ =V _T , the charge of capacitor C2 -
(2V _IN -V _R )C1 is transferred to capacitor C1. As a result, the output V _O is V _O =V _T +v ₁ =V _T +
2V _IN −V _R −V _T =2V _IN −V _R. That is,
When V _IN ≧V _R /2, a residual output of 2V _IN −V _R is obtained.

In a 1-bit A/D converter with this configuration, the offset (or threshold voltage) of the inverting amplifier
In principle, this does not affect the accuracy of the output, so something as simple as an inverter can be used. It is also possible to obtain the residual output without using any (high precision) resistors. Furthermore, capacitors C1 and C
A value of 2 does not affect accuracy in principle and matching is unnecessary. Since this method uses a capacitor, no current flows in a balanced state, so there is no error caused by the on-resistance of the switch. Another advantage is that a single inverting amplifier can serve as both a hold amplifier and a comparator, making the circuit configuration simple and requiring no high-precision components, making it suitable for IC implementation.

Note that by inserting a buffer in front of the capacitor C1 (point P), the charging time from an external circuit connected to the input portion can be shortened (improvement of input impedance).

FIG. 5 is a block diagram showing a second embodiment of the present invention, in which the 1-bit A/D conversion circuit of FIG.
This is a D converter. In the figure, 51
is an input terminal to which the input signal V _IN is applied, S51 is a switch whose one end is connected to this input terminal 51, 52 is a sample and hold circuit whose other end is connected to the input terminal of this switch S51, and 30 is this S/ The main circuit of the 1-bit A/D conversion circuit whose input is the output of the H circuit 52 (see FIG. 3), S
52 is a switch to which the residual output V _O from the main circuit 30 is connected at one end and the other end is connected to the input of the S/H circuit 52; 53 is a switch which connects the comparison output Vc from the main circuit 30 and an external clock; Input control signals to each switch including S51 and S52 and multi-bit data output D _O ~Dn _-1 (n
This is a control circuit that generates a bit (in the case of a bit).

The operation of the A/D converter having such a configuration is as follows. The input signal V _IN is first held in the S/H circuit 52 by turning on the switch S51. The input V _IN is then applied to the main circuit 30 to generate an A/D conversion output of the first bit (MSB) and a remainder output. This residual output is held in the S/H circuit 52 by turning on the switch S52, and the above procedure is similarly repeated for the required number of bits (n) to output data (A/D conversion output) D _O ~ Dn _-1 get.
However, from the second bit onward, step A in FIG. 4 is unnecessary (the voltage held in capacitor C1 in the final step of the previous conversion can be used as is), and the value from the S/H circuit 52 is ( Used only in step C).

The A/D converter having such a structure has the advantage of not only having the features of the first embodiment but also being able to realize a high-precision, multi-bit A/D converter with a simple structure. Furthermore, the number of bits can be easily expanded by simply increasing the number of repetitions of the procedure.

FIG. 6 is a block diagram showing a third embodiment of the present invention, in which a plurality of 1-bit A/D converters shown in FIG. 3 are connected in series to form a multi-bit A/D converter. be. The input signal V _IN applied to the input terminal 61 is held by the S/H circuit 62 and then input to the main circuit 30 (FIG. 3) of the 1-bit A/D conversion circuit. The remainder output of the main circuit 30 becomes an input to the next stage main circuit 30, and is similarly connected to the number of main circuits 30 corresponding to the required number of bits.
The comparison outputs Vc _O to Vcn _-1 from each main circuit 30 and an external clock are applied to the control circuit 63.
Control output and data output (A/
D conversion output) D _O ~Dn _-1 is generated. In this case, so that the processing step length of each stage does not differ depending on the comparison result shown _{in FIG} .
It is necessary to maintain the state of step (F) until timing (J).

The cascade type A/D in Figure 6 is the circulating type A/D in Figure 5.
The configuration is more complex than that, but it has the advantage of allowing a higher sample rate.

FIG. 7 is an explanatory diagram showing the operation of a fourth embodiment of the present invention in which the interface circuit of FIG. 3 is operated as a differential sample-and-hold circuit. The seventh step is obtained by skipping steps C to G from each operation step of the 1-bit A/D converter in Fig. 4.
This corresponds to steps A to E in the figure. That is, in the final step E, the differential output V _O of the two inputs V _IN and V _R is
= V _IN − V _R can be obtained.

By appropriately combining the above steps,
The calculation of V _O =±mV _IN ±nV _R (m and n are integers) can also be realized. Also, switches S31, S32 and terminal 3
Similarly to 1 and 32, the number of terms in the above equation can be increased arbitrarily by increasing the number of switches and terminals. Also, gain can be obtained by feedback using a resistive voltage divider circuit in the output section.

By providing an S/H circuit at the output of the above-mentioned differential or arithmetic sample/hold circuit, unnecessary output signals at intermediate steps can be shielded from the outside, and only the necessary output from the final step can be output to the outside. can.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize an interface circuit that uses fewer high-precision parts and can be easily integrated into an IC.

[Brief explanation of drawings]

Fig. 1 is an electric circuit diagram showing an example of a conventional interface circuit, Fig. 2 is an explanatory diagram for explaining the input/output relationship of the circuit shown in Fig. 1, and Fig. 3 shows an example of the present invention. 4 is an explanatory diagram of the operation when the interface circuit of FIG. 3 is operated as a 1-bit A/D converter, and FIG. 5 is a block diagram showing a second embodiment of the present invention. , FIG. 6 is a block diagram showing the third embodiment of the present invention, and FIG. 7 shows the operation of the fourth embodiment of the present invention, in which the interface circuit of FIG. 3 is operated as a differential sample and hold circuit. It is an explanatory diagram. 30...Main circuit, 31...Reference voltage terminal, 32
... Input terminal, 33 ... Inverting amplifier, 34 ... Output terminal, 35 ... Control circuit, V _R ... Reference voltage,
V _IN ...Input signal, V _O ...Remainder output, Vc, Vc _O ~
Vcn _-1 ... Comparison output, D _O - Dn _-1 ... A/D conversion output, S31 - S37 ... Switch, C1, C2
...Capacitor, n...Number of output bits.

Claims (1)

[Scope of Claims] 1: first and second capacitors whose ends are connected to each other; an inverting amplifier whose input terminal is connected to the connection point of the first and second capacitors; and a reference voltage and the first capacitor. a first switch connected between the input voltage and the other end of the first capacitor; a second switch connected between the input voltage and the other end of the first capacitor; and a second switch connected between the common and the other end of the first capacitor. a third switch connected between the common and the second switch;
a fourth switch connected between the output terminal of the inverting amplifier and the other end of the first capacitor, and an input terminal of the inverting amplifier. and a seventh switch connected between the output terminal of the inverting amplifier and the other end of the second capacitor, and a control for controlling opening and closing of each of the switches. circuit, the second, fourth, and sixth switches are turned on by the opening/closing signal from the control circuit to maintain the input voltage in the first capacitor;
Turn on the third and seventh switches to transfer the charge in the first capacitor to the second capacitor, and
The seventh switch is turned on to hold the reference voltage in the first capacitor, the third and sixth switches are turned on to reset the first capacitor, and the fourth and fifth switches are turned on to reset the first capacitor. 1. An interface circuit characterized in that the interface circuit is configured to perform addition and subtraction between an input voltage and a reference voltage by transferring the charge of a second capacitor to a first capacitor. 2 A 1-bit A/D conversion circuit configured as in (a) below and an input signal or a signal related to the residual output of the 1-bit A/D conversion circuit are input, and the output signal is input to the A/D conversion circuit. It consists of a sample and hold circuit that serves as the input voltage of the conversion circuit, and is configured to obtain a plurality of bits of A/D conversion output from each comparison output by repeating conversion a number of times corresponding to the number of output bits. interface circuit. (a) first and second capacitors whose ends are connected to each other; an inverting amplifier whose input terminal is connected to the connection point of the first and second capacitors; and a reference voltage and the first capacitor. a first switch connected between the input voltage and the other end of the first capacitor, and a second switch connected between the common and the other end of the first capacitor. a fourth switch connected between the common and the other end of the second capacitor, and a fourth switch connected between the output terminal of the inverting amplifier and the other end of the first capacitor. a fifth switch connected between the input terminal and the output terminal of the inverting amplifier; and a seventh switch connected between the output terminal of the inverting amplifier and the other end of the second capacitor. switch, and a control circuit for controlling the opening and closing of each of the above-mentioned switches, and the second, fourth, and sixth switches are turned on by the opening/closing signal from the control circuit to maintain the input voltage in the first capacitor, 3rd, 7th
switch is turned on to transfer the charge of the first capacitor to the second capacitor, the second and sixth switches are turned on to maintain the input voltage in the first capacitor, and the fourth and fifth switches are turned on to transfer the charge of the first capacitor to the second capacitor. is turned on to transfer the charge of the second capacitor to the first capacitor, a first switch is turned on to generate a comparison output from the inverting amplifier, and a different switch is turned on corresponding to said comparison output to transfer the charge of the second capacitor to the first capacitor. A 1-bit A/D conversion circuit configured to generate an output. 3 The residual output of each stage is used as the input voltage of the next stage, and the number of 1-bit A/D conversion circuits shown in (a) below are connected in cascade corresponding to the number of output bits, and each switch of each of the 1-bit A/D conversion circuits is connected in series. 1. An interface circuit comprising: a control circuit for controlling opening/closing, and wherein a plurality of bits of A/D conversion output are obtained from comparison outputs of each of the 1-bit A/D conversion circuits. (a) first and second capacitors whose ends are connected to each other; an inverting amplifier whose input terminal is connected to the connection point of the first and second capacitors; and a reference voltage and the first capacitor. a first switch connected between the input voltage and the other end of the first capacitor, and a second switch connected between the common and the other end of the first capacitor. a fourth switch connected between the common and the other end of the second capacitor, and a fourth switch connected between the output terminal of the inverting amplifier and the other end of the first capacitor. a fifth switch connected between the input terminal and the output terminal of the inverting amplifier; and a seventh switch connected between the output terminal of the inverting amplifier and the other end of the second capacitor. The second, fourth and sixth switches are turned on by the open/close signal from the control circuit to hold the input voltage in the first capacitor, and the third and seventh switches are
switch is turned on to transfer the charge of the first capacitor to the second capacitor, the second and sixth switches are turned on to maintain the input voltage in the first capacitor, and the fourth and fifth switches are turned on to transfer the charge of the first capacitor to the second capacitor. is turned on to transfer the charge of the second capacitor to the first capacitor, a first switch is turned on to generate a comparison output from the inverting amplifier, and a different switch is turned on corresponding to said comparison output to transfer the charge of the second capacitor to the first capacitor. A 1-bit A/D conversion circuit configured to generate an output.