JPH0141995B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a display drive circuit, particularly a dynamic display drive circuit which receives m character information signals, n digit designation signals, and one display control signal as inputs. Related to improvements to reduce the number of signal lines, etc.

BACKGROUND TECHNOLOGY AND PROBLEMS Conventionally, a so-called dynamic display drive circuit as shown in FIG. 1 has been used to drive and display a multi-digit display element with a small number of signal lines. In the figure, 1 is a digit timing signal generation circuit, 2 is a digit drive circuit, 3 is an N-digit display element, and 4 is a character decoder and drive circuit. The digit timing signal generation circuit 1 is connected to n signal lines for inputting digit designation signals AT ₁ to AT _o and one signal line for inputting a display control signal BLNK. By supplying a digit timing signal to the digit drive circuit 2 through the digit (≦2 ⁿ ) signal lines, the N digits are sent from the digit drive circuit 2 to each designated digit display element of the N digit display element 3. A drive signal is given via a signal line.

Further, m signal lines for inputting character information signals SD ₁ to _{SD o} are connected to the character decoding and driving circuit 4, and the circuit 4 inputs N digits through M signal lines (≦2 ^m ). A character information signal is given to the display element of each designated digit of the display element 3.

In this way, the conventional dynamic display drive circuit described above has only m character information signal lines, n digit designation signal lines, and one display control signal line, and in principle can handle up to N digits (=2 ⁿ It is possible to display M (=2 ^m ) character sets on display elements of (digits).

However, in the conventional circuit configuration described above, when driving multiple systems of display elements, each display drive circuit has m
Book character information signal line, n digit designation signal lines and 1
Since this requires a display control signal line, if there are many circuits (number of axes) to display, such as displaying the amount of movement for multiple moving axes in a numerically controlled machine tool, the required circuit The disadvantage is that the number of required signal lines increases as the number increases, making it complicated and expensive.

OBJECTS OF THE INVENTION An object of the present invention is to improve the drawbacks of the prior art and reduce the number of signal lines, thereby simplifying the configuration and reducing costs.

Summary of the Invention In order to achieve this object, the present invention includes m character information signal lines, n digit designation signal lines, one display control signal line, and n or n+1 systems of N digit display elements. , a decoder circuit that commonly applies a digit timing signal to each digit drive circuit that drives the display element using the row designation signal from the n signal lines and the display control signal from the one signal line; and the display element. a latch signal generation circuit that generates a latch signal from each of the digit designation signals and the display control signal corresponding to each system; and a latch signal generation circuit that sequentially latches the character information signals from the m signal lines in response to the latch signal. The present invention is characterized in that it is provided with a latch circuit that supplies character decoders and drive circuits of corresponding systems, respectively.

Embodiments The present invention will be described below with reference to embodiments shown in the drawings. FIG. 2 shows a general configuration example of the present invention.
With the same number of signal lines as in the conventional example shown in the figure, N-digit display circuits including M character sets can be independently driven in n or n+1 systems.

In the figure, CK ₁ to CK _o+1 are display drive circuits of n+1 systems, and n digit designation signal lines AT ₁ to AT _o 1 are input signal lines to these display drive circuits.
The book display control signal line BLNK and m character information signal lines SD ₁ to _{SD o} are used, and the conventional one line is sufficient.

Each display drive circuit is connected to the digit drive circuit 2 as described above.
₁ to 2 _o+1 , N digit display elements 3 ₁ to 3 _o+1 and character decoder and drive circuits 4 ₁ to 4 _o+1 are provided, and
The system of CK ₁ -CK _o is provided with latch circuits 5 ₁ -5 _o consisting of, for example, 4-bit flip-flops and latch signal generating circuits 6 ₁ -6 _o consisting of AND circuits.

Further, a digit timing signal generation circuit 1 is provided commonly to all display drive circuits.

Digit designation signal AT ₁ to AT _o and display control signal
BLNK is given to the digit timing signal generation circuit 1, which circuit 1 is connected to the digit drive circuit path 2 of each display drive circuit.
A common digit drive timing signal is given to ₁ to 2 _o+1 .

Furthermore, each of the digit designation signals AT ₁ , AT _{2 .} . . and the display control signal BLNK are the latch signal generation circuits 6 ₁ , 6 ₂ . . . of the display drive circuits CK ₁ , CK ₂ .
given to. The character information signals SD ₁ to _{SD o} are commonly given to the latch circuits 5 ₁ to 5 _o of each display drive circuit, but each latch circuit is given a latch signal from each latch signal generation path as described above. The appropriately latched character information signal is applied to each character decoder and drive circuit 4 ₁ -4 _o .

FIG. 3 shows an 8-digit, 3- or 4-axis display drive circuit suitable for displaying the amount of movement in a numerically controlled machine tool as a specific example of the above-described configuration. In the _same figure _{, CK
X} to _5Z and latch signal generation circuits _6X to _6Y are not provided.

Figure 4 shows the digit designation signal used in the above circuit.
AT ₁ ~ _{AT 3} , display control signal BLNK, character information e.g. (BCD) signal SD ₁ ~ _{SD 4} and latch signal LK _X
~ Shows the timing chart of LK _Z. In the same figure, the display control signal BLNK consists of the timing of the light-off level H and the light-on level L, as shown in the figure.
On the other hand, the levels of the digit designation signals AT ₁ to _{AT 3} change as shown in the figure within the timing of the turn-off level of the display control signal, and these digit designation _signals and Latch timing signals LK _X to LK _Z are obtained by ANDing with the display control signal. By these latch timing signals, the character information signals SD ₁ to SD ₄ are sequentially transmitted from X to Z in each latch circuit 5 _X to 5 _Z at t3 _X , t _3Y ,
It is latched at timings such as t _3Z , and the X-axis, Y-axis,
Z-axis BCD output (3rd digit) D _3X , D _3Y , D _3Z is obtained. Note that D _3T is the BCD output of the T axis. FIG. 5 is a flowchart specifically showing the timing operation in one digit timing section of the microcomputer-using system as the embodiment of FIG.

Effects of the Invention As is clear from the above explanation, according to the present invention, the display element can be driven with a very small number of signal lines for a large number of display axes (number of display circuits), so the main body and the display section can be separated. When installing the device, the number of cable lines and connector terminals can be reduced. In addition, even if the number of display axes is expanded, if it is within the allowable range (n or n+1), there is no need to change or add the number of signal lines, which helps standardize the hardware and software during system configuration. be able to. The above enables cost reduction, and is particularly suitable as a display drive circuit for a system equipped with a microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional dynamic display drive circuit, FIG. 2 is a block diagram showing a general configuration example of the present invention, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 is a block diagram showing a general configuration example of the present invention. is a timing chart for explaining the operation, and FIG. 5 is a flow chart for explaining the operation. CK ₁ ~ _{C o+1} ... Display drive circuit, 1 ... Digit timing signal generation circuit, 2 ₁ - 2 _o+1 ... Digit drive circuit,
3 ₁ to 3 _o+1 ...N digit display element, 4 ₁ to 4 _o+1 ... character decoder and drive circuit, 5 ₁ to 5 _o ... latch circuit, 6 ₁ to 6 _o ... latch signal generation circuit , AT ₁ ~
AT _o ...Digit designation signal, BLNK...Display control signal,
SD ₁ ~SD _o ...Character information signal.

Claims (1)

[Claims] 1 m character information signal lines, n digit designation signal lines, 1 display control signal line, n or n+1 systems of N digit display elements, and digit designation signals from the above n signal lines. and a digit timing signal generation circuit which supplies a digit timing signal to a line commonly connected to each digit drive circuit that drives display elements of each system using a display control signal from one signal line; a latch signal generation circuit that generates a latch signal from each of the digit designation signals and a display control signal corresponding to each system; 1. A display drive circuit comprising a latch circuit that sequentially latches information signals and applies the latch signals to character decoders and drive circuits of display elements of corresponding systems.