JPH0142144B2 - - Google Patents
Info
- Publication number
- JPH0142144B2 JPH0142144B2 JP55173102A JP17310280A JPH0142144B2 JP H0142144 B2 JPH0142144 B2 JP H0142144B2 JP 55173102 A JP55173102 A JP 55173102A JP 17310280 A JP17310280 A JP 17310280A JP H0142144 B2 JPH0142144 B2 JP H0142144B2
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- substrate
- solution
- layer
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
- H10D48/30—Devices controlled by electric currents or voltages
- H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H10D48/34—Bipolar devices
- H10D48/345—Bipolar transistors having ohmic electrodes on emitter-like, base-like, and collector-like regions
Landscapes
- Bipolar Transistors (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Description
【発明の詳細な説明】
本発明は、GaAsやGaAIAs等のGaAs系化合物
半導体を母材としたnpnトランジスタの製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an npn transistor using a GaAs-based compound semiconductor such as GaAs or GaAIAs as a base material.
GaAs系npnトランジスタも通常のnpnトランジ
スタと同様に液相成長、気相成長あるいは拡散技
術を駆使することによつて製造することができ
る。しかし、通常の製造方法では、ベース層内の
キヤリア拡散長が極めて小さく、従つて極めて薄
いベース層としなければならないため、再現性良
く製造することは困難であつた。 GaAs-based npn transistors can also be manufactured by making full use of liquid phase growth, vapor phase growth, or diffusion techniques in the same way as normal npn transistors. However, with normal manufacturing methods, the carrier diffusion length within the base layer is extremely small, and therefore the base layer must be extremely thin, making it difficult to manufacture with good reproducibility.
本発明は、この欠点を除き、且つ、高速度特性
と高耐圧特性等を有するnpnトランジスタを得る
ことを目的とし、これをSiを不純物とした除冷式
液相成長ででコレクタ層とベース層とを成長さ
せ、且つ、両層間で基板を覆う溶液の厚さを変え
ることによつて達成したものである。 The purpose of the present invention is to eliminate this drawback and to obtain an npn transistor having high speed characteristics and high breakdown voltage characteristics, etc., by forming a collector layer and a base layer by slowly cooling liquid phase growth using Si as an impurity. This was achieved by growing the two layers and varying the thickness of the solution covering the substrate between the two layers.
第１図〜第３図は本発明の一実施例の説明図で
あり、第１図は徐冷式液相成長における溶液温度
制御プロセスを示し、第２図はこの方法で用いる
製造装置の構造を示し、第３図はこの実施例で得
られたnpnトランジスタにおけるキヤリヤ濃度分
布を示したものである。 Figures 1 to 3 are explanatory diagrams of one embodiment of the present invention, with Figure 1 showing the solution temperature control process in slow cooling liquid phase growth, and Figure 2 showing the structure of the manufacturing equipment used in this method. FIG. 3 shows the carrier concentration distribution in the npn transistor obtained in this example.
この実施例は、第２図に示した如く、ｎ型
GaAs基板１を炉内の基板保持板２に設置し、
又、GaAs溶質とSi不純物とを溶存させたGa溶液
３を溶液ホルダ４に設置し、スライダ５，６を移
動させてｎ型GaAsのコレクタ層とｐ型GaAsの
ベース層とを次順に連続して徐冷成長させるもの
である。このn+型GaAs基板１内のキヤリヤ濃度
は、第３図に示した如く一様である。 In this embodiment, as shown in FIG.
Place the GaAs substrate 1 on the substrate holding plate 2 in the furnace,
Further, a Ga solution 3 in which a GaAs solute and Si impurities are dissolved is placed in the solution holder 4, and the sliders 5 and 6 are moved to successively form an n-type GaAs collector layer and a p-type GaAs base layer. It is grown by slow cooling. The carrier concentration within this n + type GaAs substrate 1 is uniform as shown in FIG.
第１図のプロセスにおいて、Si不純物と飽和量
以上のGaAS溶質とを溶解したGa溶液３を一度
ｎ−ｐ反転温度T1より高い温度T0に上昇させ、
溶質を十分溶解させた後、時刻t0より徐冷してい
くとSi不純物ドープのGaAsの結晶成長が行われ
る。本実施例では、このt0以後の時刻、例えば時
刻t1において、スライダ５及び６を移動させてn+
型GaAs基板１上を前記Ga溶液３で覆うとエピタ
キシヤル成長が行われる。すなわち、ｎ−ｐ反転
温度T1より高い温度T2より徐冷してゆくと、前
記n+型GaAs基板１上にｎ型のコレクタ層が成長
する。このコレクタ層のキヤリヤ濃度は第３図に
示したようにn+型GaAs基板１側よりベース層に
向つてそのキヤリヤ濃度が徐々に小さくなるよう
に分布する。更に徐冷してゆくと第１図に示す時
刻t2でｎ−ｐ反転温度T1となり、時該t3までこの
まま連続して徐冷してゆくとｐ型のベース層が成
長してゆく。なお、第１図に示すように、徐冷に
おける冷却速度はほぼ一定である。 In the process shown in FIG. 1, the Ga solution 3 in which Si impurities and a saturation amount of GaAS solute are dissolved is once raised to a temperature T 0 higher than the n-p inversion temperature T 1 , and
After sufficiently dissolving the solute, cooling is continued from time t0 , and crystal growth of Si impurity-doped GaAs takes place. In this embodiment, at a time after this t 0 , for example, at time t 1 , sliders 5 and 6 are moved to n +
When the GaAs substrate 1 is covered with the Ga solution 3, epitaxial growth is performed. That is, as the temperature is gradually cooled from a temperature T 2 higher than the n-p inversion temperature T 1 , an n-type collector layer grows on the n + type GaAs substrate 1 . As shown in FIG. 3, the carrier concentration in the collector layer is distributed such that the carrier concentration gradually decreases from the n + type GaAs substrate 1 side toward the base layer. As the temperature is further slowly cooled, the n-p reversal temperature T 1 is reached at time t 2 shown in Figure 1, and as the temperature continues to cool until t 3 , a p-type base layer grows. . Note that, as shown in FIG. 1, the cooling rate during slow cooling is approximately constant.
本実施例では、このｎ−ｐ反転温度T1におい
てスライダ５はそのままとしスライダ６を移動さ
せて、薄いGa溶液３で覆いｐ型のベース層を成
長させる。このベース層では第３図に示すように
コレクタ層側よりキヤリヤ濃度が徐々に増加する
ようなキヤリヤ分布となる。 In this embodiment, at this n-p inversion temperature T1 , the slider 5 is left as it is and the slider 6 is moved to cover it with a thin Ga solution 3 and grow a p-type base layer. As shown in FIG. 3, this base layer has a carrier distribution in which the carrier concentration gradually increases from the collector layer side.
このように徐冷して液相成長させ、適当な時刻
t4で成長を中止させるために、スライダ５を移動
させてｐ型半導体基板１からGa溶液３を離す。
ｎ型エミツタ層は、時刻t3からt4までに成長した
ｐ型層にSn等を拡散してn+層にすることによつ
て形成する。この結果、第３図に示すようなキヤ
リヤ濃度分布のnpnトランジスタを製造すること
ができる。 In this way, slow cooling allows liquid phase growth, and then
In order to stop the growth at t 4 , the slider 5 is moved to separate the Ga solution 3 from the p-type semiconductor substrate 1 .
The n-type emitter layer is formed by diffusing Sn or the like into the p-type layer grown from time t 3 to time t 4 to form an n + layer. As a result, an npn transistor having a carrier concentration distribution as shown in FIG. 3 can be manufactured.
本発明のnpnトランジスタはベース層のキヤリ
ヤ濃度がエミツタ層側で高く、コレクタ層側で低
くなるキヤリヤ濃度分布を有するために、トラン
ジスタ動作において電子をドリフトさせる電界が
生じ、キヤリヤの実効拡散長が長くなり、ベース
幅を広くして制御しやすくすることができると共
に、高速応答特性の改善を図ることができるもの
である。 Since the npn transistor of the present invention has a carrier concentration distribution in which the carrier concentration in the base layer is high on the emitter layer side and low on the collector layer side, an electric field that causes electrons to drift occurs during transistor operation, and the effective diffusion length of the carriers becomes long. Therefore, the base width can be widened to facilitate control, and high-speed response characteristics can be improved.
更に第３図に示す如く、ベース・コレクタ接合
部の近傍のキヤリヤ濃度を低濃度とすることによ
り高耐圧効果が期待でき、大電力化が容易なnpn
トランジスタとすることができる。 Furthermore, as shown in Figure 3, by reducing the carrier concentration near the base-collector junction, a high withstand voltage effect can be expected, making it easy to increase the power consumption of NPN.
It can be a transistor.
更に本実施例においては、ｎ−ｐ反転温度T1
において、スライダ６を移動させてGa溶液の厚
さを小さくして基板１を覆うため、コレクタ成長
におけるキヤリヤ濃度変化よりもベース成長にお
けるキヤリヤ濃度変化が大きく、従つて、低濃度
のコレクタ層が得やすく、且つ、大きな実効拡散
長のベース層が得やすいものである。 Furthermore, in this embodiment, the n-p inversion temperature T 1
In this step, since the slider 6 is moved to reduce the thickness of the Ga solution to cover the substrate 1, the carrier concentration change during the base growth is larger than the carrier concentration change during the collector growth, and therefore a low concentration collector layer is obtained. It is easy to obtain a base layer with a large effective diffusion length.
なお、前記実施例において、Ga溶液中に溶存
させたGaAs溶質に代えて、AI−GaAs等の他の
GaAS系溶質を溶存させておくことによつて、他
のGaAs系npnトランジスタを製造することがで
きる。 In the above examples, instead of the GaAs solute dissolved in the Ga solution, other materials such as AI-GaAs were used.
Other GaAs-based npn transistors can be manufactured by dissolving the GaAS-based solute.
また、前記実施例におけるn+型GaAs半導体基
板に代えてn+層を有する絶縁性基板、又はｐ型
基板を用いることによつて、npnトランジスタを
構成要素とする集積回路を作ることができる。ま
た前記実施例において、エミツタ層を拡散で形成
したが、時刻t3（第１図参照）で成長を止め、エ
ミツタ層を別の温度サイクルの液相成長法で成長
させてもよい。またベース層に比べて、大きなエ
ネルギー禁止帯を有するGaAs系半導体でエミツ
タ層を形成することによつてエミツタ注入効率を
高めることができる。 Further, by using an insulating substrate having an n + layer or a p-type substrate in place of the n + type GaAs semiconductor substrate in the above embodiment, an integrated circuit having npn transistors as a component can be manufactured. Further, in the above embodiment, the emitter layer is formed by diffusion, but the growth may be stopped at time t 3 (see FIG. 1) and the emitter layer may be grown by a liquid phase growth method using a different temperature cycle. Furthermore, by forming the emitter layer with a GaAs-based semiconductor having a larger energy forbidden band than the base layer, the emitter injection efficiency can be increased.
以上の如く本発明によれば、高速性と高耐圧特
性等を有するGaAs系のnpnトランジスタを作る
ことができ、又、このnpnトランジスタを構成要
素とする集積回路を作ることができる。 As described above, according to the present invention, a GaAs-based npn transistor having high speed and high breakdown voltage characteristics can be manufactured, and an integrated circuit using this npn transistor as a component can be manufactured.
第１図は本発明の一実施例のGaAs系のnpnト
ランジスタを作るための徐冷式液相成長法におけ
る溶液温度制御プロセスを示した図、第２図はそ
の実施例で用いた製造装置の構造を示す断面図、
第３図はこの実施例で得られたnpnトランジスタ
におけるキヤリヤ濃度分布を示した図である。
１……n+型GaAs基板、２……基板保持板、３
……Ga溶液、４……溶液ホルダ、５，６……ス
ライダ。
Figure 1 shows the solution temperature control process in the slow cooling liquid phase growth method for manufacturing a GaAs-based npn transistor according to an embodiment of the present invention, and Figure 2 shows the manufacturing equipment used in that embodiment. A sectional view showing the structure,
FIG. 3 is a diagram showing the carrier concentration distribution in the npn transistor obtained in this example. 1...n + type GaAs substrate, 2...substrate holding plate, 3
...Ga solution, 4...solution holder, 5, 6...slider.
Claims (1)
と基板とを炉内に用意する工程と、 ある厚さの前記Ga溶液で前記基板を覆い、ｎ
−Ｐ反転温度より高い温度からｎ−ｐ反転温度ま
でほぼ一定の冷却速度で徐冷しながら、前記基板
上にｎ型コレクタ層を形成する工程と、 前記Ga溶液の前記厚さを減じ、前記ｎ−ｐ反
転温度から前記冷却速度でさらに徐冷しながら、
前記ｎ型コレクタ層上にｐ型ベース層を形成する
工程と、 ｎ型エミツタ層を形成する工程と を有することを特徴としたnpnトランジスタの製
造方法。[Claims] 1. A step of preparing a substrate and a Ga solution dissolving a GaAs-based solute and Si impurities in a furnace, and covering the substrate with the Ga solution of a certain thickness,
- forming an n-type collector layer on the substrate while slowly cooling from a temperature higher than the P inversion temperature to the n-P inversion temperature at a substantially constant cooling rate; and reducing the thickness of the Ga solution; While further gradually cooling from the n-p inversion temperature at the cooling rate,
A method for manufacturing an npn transistor, comprising: forming a p-type base layer on the n-type collector layer; and forming an n-type emitter layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173102A JPS5797665A (en) | 1980-12-10 | 1980-12-10 | Manufacture of npn transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173102A JPS5797665A (en) | 1980-12-10 | 1980-12-10 | Manufacture of npn transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5797665A JPS5797665A (en) | 1982-06-17 |
| JPH0142144B2 true JPH0142144B2 (en) | 1989-09-11 |
Family
ID=15954208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55173102A Granted JPS5797665A (en) | 1980-12-10 | 1980-12-10 | Manufacture of npn transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5797665A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61159725A (en) * | 1984-12-29 | 1986-07-19 | Toyota Central Res & Dev Lab Inc | Liquid phase growth method of compound semiconductor |
| JPH01179452A (en) * | 1988-01-06 | 1989-07-17 | Nec Corp | Heterojunction semiconductor device and manufacture thereof |
| JPH01179453A (en) * | 1988-01-06 | 1989-07-17 | Nec Corp | Heterojunction semiconductor device and manufacture thereof |
| JPH01179454A (en) * | 1988-01-06 | 1989-07-17 | Nec Corp | Heterojunction semiconductor device and its manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5123438B2 (en) * | 1972-06-14 | 1976-07-16 |
-
1980
- 1980-12-10 JP JP55173102A patent/JPS5797665A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5797665A (en) | 1982-06-17 |
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