JPH0145097B2 - - Google Patents

Description

Detailed Description of the Invention (Technical Field) The present invention detects a double moving average value in which the average value of values within a certain period of time is sequentially determined, and the average value of the values within a certain period of time is further calculated from the average value. This is realized using digital circuits.

(Prior Art) A method for realizing a moving average value using a digital circuit includes the method described in the specification of Japanese Patent Application No. 57-211495. FIG. 1 shows the above-mentioned conventional example, and the operation of the conventional example will be briefly explained. In the figure, 1 is an input terminal, and one of two values, 1 and 0, is input. 2 is an M+1 stage shift register (M is a positive integer); 3 is a sampling clock oscillator;
4 is a logic circuit which inputs the contents of the first stage of the shift register 2 where data is written first and the M+1th stage where data is written last. 5
is an up-down counter that can count up to at least M, and 6 is a digital comparator.
The data at input terminal 1 is sampled according to the clock of sampling clock oscillator 3, and
The data is read into the first stage A of a one-stage shift register (hereinafter referred to as shift register). The data is stored when the clock of the sampling clock oscillator 3 is 1.
It shifts to the right every cycle, and M+ of shift register 2 is shifted to the right by M sampling clocks.
Shift to 1st stage B. The logic circuit 4 performs the logical operation shown in FIG.
The up-count or down-count of the up-down counter 5 is determined based on the contents of the stage A and the contents of the M+1 stage B. The frequency c of the sampling clock oscillator 3 is a high frequency that samples the signal applied to the input terminal 1 as faithfully as possible, and is determined by the following equation.

c=M/T However, T is the time length for obtaining the average value.

Next, the operation of the circuit configured as described above will be explained. First, it is assumed that the contents of each stage of the shift register 2 and the contents of each bit of the up-down counter are all "0". When the sampling clock oscillator 3 advances by one cycle, the sampling data is taken into the first stage A of the shift register 2. If this value is "1", the second stage of shift register 2 will be
As the value changes, the up-down counter 5 counts up by 1 bit according to the logic operation shown in FIG. Thereafter, the sampling data is sequentially moved in the shift register 2 according to the sampling clock,
The contents of the up-down counter 5 are increased by the number of "1"s in the sampling data. When the number of sampling clocks reaches M+1, the first sampling data appears at the M+1st stage B of the shift register 2.
The numbers whose contents are "1" in each of the second to M+1st rows match the contents of the up-down counter 5.
Next, 1st stage A and M+1st stage B of shift register 2
When the values match, the number of "1"s in the second to M+1 stages does not change even if the contents of the shift register 2 are shifted one stage at a time at the next sampling clock. At this time, the contents of the up-down counter 5 do not change either. In addition, when the content of the first stage A of shift register 2 is "1" and the content of M+1 stage B is "0", the next sampling clock shifts the second stage to M+.
The number of "1"s in the first row increases by one, and the contents of the up-down counter 5 also increase by one. Conversely, if the contents of the first stage A of shift register 2 are "0", the contents of the M+1st stage B
When the content of is "1", the number of "1"s in the second to M+1 stages of the shift register 2 decreases by one, and the content of the up-down counter 5 also decreases by one. As described above, the number of "1"s in the second to M+1 stages of the shift register 2 always matches the contents of the up-down counter 5. Also shift register 2
The number of "1"s in the contents of the second to M+1st rows indicates how often there were "1"s from that time to the time T back, and this number By comparing M and M, it means that the time average within the above-mentioned time period is being calculated. Since the contents of the shift register 2 change sequentially in accordance with the period of the sampling clock oscillator 3, a moving average within time T is obtained. By setting M/2 in the digital comparator 6, it is possible to obtain at the output terminal 7 whether the average value exceeds 1/2. In addition, in the circuit shown in Fig. 1, if the number of "1"s in the second to M+1 stages of the shift register 2 and the contents of the up-down counter 5 do not match for some reason, for example due to disturbances such as noise, from then on they are correct. It no longer shows the moving average value. A conventional example shown in FIG. 3 has been devised to prevent this. In Fig. 3, 8 and 9 are logic circuits,
The same reference numerals as in the figures indicate the same or equivalent parts. When the content of the up-down counter 5 reaches M, the logic circuit 8 closes the gate of the logic circuit 9 which inputs the output of the logic circuit 4, and does not count up even if an up-count instruction is issued from the logic circuit 4. When the content of the up-down counter 5 is 0, even if a down-counting instruction is issued from the logic circuit 4, the up-down counter 5 is not allowed to count. With the configuration as described above, when M or more pieces of sampling data are consecutively "1" or "0", correction is automatically performed, so that a correct moving average value is indicated.

By the way, a moving average can be considered a type of low-frequency wave filter, but a moving average with only one stage does not have enough attenuation.
When the required amount of attenuation cannot be obtained, it may be necessary to obtain a two-stage moving average (hereinafter referred to as a double moving average value). The output appearing at the output terminal 7 in FIG. 1 or 3 indicates whether the moving average value exceeds a certain set value (for example, 1/2), and does not represent the moving average value itself.
Therefore, the output cannot be used as an input to the next moving average value detection circuit. Further, the contents of the up-down counter 5 represent a moving average value, but since it is multi-valued, an extremely complicated procedure is required to further obtain a moving average of this multi-valued value.

(Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a method for realizing a circuit using a digital circuit that extremely easily obtains a double moving average value and detects whether the average value exceeds a certain set value. It is something to do. The contents of the present invention will be explained in detail below using the drawings.

(Configuration of the Invention) The configuration of the present invention includes a sampling clock oscillator and an M+1 clock that is written in synchronization with the oscillator.
(M is a positive integer) stage shift register, an up-down counter that can count up to at least M, and a count when the data in the first stage and the M+1 stage where data is finally written in the M+1 stage shift register are the same value. If the data in the first stage and the M+1 stage of the M+1 stage shift register have different values, the up-count or down-count is performed in synchronization with the oscillator according to the different states, and furthermore, the count number of the up-down counter is When it is "M", up-counting does not occur even if the up-counting conditions are met, and when the count number of the up-down counter reaches "0", it does not count down even if the down-counting conditions are met. The moving average value detection circuit is connected so that the output of the Mth stage of the M+1 stage shift register in the preceding stage is written to the first stage of the M+1 stage shift register in the succeeding stage, and at least
A register that can store up to M ² +M, an adder that adds the count contents of the up-down counter in the previous stage to the register, and a subtractor that subtracts the count contents of the up-down counter in the subsequent stage from the register.
It has a digital comparator, and if the contents of the register exceeds ^M2 at the time the subtraction is completed, the contents of the register are set to ^M2 , and if the contents of the register are less than "0" at the time the subtraction is completed, it is set to "M2". 0'', and the digital comparator compares the contents of the register with a constant value to determine whether or not the constant value has been exceeded. Examples will be described in detail below.

(Description of Examples) First, an algorithm for calculating a moving average will be explained. Let x _k be the kth sampling value of the signal.
x _k is 1 or 0. The k-th moving average y _k is y _k = 1/M _M-1 〓 ^m=0 x _kn ...(1) where M is the number of samples for which moving average is to be performed, including the k-th sample from the k-th sample. Take the average of the past M sample values. The moving average value z _k of the moving average value y _k becomes a double moving average value of the sample value x _k and is expressed by the following equation.

z _k =1/M _M-1 〓 ⁿ⁼⁰ y _ko ...(2) Equation (2) is transformed as follows.

z _k =1/M _M-1 〓 ⁿ⁼⁰・1/M _M-1 〓 ^m=0 x _kno =1/M ² _M-1 〓 ⁿ⁼⁰ _M-1 〓 ^m=0 x _kno ……( 3) Expanding the double moving average value z _k with respect to m, we get Here, since x _k is 1 or 0, the double moving average value z _k is the maximum value z _{k (nax)} and the minimum value z _{k (nio)} is z _{k (nax)} = 1/M ² ( 1+...+M+...1)=1/M
² × {M (M + 1) / 2 × 2 - M} = 1 ... (4) z _{k (nio)} = 0 ... (5) and z _{k (nax)} means that x _k is at least 2M consecutive z _k(nio) occurs when x _k is "0" for at least 2M consecutive times. Hereafter, the double moving average value [z _k ] normalized by M ² will be considered. That is, [z _k ]=M ² · z _k ...(6).

Comparing the kth double moving average value and the (k+1)th double moving average value, [z _k ]=x _k +2x _k-1 +...+Mx _k-(M-1) +... +
x _k-(2M-2) [z _k+1 ]=x _k+1 +2x _k +…+Mx _k-(M-2) +…
+x _k-(2M-3) , that is, (x _k+1 +x _k +...+x _k-(M-2) ) is added to the kth, (x _k-(M-1) +...+x _{k- (2M-2)} ), it becomes (k+1)th. Therefore, the k+1st is [z _k+1 ] = [z _k ] + ( _M-2 〓 ^m=-1 x _kn − _2M-2 〓 ^m=-1 x _kn ) When generalized, [z _k ] = [z _k-1 ] + ( _M-1 〓 ^m=0 x _kn − _2M-2 〓 ^m=M x _kn ) ...(7) From equations (2) and (6), [z _k ]=[y _k ]+…+[y _k-(M-1) ] [z _k-1 ]=[y _k-1 ]+…+[y _kM ], so Equation (7) is [z _k ]=[z _k-1 ]+([y _k ]−[y _kM ]) ……same meaning as (8), y _k → _M-1 〓 ^m=0 x _kn , y _kM → _M-1 〓 ^m=0 x _k-(n+M) = _2M-2 〓 ^m=M x _kn , respectively. However, [y _k ]=M·y _k . Here, considering the recurrence formula [z _k ]=[z _k-1 ]+([y _k ]−[y _kM ]), if i≦0, [z _i ]=0, [y _i ]=0 If we assume that _[ z ₁ \] = [z _D ] + ₍ [ _{y 0} ]−[y− _{M ])} 〓 〓 〓 〓 〓 [z _M \] = [z _M-1 \] + ([y _M ] - [y ₀ ]) 〓 〓 +) [z _k ] = [z _k-1 \] + ([ y _k ]−[y _kM ]) [z _k ]=[z ₀ ]+( _K 〓 ⁱ⁼⁰ yi− _K 〓 ⁱ⁼⁰ yi−M) By the way, _M 〓 ⁱ⁼⁰ [y _iM ]=0, [ Since z ₀ ]=0, [z _k ]= _k 〓 ⁱ⁼⁰ [y _i ]− _k 〓 ^i=M [y _iM ] ……(9) Here, [y _i ]= _M-1 〓 ^{m =0} x _in , [y _iM ] = _2M-2 〓 ^m=M x _in .

The first term of equation (9) is _i =0 to (M
−1), the second term is the sample value x _i
This shows that it is sufficient to sum up the moving averages from i=M to (2M-1) from the past, and then perform the respective additions and subtractions. The moving average is
In particular, if there is no time limit, it will continue indefinitely, so _k 〓 ⁱ⁼⁰ [y _i ] and _k 〓 ^i=M [y _iM ] will diverge to infinity. To prevent this, the following modification is performed.

That is,
_M-1 〓 ⁱ⁼⁰ [y _iM ] = 0, so _k 〓 ^i=M [y _iM ] = _M-1 〓 ⁱ⁼⁰ [y _iM ] + _k 〓 ^i=M [y _iM ] = _k 〓 ⁱ⁼⁰ [y _iM ] ...(10) From equations (9) and (10), [z _k ]= _k 〓 ⁱ⁼⁰ [y _i ]− _k 〓 ^i=M [y _iM ]= _k 〓 ^{i= 0} [y _i ] _−k 〓 ⁱ⁼⁰ [y _iM ]= _k 〓 ⁱ⁼⁰ ([y _i ]−[y _iM ]) That is, M ²・z _k = _k 〓 ⁱ⁼⁰ (M・y _i −M・y _iM ) ...(11) However, since z _k(nax) = 1 and z _k(nio) = 0,
The sum of (M·y _i −M·y _iM ) never diverges.

The present invention is for realizing equation (11) and outputting whether the value exceeds a preset value, and an example thereof is shown in FIG. In the same figure, 2-1, 2-2 are M+1 stage shift registers (hereinafter referred to as shift registers), 4-1, 4-
2 is a logic circuit; 5-1 and 5-2 are up-down counters; 12 is a register that can store at least M ² +M (hereinafter simply referred to as a register); 10 is the contents of register 12 and an up-down counter 5- Add the contents of register 1 and add the contents of register 1.
2 is an adder that stores the result; 11 is a subtracter that subtracts the contents of up-down counter 5-2 from the contents of register 12 and stores the result in register 12; 13 is a comparator that stores the contents of register 12; It compares it with a fixed value, for example M ² /2, and outputs to the output terminal 14 whether or not the value has been exceeded.

The contents of the Mth stage of the shift register 2-1 are written into the first stage A of the shift register 2-2 in accordance with the clock of the sampling clock oscillator 3. Therefore, the contents of the M+1 stage B of the shift register 2-1 and the contents of the 1st stage A of the shift register 2-2 always match, so a 2M+1 stage shift register is placed in place of the shift registers 2-1 and 2-2. ,
The contents of the M+1st stage are stored in logic circuits 4-1 and 4-.
2, the same operation will occur. Next, the operation of the circuit shown in FIG. 4 will be explained. The contents of the up-down counter 5-1 are equal to both sides of equation (1) multiplied by M. That is, M・y _k = _k 〓 ^m=0 x _kn ...(12) The sampling data is written to the first stage A of the shift register 2-2 with a delay of M times from the first stage A of the shift register 2-1. From equation (12), the contents of the up-down counter 5-2 are M・y _kM = _M-1 〓 ^m=0 x _knM ……(13) Therefore, the contents of the register 12 are _k 〓 ⁱ⁼⁰ (M・y _i −M・y _iM ), which satisfies equation (11). Therefore, to detect whether the average value exceeds an arbitrary value between 0 and 1, it is sufficient to set the number obtained by multiplying an arbitrary value between 0 and 1 by M ² in the digital comparator 13, and also set the double moving average value. is 1/
When detecting whether the value exceeds 2, by setting M ² /2 in the digital comparator 13, it can be outputted to the output terminal 14.

As explained above, in the first embodiment, it is possible to detect a double moving average value with a simple configuration.

A second embodiment according to the present invention is shown in FIG. The circuit shown in FIG. 5 can also be considered as a double moving average value detection circuit as a recovery means when a malfunction occurs, and shows an embodiment thereof. Logic circuit 8-
1, when the content of the up-down counter 5-1 reaches M, the gate of the logic circuit 9-1 that inputs the output of the logic circuit 4-1 is closed, and the logic circuit 4-1 issues an up-count instruction. Conversely, when the content of the up-down counter 5-1 is "0", the gate of the logic circuit 9-1 is closed to prevent counting even if a down-count instruction is issued from the logic circuit 4-1. . With this configuration, even if the number of "1"s from the second stage to the M+1 stage of the shift register 2-1 does not match the contents of the up-down counter 5-1, it will automatically recover. This is as described in the explanation of Figure 3. Also, logic circuit 8
-2 corresponds to the logic circuit 8-1, and the logic circuit 9-2 corresponds to the logic circuit 9-1, and their functions are the same. Similarly, the register 12 can also be considered. First, from equation (4) and the explanations before and after it, the maximum value z _k(nax) of the k-th double moving average value z _k is "1" when at least 2M sampling data x _k are consecutive.
Appears when , and its value is 1. That is, the maximum value of the contents of register 12 is ^M2 . Similarly, from equation (5), the minimum value z _k(nio) of z _k appears when at least 2M pieces of sampling data x _k are consecutively "0", and the value is 0 and the contents of register 12 are also 0. . If the contents of the register 12 become larger than the correct value for some reason (such as electrical disturbance), at least 2M pieces of sampling data become "1".
The contents of register 12 become M ² before continuing, and after that, the maximum value determined by the finite bit length of register 12 is the turning point, and the binary value is sign-inverted, and no special modification is performed. Until then, the register 12 will forever show a value that deviates from the correct value. Similarly, when the contents of the register 12 become smaller than the correct value, the contents of the register 12 become 0 before at least 2M consecutive pieces of sampling data become "0", and also indicate a binary value whose sign has been inverted. To prevent this, we have prepared a logic circuit 15 which has the function of automatically returning the contents of the register 12 to the correct value when it deviates from the correct value.
This has an effect similar to that of the logic circuit 8-1 and the logic circuit 9-1 for the logic circuit 1. That is, when the value of register 12 after addition by adder 10 and subtraction by subtracter 11 exceeds M ² , M ² is set in register 12, and similarly, when the value of register 12 becomes negative, Set 0 to register 12. If configured as described above, when the contents of register 12 become larger than the correct value for some reason, at least 2M pieces of sampling data will be "1".
continues, the value in register 12 is corrected to M ² and from then on it shows the correct value, and conversely, when it becomes smaller than the correct value, at least 2M pieces of sampling data consecutively show "0". ”, it will be corrected and the correct value will be shown from then on. There is a very high probability that at least 2M pieces of sampling data will be "1" or "0" consecutively, so even if the contents of register 12 deviate from the correct value, it will be immediately corrected and the correct value will be returned. It comes to show. In the embodiment described above, the number of stages of the shift registers 2-1 and 2-2 is generally set to M+1 stages, but if this is set to 2 ^N +1 stages (N is a positive integer), numerical determination can be simplified. It has a remarkable effect. This will be explained below.

The number of stages of shift registers 2-1 and 2-2 is 2 ^N +
There is no change in the configuration of the first stage. Therefore, explanation will be given using FIGS. 4 and 6. First, in FIG. 4, the number of stages of the shift registers 2-1 and 2-2 is set to 2 ^N +1 stages, so the number of stages of the shift registers 2-1 and 2-2 is
The maximum value of the number of "1"s in the 2 ^N + 1st row is 2 ^N. Therefore, up-down counters 5-1 and 5-
2 only needs to have a capacity of at least N+1 bits, and if the up-down counters 5-1 and 5-2 have a capacity of N+1 bits, when it indicates the maximum value, the MSB is "1" and the other All bits become "0". Next, the maximum value of register 12 is (2 ^N ) ² = at the time when addition and subtraction are completed.
2 ^2N , so the capacity of register 12 is at least
2N+1 bits is enough.

The correspondence between the numerical value of the register 12 and each bit will be explained with reference to FIG. Here, assuming that the capacity of the register 12 is 2N+1 bits, the maximum value of the contents of the register 12 is ^22N as described above, so only the MSB is "1" and all other bits are "0". Also, when (2 ^2N )/2 = 2 ^2N-1 , only the next bit of the MSB is "1" and all other bits are "0", so (2 ^2N )/2 - 1 = 2 ^2N-1 When it is -1, the MSB and the bit following the MSB are "0" and all other bits are "1".
When the double moving average value exceeds 1/2, register 1
When the content of register 12 is (2 ^2N )/2 or more, it corresponds, and when the double moving average value does not exceed 1/2, it corresponds when the content of register 12 is less than (2 ^2N )/2 - 1. If so, the determination by the comparator 13 becomes extremely simple. That is, it is only necessary to pay attention to the MSB of the register 12 and the bit following the MSB. (1) If both the MSB and the bit following the MSB are "0", the double moving average value does not exceed 1/2.

(2) If either the MSB or the next bit of the MSB is "1", the double moving average value exceeds 1/2.

All you have to do is output this information to the output terminal 14. In normal applications, this method can be applied because it is only necessary to know whether the double moving average value exceeds 1/2. Note that the maximum value of the contents of register 12 is determined by completing the addition.
When the subtraction is not yet completed, it becomes 2 ^2N + 2 ^N , which means that the MSB is "1" and the N+1st bit counting from the LSB becomes "1", causing register 12 to overflow. There are no problems, so there is no problem. Also, since the 2 ^N +1st stage B of the shift register 2-1 and the first stage A of the shift register 2-2 always show the same value, the two shift registers 2
-1, 2-2 are combined to make 2 ^2N+1 +1 stage, and
It goes without saying that the same operation will occur even if the value of the 2 ^N+1 +1st stage is connected to the logic circuits 4-1 and 4-2.

Next, FIG. 5 will be explained. In the case of the same figure, if the number of stages of shift registers ^2-1 and 2-2 is 2 ^N +1 stages as in FIG. The maximum number of "1"s is ^2N , and the up-down counters 5-1 and 5-2 only need to have a capacity of at least N+1 bits. Therefore, if the up-down counters 5-1 and 5-2 have a capacity of N+1 bits, the MSB is "1" when it indicates the maximum value.
All other bits are ``0'', and the MSB is ``0'' in all other cases. Therefore, when the number of "1"s in the second to 2 ^N +1 stages of the shift registers 2-1 and 2-2 and the contents of the corresponding up-down counters 5-1 and 5-2 no longer match, It is recovered as follows. That is, when the MSB of the up-down counter 5-1 becomes "1", the logic circuit 8-1 detects this and closes the gate of the logic circuit 9-1 which inputs the output of the logic circuit 4-1. Even if an up-count instruction is issued from the logic circuit 4-1, it does not count, and conversely, when the content of the up-down counter 5-1 is 0, the logic circuit 4-1
Even if a down count instruction is issued from 1, the logic circuit 9
-1 gate is closed to prevent counting. With the above configuration, 2 of shift register 2-1
As mentioned in the explanation of Fig. 3, even if the number of "1" in the 2nd ^to 1st rows and the contents of the up-down counter 5-1 do not match, the system automatically recovers. However, the logic circuit 8-1 is simplified. Further, the logic circuit 8-2 corresponds to the logic circuit 8-1, and the logic circuit 9-2 corresponds to the logic circuit 9-1, and their functions are the same. Furthermore, the logic circuit 15 has the function of automatically restoring the contents of the register 12 to the correct value when it deviates from the correct value for some reason, and inputs M+1 to the shift registers 2-1 and 2-2.
This works in the same way as when using stages.
However, digital comparator 13 and logic circuit 1
5 is simplified. Various configurations of the register 12, digital comparator 13, and logic circuit 15 are possible. An example is shown below.

First, register 12 consists of 2N+2 bits,
Negative numbers are expressed as two's complement numbers, and if the MSB is "1", it is considered negative. Also, overflows and underflows shall be handled appropriately. FIG. 7 shows the correspondence between the numerical value of the register 12 and each bit. The difference from FIG. 6 is that one bit is added as a sign bit, and negative numbers are considered in the form of two's complement.

Next, the function of the logic circuit 15 will be explained. Adder 1
If the sign bit of the MSB of register 12 after addition by 0 and subtraction by subtractor 11 is "1", then
That is, if it is negative, the logic circuit 15 detects this and sets the contents of the register 12 to 0. Similarly, add
If the MSB of register 12 after subtraction is ``0'' and the next bit of the MSB is ``1'', that is, if it exceeds 2 ^2N -1, then set ``0'' to the MSB of register 12 and the next bit of the MSB, and so on. Set all bits to "1". That is, the maximum value is 2 ^2N , but the maximum value set by the logic circuit 15 is 2 ^2N -1. If this is done, an error of 1 will occur in the maximum value, but this is 1/2 ^2N as an error in the double moving average value and is a negligible value. If configured as above, register 12
The maximum value of the contents of is limited to 2 ^2N -1, and the minimum value is limited to 0. Even if the contents of register 12 deviate from the correct value due to some malfunction, shift registers 2-1 and 2-2
can be automatically recovered in the same way as when it is M+1 stage.
When the setting of the logic circuit 15 is completed, the digital comparator 13 checks the bit next to the MSB of the register 12 and if it is "1", the double moving average value is 1/
If the value exceeds 2, and if it is "0", it is assumed that the value does not exceed 1/2 and is output to the output terminal 14. If the contents of the register 12 after addition and subtraction are positive and do not exceed 2 ^2N -1, the logic circuit 15 is not set. Output to.
Since the register 12 takes into account the sign bit and underflow, the order in which subtracter 11 performs subtraction after addition by adder 10 is reversed, and then logic circuit 15 and digital comparator 13 are operated. You can get exactly the same results. Also, after addition or subtraction (or subtraction or addition), when the contents of register 12 exceed 2 ^2N -1, the logic circuit 15
You may also set 2 ^2N to . In this case, the judgment of the digital comparator 13 is based on the register 12.
You will see two bits: the next bit after the MSB and the next bit after the MSB. That is, if either the next bit after the MSB or the next bit after the MSB is "1", the double moving average exceeds 1/2. Otherwise, it is fine as long as it does not exceed 1/2. The above example shows that the register 12 is composed of 2N+2 bits. Next, set register 12 to 2N+1
An example composed of bits will be explained.

FIG. 8 shows the correspondence between the numerical value of the register 12 and each bit. The negative value in register 12 is expressed in two's complement as in the case of Fig. 7, and the MSB is "1".
If so, take it as negative. However, the next bit of MSB is “0”
If so, treat it as correct. After addition and subtraction, register 12
If the MSB is "1" and the next bit after the MSB is "0", that is, if it exceeds 2 ^2N -1, then the logic circuit 15
sets 2 ^2N −1 in register 12. Also, if the MSB of the register 12 is "1" and the next bit of the MSB is "1", that is, if it is negative, 0 is similarly set. If the judgment by the digital comparator 13 is made using the next bit of the MSB, it can be determined whether the double moving average value exceeds 1/2. It is also possible to use a method in which the logic circuit 15 sets 2 ^2N in the register 12 when the contents of the register 12 after addition or subtraction exceeds 2 ^2N -1; in this case, the judgment of the digital comparator 13 is The determination is made using two bits: the MSB and the next bit after the MSB.

As mentioned above, shift registers 2-1 and 2-
If 2 ^N +1 stages are used for 2, the numerical judgment of the logic circuit 15 and the digital comparator 13 becomes extremely simple.

(Effects of the Invention) As explained above, according to the present invention, the double moving average value can be easily obtained digitally by configuring a simple digital circuit, and is therefore useful for LSI implementation.

[Brief explanation of drawings]

1 and 3 are circuit diagrams showing a conventional configuration, FIG. 2 is an explanatory diagram showing the operation of a logic circuit, and FIG. 4 is a circuit diagram showing a first and third embodiment according to the present invention, FIG. 5 is a circuit diagram showing the second and fourth embodiments of the present invention, and FIGS. 6, 7, and 8 are explanatory diagrams showing the correspondence between the numerical values of the register and each bit. 1... Input terminal, 2, 2-1, 2-2... Shift register, 3... Sampling clock oscillator, 4, 4-1, 4-2, 8, 8-1, 8-2,
9, 9-1, 9-2, 15...Logic circuit, 5, 5
-1,5-2...Updown counter, 6,1
3...Digital comparator, 10...Adder, 11...Subtractor, 12...Register, 7,1
4...Output terminal.

Claims (1)

[Claims] 1. A sampling clock oscillator and M+1 (M is a positive integer) written in synchronization with the oscillator.
A stage shift register, an up-down counter that can count up to at least M, and an M+1 stage shift register that does not count when the first stage of the M+1 stage shift register and the data of the M+1 stage where data is finally written are the same value. 1st stage and M+
When the first stage data has different values, two sets of moving average value detection circuits that perform up-counting or down-counting in synchronization with the oscillator according to different states are connected to the M-stage output of the M+1-stage shift register in the previous stage. A register that can store at least M ² +M, an adder that adds the count contents of the up-down counter in the previous stage to the register, and an up-down counter in the latter stage. A subtracter that subtracts the count contents of the register from the register, and a digital comparator, the digital comparator compares the contents of the register with a constant value, and determines whether or not the register exceeds the constant value. Heavy moving average value detection method. 2. Two sets of moving average value detection circuits each having a shift register with 2 ^N +1 stages (N is a positive integer) and an up-down counter with a capacity of N+1 bits are installed in the previous stage.
The output of the ^2N stage of the 2 ^N +1 stage shift register is
2. The double moving average value detection method according to claim 1, which is connected to write to the first stage of a 2 ^N +1 stage shift register. 3 Sampling clock oscillator and M+1 written in synchronization with the oscillator (M is a positive integer)
A stage shift register, an up-down counter that can count up to at least M, and an M+1 stage shift register that does not count when the first stage of the M+1 stage shift register and the data of the M+1 stage where data is finally written are the same value. 1st stage and M+
When the first stage data has different values, up-counting or down-counting is performed in synchronization with the oscillator according to different states, and when the count number of the up-down counter is "M", the up-counting condition is satisfied. Two sets of moving average value detection circuits that do not count up even when the up-down counter reaches "0" and do not count down even if the down-counting conditions are met are connected to the M in the previous stage.
The output of the Mth stage of the +1 stage shift register is transferred to the Mth stage of the subsequent stage.
A register connected to write to the first stage of the +1 stage shift register and capable of storing at least M ² +M, an adder that adds the count contents of the up-down counter in the previous stage to the register, and the count contents of the up-down counter in the subsequent stage. It has a subtractor that subtracts M from the register and a digital comparator, and when the contents of the register are M ² when the subtraction is completed,
If it exceeds, set the contents of the register to M ² ,
If the contents of the register are "0" or less at the time when the subtraction is completed, it is set as "0", and the digital comparator compares the contents of the register with a certain value to determine whether the value exceeds the certain value. Double moving average value detection method. 4 Two sets of moving average value detection circuits each having a shift register stage of 2 ^N +1 stages (N is a positive integer) and an up-down counter having a capacity of N+1 bits are installed in the previous stage.
The output of the ^2N stage of the 2 ^N +1 stage shift register is
^2N + 1-stage shift register, connected to write to the first stage and capable of storing up to 2N+1 registers.
+1 register, and when the MSB of the N+1 bit up-down counter becomes "1", it does not count up even if the up-counting conditions are met;
When each bit of the N+1 bit up-down counter becomes "0", it does not count down even if the down-counting conditions are met, and when the 2N+1 register completes addition or subtraction, the contents of the 2N+1 register become 2 ^2N. Claim 3, characterized in that when the content exceeds -1, the content is set to 2 ^2N -1 or 2 ^2N , and when the content of the 2N+1 register is negative, the content is set to "0". double moving average value detection method.