JPH0145800B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a distributed control electronic switching system in which a plurality of processors share an operating clock, and more particularly to a clock supply circuit of the switching system.

Conventionally, this type of distributed control switch operates with a functional unit 100 having a first processor (CPU) 103 that operates with its own clock generation circuit 102 and its own clock generation circuit 104, as shown in FIG. When the functional units 101 having the second processor (CPU) 105 are located close to each other, there is a drawback that the clocks 102 and 104 may interfere with each other, causing noise in the clocks.

On the other hand, as shown in FIG. 2, a circuit has been devised to supply an operating clock from a common clock source 202 via a clock supply lead 203 to a functional unit 200 having a first processor and a functional unit 201 having a second processor. It was done. However, this scheme has the disadvantage that if clock source 202 fails, all processors will shut down. Therefore, as shown in FIG.
A clock source 301 is provided, and a clock switching circuit 30 is provided.
2 to the processors 200, 2 from either clock source via the clock supply lead 203.
A circuit was considered to supply a clock to 01, but
If the phases of the clocks of the two clock sources are different, the clocks may fluctuate when the clocks are switched, and the processor may stop.

SUMMARY OF THE INVENTION In order to solve these conventional drawbacks, it is an object of the present invention to provide a clock supply circuit for a distributed control electronic exchange that can absorb fluctuations in the operating clock during clock switching by using a phase-locked oscillator circuit. .

In the clock supply circuit in the distributed control type electronic exchange of the present invention, the operating clock of each processor is shared and the clock source of the common clock is configured to be redundant. The present invention is characterized in that, when switching the clock sources, fluctuations in the processor operating clock due to the phase difference between the two clock sources are absorbed by a phase synchronized oscillation circuit.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit diagram showing one embodiment of the present invention, in which a phase synchronized oscillation circuit is constructed of a clock phase comparison circuit and a voltage controlled oscillation circuit (VCO).
A first operating clock source 400 and a second clock source 401 are connected by leads 402 and 403, respectively, to a selector 404 for switching clocks, and the output thereof is connected to one input of a clock phase comparison circuit 405. The output of the clock phase comparison circuit 405 is connected to the voltage control terminal of the voltage controlled oscillation circuit 406.
The output of the clock phase comparator circuit 405 is connected to the other input of the clock phase comparison circuit 405, and the output of the buffer circuit 407 is also connected to the input of the buffer circuit 407. Further, the output of the buffer circuit 407 is sent to the first processor 41 via a lead 408.
0, the clock receiving circuit 411 of the second processor 412, the clock receiving circuit 413 of the third processor 414, etc., respectively.

When the first clock source 400 supplies an operating clock to each processor 410, 412, 414, etc., the clock input from the selector 404 is generated by the clock phase comparison circuit 405 and the voltage controlled oscillation circuit 406. The voltage controlled oscillation circuit 406 is controlled by its output, and the voltage controlled oscillation circuit 406 generates a clock synchronized with the operating clock of the clock source 400, and the clock is sent to each processor 41 via the buffer circuit 407.
A clock is provided at 0,412,414, etc.

Furthermore, when switching from the first clock source 400 to the second clock source 401, if the phases of the clocks generating the two clock sources are different, the output of the clock switching circuit 406 will be as shown in FIG. However, the output waveform is compared with the output of the voltage controlled oscillation circuit 406 by the clock phase comparison circuit 405, and as a result, the output of the voltage controlled oscillation circuit 406 is changed to the clock of the second clock source 401. gradually synchronize. At this time, there is an effect that large fluctuations in pulse width related to the operation of the processor, as seen in the waveform at the time of clock switching in the operating clock switching circuit shown in FIG. 5, can be absorbed.

Furthermore, even if both the first clock source 400 and the second clock source 401 are in trouble and cannot supply clocks during processor operation, the voltage controlled oscillator circuit 406 can continue to supply clocks to the processor. It's also effective.

As explained above, the present invention has the effect of absorbing clock fluctuations during clock switching by using a phase synchronized oscillation circuit in the clock supply circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional clock supply system, Figure 2 is a circuit diagram of a conventional example that is an improvement over the conventional example shown in Figure 1, and Figure 3 is a conventional circuit diagram that is an improvement over the conventional example shown in Figure 2. FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIG. 5 is a waveform diagram at the time of clock switching according to the embodiment of the present invention. 400...first clock source, 401...second clock source
clock source, 402...lead from the first clock source, 403...lead from the second clock source, 404...selector, 405...clock phase comparison circuit, 406...voltage controlled oscillation circuit, 4
07... Buffer circuit, 408... Clock supply lead, 409... Clock receiving circuit of first processor, 410... First processor, 411
...Clock receiving circuit of second processor, 41
2...Second processor, 413...Clock receiving circuit of third processor, 414...Third processor.

Claims (1)

[Claims] 1. In a distributed control electronic exchange controlled by multiple processors, when the operating clock of each processor is shared and the clock source of the common clock is configured to be duplicated, the clock switching circuit and the phase synchronized oscillation circuit are common to the system. 1. A clock supply circuit for a distributed control electronic exchange, characterized in that when the clock source is switched, fluctuations in the processor operating clock due to the phase difference between the two clock sources are absorbed by a phase synchronized oscillation circuit.