JPH0147010B2 - - Google Patents
Info
- Publication number
- JPH0147010B2 JPH0147010B2 JP54106421A JP10642179A JPH0147010B2 JP H0147010 B2 JPH0147010 B2 JP H0147010B2 JP 54106421 A JP54106421 A JP 54106421A JP 10642179 A JP10642179 A JP 10642179A JP H0147010 B2 JPH0147010 B2 JP H0147010B2
- Authority
- JP
- Japan
- Prior art keywords
- groove
- element isolation
- isolation region
- substrate
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
- H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
- H10W10/0124—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves the regions having non-rectangular shapes, e.g. rounded
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は、新しい素子分離方式による半導体装
置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device using a new element isolation method.
従来、MOS型又はバイポーラ型のような集積
回路にあつては、ダイオードやトランジスタ等の
素子それぞれを分離する方式としてＰ−Ｎ接合分
離による方式が一般的であつた。例えば第１図に
示すＮチヤネルMOS型トランジスタを用いたIC
においては、低濃度基板１上にN++拡散層２，
３，４，５をトランジスタのソース・ドレインと
なるように配列し、又トランジスタはゲート絶縁
膜８上にゲート材料９を形成し、この直下がチヤ
ネルとして形成される。この時N++拡散層３，４
を分離するのにＰ型の比較的高濃度のP+ストツ
パ層７が用いられる。これは、N++拡散層３と４
が表面の反転層で短絡することを避けるために、
比較的高濃度として、表面の反転耐圧を上昇させ
るためである。この時P+ストツパ層７の幅は、
N++拡散層３と４の各々の空乏層同志が接触しな
い距離、いわゆるパンチスルーを防ぐ距離とリソ
グラフイ技術の２つによつて制限される。例え
ば、通常用いられる基板濃度が1016／cm3付近では
この距離は5μm以上は必要となり、又リソグラフ
イ技術も5μm以下はむずかしい。従つて、この素
子分離領域に5μm以上要するということはチヤネ
ルの長さが5μmというのに比し余りにも長すぎ、
ICの集積度を低下させる大きな要因となつてい
る。 Conventionally, in integrated circuits such as MOS type or bipolar type, a method using PN junction isolation has been common as a method for isolating elements such as diodes and transistors. For example, an IC using an N-channel MOS transistor as shown in Figure 1.
In this case, an N ++ diffusion layer 2 is formed on a low concentration substrate 1,
3, 4, and 5 are arranged to serve as the source and drain of a transistor, and a gate material 9 is formed on a gate insulating film 8 of the transistor, and a channel is formed directly under this. At this time, N ++ diffusion layer 3, 4
A relatively high concentration P + stopper layer 7 of P type is used to separate the . This is the result of N ++ diffusion layers 3 and 4
To avoid shorting at the surface inversion layer,
This is because the relatively high concentration increases the inversion breakdown voltage of the surface. At this time, the width of P + stopper layer 7 is
It is limited by two factors: the distance at which the depletion layers of the N ++ diffusion layers 3 and 4 do not come into contact with each other, that is, the distance to prevent so-called punch-through, and the lithography technique. For example, when the substrate concentration commonly used is around 10 16 /cm 3 , this distance needs to be 5 μm or more, and it is difficult for lithography technology to reduce the distance to 5 μm or less. Therefore, the fact that this element isolation region requires more than 5 μm is too long compared to the channel length of 5 μm.
This is a major factor in reducing the degree of integration of ICs.
従つて本発明目的は、微細な素子分離領域を得
るにあたり、特別なリソグラフイ技術を用いず
に、この素子分離領域に必要な距離を極限まで低
下させることにより半導体装置のの集積度を向上
させることにある。 Therefore, an object of the present invention is to improve the degree of integration of a semiconductor device by reducing the distance required for a fine element isolation region to the minimum without using any special lithography technology. There is a particular thing.
本発明は、素子を分離させるのに酸化膜の深い
ウオールを形成することにあり、第２図にその製
造工程の一例を示す。 The present invention consists in forming a deep wall of oxide film to separate elements, and an example of the manufacturing process is shown in FIG.
第２図ａにおいて基板１０素子分離領域に相当
する部分に幅10μm、深さ4μm程度のＵ字型の第
１の溝１１を開ける。これはイオンエツチング法
により形成する。あるいはウエツトエツチングを
用いた、Ｖ字型の溝でもよい。次にこれにｂの如
くエピタキシヤル層１２を5μm程度成長させる
と、Ｕ字型の第１の溝が少しだれた形の第２の溝
１３となる。次に表面を1μm相当の熱酸化する
と、表面に酸化膜１４が付着すると同時に幅が狭
くて、酸化膜の深いウオール溝からなる素子分離
領域１５が形成される。そして、ｄの如く基板表
面の酸化膜１４を除去すると、深さが３〜4μm、
幅が１〜2μm程度のウオール溝からなる素子分離
領域１５が残される。このウオール溝が素子分離
領域に用いられる。この酸化膜１４の深さが3μm
程度あると、N++拡散層１６と１７の空乏層同志
がつながることなく、完全な素子分離が可能とな
る。 In FIG. 2a, a U-shaped first groove 11 having a width of about 10 μm and a depth of about 4 μm is formed in a portion of the substrate 10 corresponding to the element isolation region. This is formed by an ion etching method. Alternatively, a V-shaped groove using wet etching may be used. Next, as shown in b, an epitaxial layer 12 is grown to a thickness of about 5 μm, so that the U-shaped first groove becomes a slightly sagging second groove 13. Next, when the surface is thermally oxidized to a thickness equivalent to 1 μm, an oxide film 14 is deposited on the surface, and at the same time, an element isolation region 15 consisting of a narrow and deep wall groove of the oxide film is formed. Then, when the oxide film 14 on the substrate surface is removed as shown in d, the depth becomes 3 to 4 μm.
An element isolation region 15 consisting of a wall groove with a width of about 1 to 2 μm is left. This wall groove is used as an element isolation region. The depth of this oxide film 14 is 3 μm
To a certain extent, the depletion layers of the N ++ diffusion layers 16 and 17 are not connected to each other, allowing complete element isolation.
本発明による方式は、従来素子分離領域に必要
とした5μmの距離を、特別なリソグラフイ技術な
しに1μmに縮小することが可能となり、Ｎ−
MOSICにおいてはその集積度を50％向上するこ
とが可能である。又Ｃ−MOS構造ではＮチヤネ
ルとＰチヤネルの基板の分離に摘要させると、約
２倍近い集積度の向上ができる点でその効果は大
きい。 The method according to the present invention makes it possible to reduce the distance of 5 μm, which was conventionally required for the element isolation region, to 1 μm without special lithography technology.
It is possible to increase the density of MOSIC by 50%. Furthermore, in the C-MOS structure, the separation of the N-channel and P-channel substrates has a great effect in that the degree of integration can be improved by about twice.
また、本発明は微細な素子分離領域得るにあた
り、第１の溝を設けた基板上にエピタキシヤル層
を設け、このエピタキシヤル中に第１の溝よりも
小さい第２の溝を形成し、この第２の溝中に酸化
膜等を埋込み形成している。 Furthermore, in order to obtain a fine element isolation region, the present invention provides an epitaxial layer on a substrate provided with a first groove, forms a second groove smaller than the first groove in this epitaxial layer, and forms a second groove smaller than the first groove. An oxide film or the like is buried in the second trench.
つまり、基板上のエピタキシヤル層が基板の段
差を反映した形で成長するので、そのエピタキシ
ヤル層にも基板に設けられた第１の溝よりも小さ
い第２の溝が形成されるのである。 In other words, since the epitaxial layer on the substrate grows in a manner that reflects the step difference in the substrate, a second groove smaller than the first groove provided in the substrate is also formed in the epitaxial layer.
このように、本発明は歩留りが低下しやすい微
細なパターン、つまり素子分離領域を作るための
特別なリソグラフイ技術を使用しなくて、上述の
ような信頼性の良い非常に簡単な方法で極めて微
細な素子分離領域を得るために最良な方法を示し
ている。 As described above, the present invention does not require the use of special lithography techniques for creating fine patterns that tend to reduce yield, that is, element isolation regions, and can be achieved using the highly reliable and extremely simple method described above. The best method for obtaining fine isolation regions is shown.
第１図は従来の素子分離領域の構造を示す主要
断面図、第２図は本発明の素子分離領域の構造を
示す工程断面図。
１２……エピタキシヤル層、１４……酸化膜、
１５……素子分離領域。
FIG. 1 is a main sectional view showing the structure of a conventional element isolation region, and FIG. 2 is a process sectional view showing the structure of the element isolation region of the present invention. 12...Epitaxial layer, 14...Oxide film,
15...Element isolation region.
Claims (1)
子分離領域を形成する半導体装置の製造方法にお
いて、前記基板を選択的にエツチング除去して第
１の溝を形成する工程、前記基板上に前記エピタ
キシヤル層を形成し、前記第１の溝上方の前記エ
ピタキシヤル層表面部に前記第１の溝より微細な
幅を持つ第２の溝を設ける工程、前記第２の溝中
に酸化膜を埋め込み形成し、素子分離領域とする
工程を有することを特徴とする半導体装置の製造
方法。1. In a method of manufacturing a semiconductor device in which an element isolation region is formed in an epitaxial layer provided on a substrate, a step of selectively etching away the substrate to form a first groove; a step of forming a second groove having a finer width than the first groove in a surface portion of the epitaxial layer above the first groove, embedding an oxide film in the second groove; 1. A method of manufacturing a semiconductor device, comprising a step of forming an element isolation region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10642179A JPS5630737A (en) | 1979-08-21 | 1979-08-21 | Semiconductor ic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10642179A JPS5630737A (en) | 1979-08-21 | 1979-08-21 | Semiconductor ic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5630737A JPS5630737A (en) | 1981-03-27 |
| JPH0147010B2 true JPH0147010B2 (en) | 1989-10-12 |
Family
ID=14433191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10642179A Granted JPS5630737A (en) | 1979-08-21 | 1979-08-21 | Semiconductor ic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5630737A (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5226182A (en) * | 1975-08-25 | 1977-02-26 | Hitachi Ltd | Manufacturing method of semi-conductor unit |
| JPS5260581A (en) * | 1975-11-14 | 1977-05-19 | Agency Of Ind Science & Technol | Semiconductor device |
| JPS5456357A (en) * | 1977-10-14 | 1979-05-07 | Hitachi Ltd | Production of semiconductor device |
| JPS5499575U (en) * | 1977-12-26 | 1979-07-13 | ||
| JPS5457877A (en) * | 1978-08-28 | 1979-05-10 | Hitachi Ltd | Semiconductor device |
-
1979
- 1979-08-21 JP JP10642179A patent/JPS5630737A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5630737A (en) | 1981-03-27 |
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