JPH0147065B2 - - Google Patents

Description

Detailed description of the invention [Technical field to which the invention pertains] This invention relates to a waveform in which a first level of unit time width T is repeated twice with a second level of time width T in between, and a first level of unit time width 3T. For each of the level waveforms, the total time width with a second level of time width T
Serial data reading circuit for converting serial data input using 4T RZ signal as one logical value and the other logical value of binary logic into NRZ pulse signal that can be determined as 0 or 1 using a normal circuit. Regarding.

[Prior art and its problems]

Conventionally, in serial data transmission, the first, second, and third
The 1 and 0 signals defined as shown in the figure are combined as shown in each figure. Of these, Figure 1 shows whether, for example, high-level magnetization is in the first half or the second half within a predetermined time width.
Binary logic 0 (Figure 1a) or 1 (Figure 1b)
This is the basic method when magnetic tape is used as a signal medium. Figure 2 shows the first level of the unit time width T and the first level of the time width 2T, each accompanied by a second level of the time width T, of binary logic 0.
(Fig. 2a) or 1 (Fig. 2b), and is a generally used method. Third
The figure shows a method devised by IBM and widely used. Binary logic 0 and 1 correspond to the first level in the first quarter and the second level in the last three quarters of the given time width. (Fig. 3a), and the front 3/4 corresponds to the first level and the rear 1/4 corresponds to the second level (Fig. 3b). In the case of Fig. 1, the start pulse signal to indicate the start of the data signal must be distinguished from the data as a specific pattern that does not appear in the data, as shown in Fig. 4, for example. There is a drawback that the start pulse signal must be long. Furthermore, a special circuit is required to determine a long start pulse signal, which increases the complexity of the circuit. In the case of Figure 2, there is a drawback that the length of the entire data depends on the content of the transmission, and may become longer or shorter (Figure 2c).
reference). In the case of Figure 3, when this signal is used for automatic monitoring of the presence or absence of fire in each room of a high-rise building [for example, "Ministerial Ordinance Establishing Technical Standards for Fire Alarm Equipment" (Effective on 1 day)
The time required for automatic monitoring from the start to the completion of one round of electronic scanning of the monitored object is specified to be within 5 seconds], and the data from each room detector is returned in synchronization with the binary logic signal. Because it is normal, the time range
Only 1 bit is sent during 4T (3rd
(See Figure C), this signal can be said to be inefficient in terms of efficiency because it takes a long time to perform one round of electronic scanning when there are many objects to be automatically monitored.

[Purpose of the invention]

The purpose of this invention is to be able to easily attach a short start pulse signal, to prevent the overall length of the data from becoming longer or shorter depending on the content of the transmission, and to be able to be used efficiently for synchronizing replies in the case of automatic monitoring. Serial data input consisting of a combination of binary logic signals using RZ pulses is input to 0, 1 using a normal circuit.
It is an object of the present invention to provide a serial data reading circuit that can convert into an NRZ signal that can be determined.

[Key points of the invention]

In this invention, for each of the waveform in which the first level of unit time width T is repeated twice with the second level of time width T in between, and the waveform of the first level of time width 3T, Total time span with 2 levels
The means for charging or discharging a capacitor in synchronization with the serial data input using the 4T RZ signal as one logical value and the other logical value of binary logic, respectively, mainly uses an R-S flip-flop circuit, a Schmitt trigger circuit, etc. By combining the logic operations of the circuits, the logic signal with the recess in the center generates a short pulse and the logic signal with a wide pulse at the timing of the central recess, and the other logic signal generates a short pulse and a wide pulse at the timing near the center of the first level, respectively. read as,
The attempt was made to obtain an NRZ signal corresponding to serial data input by using these as a clock for a D flip-flop circuit.

[Embodiments of the invention]

Embodiments of a serial data reading circuit according to the present invention will be described below with reference to the drawings.

FIG. 5a shows a "0" signal 100 according to the present invention;
Similarly, b indicates the “1” signal 101. The former is an RZ pulse waveform with a total time width of 4T, in which a first level with a unit time width T and a second level lower than the first level with a time width T are repeated twice in this order, and the latter is an RZ pulse waveform with a total time width of 3T. the first level and the second level of time width T;
This is an RZ pulse waveform with a time width of 4T consisting of a level. FIG. 5c is an example of serial data in which these RZ pulse waveforms are combined as a binary logic signal.
As will be explained in detail below, the reading of these data according to the present invention is performed with the "0" signal 100 at the timing of the central recess and the "1" signal 101 at the timing near the center of the first level.

FIG. 6 is a circuit diagram of the present invention, and FIG. 7 is a diagram showing its operating waveforms. In Fig. 6, input terminal 1 is connected to inverter 2, whose output is R-
S flip-flop (hereinafter abbreviated as FF)
Connected to the S input side of 3. The output Q of the R-S•FF 3 is connected to one end of a resistor 5 via a tristate 4 . The other end of the resistor 5 is connected to a connection point A between the resistor 6 and the capacitor 7. A resistor 6 and a capacitor 7 are connected in series between the +V power supply and GND. Schmitt trigger 8 (high level Vh, low level
The input of Vl) is connected to the connection point A of the resistor 6 and capacitor 7, and its output is passed through the inverter 9.
It is connected to the input of the NAND gate 10 and the C input of the DFF 11. The output side of the inverter 2 is connected to the other input of the NAND gate 10. The output of the NAND gate 10 is connected to the R input side of the R-S•FF3. Further, the output of the inverter 2 is connected to the D input of the D/FF 11 via the inverter 12. Supports serial data input
The NRZ signal is obtained from terminal 13.

In the circuit configured as described above, suppose that the serial data input shown in FIG. 7a is applied to the input terminal 1, for example. When the input becomes high level at time _t1 when the "0" signal 100 starts, R-S.
FF3 is set, tristate 4 becomes high impedance, and capacitor 7 begins to be charged via resistor 6. The charging speed is capacitor 7
It is desirable to set the charging voltage to the high level Vh of the Schmitt trigger 8 at approximately 1.5T from the start of charging. Charging voltage of capacitor 7
When Vc reaches the high level Vh of the Schmitt trigger 8, the output of the NAND gate 10 becomes low level and the R-S•FF 3 is reset. For this reason,
The tri-state 4 is turned ON, the capacitor 7 is discharged via the resistor 5, and when its charging voltage Vc reaches the low level Vl of the Schmitt trigger 8, the output of the Schmitt trigger 8 via the inverter 9 becomes low level. The output via this inverter 9 also serves as the clock for the D/FF 11, and as shown in FIG. Until then, one item is output. The generation of this clock means that the "0" signal 100 during serial data input is read. The clock pulse width in this case is
It is determined by the high level Vh and low level Vl of the Schmitt trigger 8 and the discharge time constant of the capacitor 7. Also, due to the action of D・FF11, terminal 1
3 is output as 0.

This circuit operates in much the same way after time t ₂ when the "1" signal 101 begins in FIG. 7, but in this case, the capacitor 7 is When the charging voltage Vc reaches the high level Vh of the Schmitt trigger 8, the clock pulse starts to be output, and the second of the "1" signal 101
Charging voltage of capacitor 7 during discharging when level
Since Vc finishes outputting when it reaches the low level Vl of the Schmitt trigger 8, the width of the clock pulse becomes wider than when it is the "0" signal 100. In d of the same figure, when two "1" signals 101 are in succession, the terminal 13 is
It was shown that a signal equivalent to 1 can be obtained continuously without dropping to 0.

In this manner, according to the present invention, an RZ signal can be converted and outputted into an NRZ signal by utilizing the charging and discharging of the capacitor 7.

FIG. 8 is a circuit diagram of a second embodiment of the present invention, in which constant current sources 21 and 2 are used instead of the resistors 5 and 6 in FIG.
This is an example using 2. When the constant current sources 21 and 22 and the input lines 23 and 24 are set to high level, the current is turned on, and when set to the low level, the current is turned off.

FIG. 9 is a circuit diagram of a third embodiment of this invention,
When the Q output of R-S・FF3 in FIG. 6 becomes high level, the NMOS transistor 31
OFF, and charging of capacitor 7 begins. OR gate 33 functions in the same way as NAND gate 10 which receives input via inverter 2 and input via inverter 9 in FIG.
The inverter 32 has the same effect on the DFF 11 as the inverter 9 in FIG.

FIG. 10 is a circuit diagram of a fourth embodiment of this invention,
FIG. 11 is a diagram showing its operating waveforms. This circuit differs from the first embodiment shown in FIG. 6 in that the tristate 4 is replaced by a transistor 41 connected to the base of a resistor 42, and the inverter 9 is omitted. The capacitor 7 of the first embodiment starts charging when the signal at the input terminal 1 becomes high level, and the high level Vh of the Schmitt trigger 8 starts discharging.
Clock 1 is applied between the low level Vl during discharge and
In contrast, in the fourth embodiment,
Basically, the capacitor 7 is charged to +V, and the capacitor 7 starts discharging when the signal at the input terminal 1 becomes high level, and starts recharging when the Schmitt trigger 8 becomes low level Vl during discharging. One clock is generated until the next high level Vh is reached.

Now, in the circuit of Fig. 10, for example, Fig. 11a
Suppose that the serial data input shown in is applied from input terminal 1. Time t ₁₁ when “0” signal 100 starts
When the input becomes high level, R-S•FF3 is set and the transistor 41 becomes conductive. Therefore, the capacitor 7 that had been charged to +V starts discharging through the transistor 41 via the resistor 5. The discharging speed is desirably set so that the charging voltage +V of the capacitor 7 reaches the low level Vl of the Schmitt trigger 8 at approximately 1.5 T from the start of discharging. When the voltage Vc of the capacitor 7 reaches the low level Vl of the Schmitt trigger 8,
The output of NAND gate 10 becomes low level and R
-S.FF3 is reset. Therefore, the transistor 41 is turned OFF, and the capacitor 7 completely changes and begins to be charged by the +V power supply. Charging is performed via the resistor 6, and when the voltage Vc reaches the high level Vh of the Schmitt trigger 8, the output of the Schmitt trigger 8 becomes high level. One clock signal for the D/FF 11 is generated while the input of the shot trigger 8 goes from low level Vl to high level Vh. The generation of this clock means that the serial data input "0" signal 100 is read. The pulse width of the clock in this case is determined by the high level Vh and low level Vl of the shot trigger 8 and the charging time constant of the capacitor 7. In addition, due to the action of D・FF11,
0 is output to the terminal 13.

This circuit operates in almost the same way even after the time _t12 when the "1" signal 101 in FIG. 11 starts, but
In this case, while the first level of the "1" signal 101 is still present, the charging voltage Vc of the capacitor 7 reaches the low level Vl of the Schmitt trigger 8 and starts outputting the clock, and the recharging voltage of the capacitor 7 becomes "1". When the signal 101 is at the second level, the charging voltage Vc of the capacitor 7 reaches the high level Vh of the Schmitt trigger 8 and ends, so that the width of the clock pulse is wider than when the signal 100 is "0". Due to the action of D・FF11,
A signal equivalent to 1 is obtained at the terminal 13.

FIG. 12 is a circuit diagram in which a circuit capable of receiving serial data input with a start pulse and generating an initial reset signal is added to the circuit of the first embodiment shown in FIG. 6. The circuit that generates the initial reset signal is D・FF51 in the figure.
It is composed of a NAND gate 52 and a NOR gate 53. FIG. 13 is a diagram schematically showing the operation of the circuit shown in FIG. 12. The first level of time width T and the first level of time width 3T are the second level of time width T.
It is shown that an initial reset signal can be obtained by providing a serial data input with a short simple start pulse of a total duration of 6T, followed by a second level of duration T at the end.

The above is shown in Figure 5a as "0" and "1" signals.
As shown in FIG. 14a, the second level with the unit time width T and the first level higher than the second level with the time width T are repeated twice in this order over the entire time. Assuming that the RZ pulse waveform with a width of 4T is a "0" signal 200, as shown in Figure 14b,
The circuit shown in the above embodiment can also be used in the case of serial data input in which the "1" signal 201 is an RZ pulse waveform with a time width of 4T, which is composed of the second level with a time width T and the first level with a time width 3T. It is easy to understand that it works in the same way and outputs an NRZ signal.

Further, when the "1" and "0" signals according to the present invention are used, the data length does not change depending on the transmission content.

Note that the above explanation uses the "0" and "1" signals as shown in Fig. 5 a and b or Fig. 14 a and b, respectively.
However, it goes without saying that the "0" and "1" signals may be defined in the opposite manner.

〔Effect of the invention〕

In this invention, for each of the waveform in which the first level of the unit time width T is repeated twice with the second level of the time width T in between, and the waveform of the first level of the time width 3T, the second level of the time width T Total time span with level
R-S/FF circuits, Schmitt trigger circuits, etc. are mainly used as means for charging or discharging capacitors in synchronization with serial data input using 4T RZ signals as one logical value and the other logical value of binary logic, respectively. By combining the logical operations of the circuit, the logic signal with the recess in the center generates a short pulse and the logic signal with a wide pulse at the timing of the central recess, and the other logic signal generates a short pulse and a wide pulse at the timing near the center of the first level, respectively. Since we decided to obtain the NRZ signal by reading it as pulses and using these as a clock for the D/FF circuit, we can easily add a short start pulse signal, and the overall length of the data can be made longer depending on the content being transmitted. NRZ is a serial data input that combines binary logic signals with RZ pulses that do not become long or short and can be efficiently used for synchronizing responses in automatic monitoring, and can be judged as 0 or 1 using a normal circuit. We were able to provide a serial data reading circuit that converts the data into signals.

[Brief explanation of drawings]

Figures 1, 2, and 3 are diagrams showing conventional 1,0 signals and examples of serial data using them; Figure 4 is a diagram of an example of a start pulse signal used for the serial data in Figure 1; Figure 5 shows "1" according to this invention,
6 is a circuit diagram of the first embodiment of the present invention, FIG. 7 is an operation waveform diagram of the circuit of FIG. 6, and FIGS. 8, 9, and 10 are diagrams showing the "0" signal. Circuit diagrams of the second, third, and fourth embodiments of the invention, FIG. 11 is an operating waveform diagram of the circuit of FIG. 10, and FIG. 12 is a circuit diagram that receives serial data input with a start pulse and generates an initial reset signal. FIG. 13 is a schematic diagram of the operating waveform of the circuit shown in FIG. 12, and FIG. 14 shows "1" and "0" signals according to the invention, which are different from those shown in FIG. 5. FIG. 100,200..."0" signal, 101,201
..."1" signal, 3...R-S flip-flop, 4
...Tri-state, 8...Schmitt trigger, 1
1, 51...D flip-flop, 21, 22...constant current source, 31...NMOS transistor, 41...transistor.

Claims (1)

[Claims] 1 The first level of unit time width T is the second level of time width T
For each waveform that is repeated twice with the level in between and the first level waveform with a time width of 3T, the RZ signal with a total time width of 4T accompanied by the second level with a time width of T is applied to each one of the binary logics. a flip-flop circuit set by a first level of the serial data input used as the value and the other logical value;
charging/discharging means for charging or discharging a capacitor when the flip-flop circuit is set and discharging or charging the capacitor when the flip-flop circuit is reset; and an output when the voltage of the capacitor reaches a first threshold. a Schmitt trigger circuit that generates an output and makes the output disappear when a second threshold is reached; and a Schmitt trigger circuit that detects that the serial data input is at a second level and outputs the output. A serial data reading circuit comprising: a gate circuit that resets the flip-flop circuit when the serial data is generated; and a D flip-flop circuit that receives the serial data input and uses the output of the Schmit trigger circuit as a clock.