JPH01470A - speed detection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed detection circuit that detects the speed of a vehicle, etc., compares it with a predetermined reference speed, and outputs a discrimination signal.

[Conventional technology]

A conventional speed detection circuit is configured as shown in FIG. 5, for example.

The figure shows the configuration of a low-speed driving recorder for an automobile, including an axle rotation detector 8, a waveform shaping circuit 9 including a differential circuit with a capacitor C8 and a resistor R1 as required, an integrating circuit with a resistor R9° and a capacitor 06'. f-V conversion circuit 1 consisting of
0 and a comparator CP are connected in series.

The comparison circuit 11 includes a comparator CP, and the normal input of the comparator CP is connected to the output of the fV conversion circuit 10 via a resistor R11, and is also connected to the power supply Vcc via a resistor R1□. Ru. Further, a reference voltage V2 is applied to the inverting input, which is grounded via a resistor R13. Furthermore, a resistor RI4 is connected between the output and the normal rotation input.

This comparator CP.

The base of the drive transistor Q4 is connected to the output of
An electromagnetic coil 12 for creating a record chart is connected to the collector output.

In this configuration, the axle rotation detector 8 detects the rotation of the axle as the vehicle travels and generates a speed signal whose frequency is proportional to the vehicle speed.

is emitted.

This speed signal "," is given as an input to the waveform shaping circuit 9, and is manually inputted to the waveform shaping circuit 9 via a differential signal f2 obtained by being differentiated by a differentiating circuit including a capacitor C3 and a resistor R1. Therefore, its output is f2 A shaped speed signal (pulse signal) f proportional to the vehicle speed is obtained by the steering frequency.

The shaping speed signal f3 thus obtained is then r-
The integrating capacitor C is given as an input to the v conversion circuit 10.
is applied between both terminals of 6. As already mentioned, the repetition frequency of the shaped speed signal f3 as the output of the waveform shaping circuit 9, that is, the number of pulses emitted per unit time, is proportional to the vehicle speed.

Therefore, on the basis of this shaped speed signal f3, a voltage (2) proportional to the vehicle speed is obtained across the integrating capacitor C6.

A voltage proportional to the vehicle speed obtained by the conversion capacitor C6 is applied to the normal rotation input terminal in1 of the comparator CP of the comparison circuit 11 via the resistor R11. Further, a reference voltage 2 determined by a setting resistor RI3 is applied to the inverting input terminal in2 of the comparator CP. This reference voltage v
2 is the minimum vehicle speed you wish to detect, for example 1 to 3kl+
The voltage value is set to correspond to a vehicle speed of /h.

The voltage V obtained at the output terminal out of the comparator CP becomes a constant high level when vI exceeds v2, and Vl
is set to a constant low level below V2. Therefore, by appropriately setting the reference voltage v2 corresponding to the minimum vehicle speed, when the vehicle speed is higher than the predetermined reference voltage 72, a predetermined output is applied to the output terminal OUT of the comparator circuit 11 (comparator CP+). You can get the signal ■.

Therefore, by turning on the driving transistor Q4 and driving the electromagnetic coil 12 when the output signal v3 is generated, it is possible to record the running on the recording chart paper at a vehicle speed higher than the minimum vehicle speed.

Note that the resistor R+a increases the output voltage of the comparator circuit 11 due to the ripple component generated in the output voltage vl of the r-v conversion circuit 10;
connected to prevent oscillation. That is, the output voltage V with respect to the input voltage V is caused by the resistor R14.
The output characteristics of V are provided with hysteresis to prevent the output voltage V from oscillating.

As the recording paper used in this case, for example, the one shown in FIG. 6 is used. The vehicle speed is graduated from the center in the diametrical direction, and the time is graduated in the circumferential direction at the corresponding vehicle speed position.

When the vehicle is running at a speed higher than the minimum vehicle speed, the pen of the recorder connected to the output terminal of the comparator circuit 11 is driven and scans the recording paper, and the running state of the vehicle is recorded as shown in FIG. It appears like a drawn figure.

[Problem that the invention seeks to solve]

In such a conventional circuit, a vehicle travels at l km/h.
At a low running speed of ~3 km/h, the ripple component of the voltage vI is large, so it is necessary to increase the hysteresis of the on/off operating points of the comparison circuit tt using the resistor R14. However, if the output characteristics have hysteresis and the hysteresis is made too large, speed detection accuracy will deteriorate. On the other hand, to reduce this ripple component,
Although it is possible to increase the capacitance of the integrating capacitor C1, the responsiveness deteriorates. Further, due to the small output voltage of the f-V conversion circuit IO, an extremely low frequency signal is generated even in a state where the rotation is stopped and the speed is zero, making it unsuitable for use in integrating detected speeds.

[Means for solving problems]

In order to solve the above problems, the speed detection circuit according to the present invention includes a rotation speed detection means for obtaining a pulse signal train of a frequency corresponding to the rotation speed of a rotating body, and a pulse signal train inputted from the rotation speed detection means. and first and second pulse signals that compare the pulse period of the pulse signal train with a first reference pulse period and a second reference pulse period shorter than the first reference pulse period and output detection signals thereof, respectively. A pulse period detecting means and each detection signal of the first and second pulse period detecting means are inputted, and the first and second pulse period detecting means of the pulse signal train are inputted.
and a discrimination signal output means for outputting a discrimination signal at a frequency corresponding to the reference pulse period, and the discrimination signal output means detects the discrimination signal by each detection signal from the first and second pulse period detection means. It is designed to have hysteresis.

[For production]

In the above configuration, the rotation speed detecting means outputs a pulse signal train having a frequency corresponding to the rotation speed of the rotating body, and a pulse signal train whose pulse period changes depending on the rotation speed is obtained.

This pulse signal train is input to the first and second pulse period detection means and compared with the first reference pulse period and the second reference pulse period set respectively. At this time, the second reference pulse period is set shorter than the first reference pulse period. Therefore, when the pulse period of the pulse signal train becomes shorter, that is, when the speed of the rotating body becomes faster,
First, the first pulse period detection means outputs a detection signal indicating that the speed has become faster than the reference speed corresponding to the reference pulse period. When the speed further increases and the pulse period of the pulse signal train becomes shorter, the second pulse period detection means outputs a detection signal indicating that the speed has become faster than the reference speed corresponding to the reference pulse period. The discrimination signal output means inputs each detection signal, and detects when the speed of the rotating body is in the increasing direction and when the pulse signal train reaches the second reference pulse period according to the detection signal of the first pulse period detection means. Outputs a discrimination signal.

Further, when the speed of the rotating means is in the direction of deceleration, the discrimination signal output means outputs a discrimination signal when the pulse signal train reaches the first reference pulse period according to the detection signal of the first pulse period detection means. .

That is, the discrimination signal output from the discrimination signal output means has hysteresis.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example applied to a low-speed driving recorder for a vehicle, similar to the conventional example shown in FIG. The rotation speed detection means 1 is composed of a rotation sensor 11 and a waveform shaping circuit 12 including a transistor Q1. The rotation sensor 11 is composed of a pickup coil, a photo coupler, etc., and detects rotation of the axle. Waveform shaping circuit 1□ is rotation sensor 1. Waveform-shapes the output of
As shown in FIG. 2(a), a pulse signal train of a frequency corresponding to the rotational speed is output. As shown in the figure, the pulse period of the pulse signal train becomes shorter as the speed increases.

The first pulse period detection means 2 includes a monostable multi-by-break (hereinafter referred to as O3M) 2I, NAND circuits 2□ to 24, and an OR circuit 2. It consists of OS M2+
After inversion, the terminal P of 2. is connected to the OR circuit 2. The output of the waveform shaping circuit 1□ is inputted through the terminal P3, and the power supply Vcc is supplied to the terminal P3. Also, a resistor R1 and a capacitor C1 are connected in series to the terminals P+ and Pz, and the output Q of the terminal P is connected to the NAND
The circuit 21 is manually powered. The output of the NAND circuit 23 is input to a NAND circuit 24 having an inverter configuration, and its output becomes a reset signal R. Also, the terminal P4 has an OR circuit 2S.
A power supply Vcc is supplied through the terminal.

The second pulse period detection means 3 is 03M3. , NAND
Circuit 3□, 3. and two D-type flip-flow knobs (hereinafter referred to as DFF) 34 and 33, and an OR circuit 36. Terminal P of OS M3l.

and P5 is a power supply and an inverted one and then an OR circuit 3. The terminal P4 is connected to the output of the waveform shaping circuit 1□ via the OR circuit 36, and the terminal P4 is connected to the power supply via the OR circuit 36. Furthermore, a series circuit of a resistor R2 and a capacitor C2 is connected to the terminals P+ and Pz. Further, the output Q of the terminal P is input to the NAND circuit 3□, and the output is sent to each DFF 34 . 3
It is input to the terminal Pff (clock input CP) of No. 5. The negative input of the NAND circuit 3□ is the waveform shaping circuit 1□
connected to the output of

Also DFF3. The terminal Ps (data input D) of the
Vcc, and the output Q of the terminal P is connected to the resistors R3 and R4.
The data is manually inputted to the terminal PS (data input D) of the DFF3s via the terminal PS (data input D). DFF34. Each terminal P4 (clear manual power CL) of 3S is connected to the output port of terminal P7 of osM3+, and each terminal P6 (preset input PR) is grounded. Also, a set signal S is sent from terminal P2 (output port) of DFF3s through capacitor C3 and resistor R6.
Output. Further, the connection point between the capacitor C3 and the resistor R6 is connected to the power supply cc via the resistor R3.

The discrimination signal output means 4 is an RS flip-flop (hereinafter referred to as R3FF) composed of NAND circuits 4□ and 43.
41, NAND circuit 2. The reset signal R that is the output of R3FF4. Terminal Pg of the NAND circuit 42 of
(reset power R3), and the set signal S from the capacitor C3 is input to the NAND circuit 4. Terminal P, (
set human power S).

5 is a power-on reset circuit consisting of a transistor Q2, resistors R, , R, and a capacitor C4. The collector and base of the transistor Q2 are connected to the power supply Vcc, and the collector output is connected to the output of the waveform shaping circuit 1□ and Each is connected to the input of a NAND circuit 2□ having an inverter configuration. Also, the output of NAND circuit 2□ is NAND circuit 2
Connected to one input of 3.

Reference numeral 6 denotes a drive circuit consisting of a transistor Q3, and its base input receives the running signal A, which is the terminal P3 of R3FF4+, manually.

7 is an electromagnetic coil driven by the drive circuit 6;
When the vehicle is driven, it operates to record the running record on the chart paper shown in FIG. 6.

Next, we will discuss the basic operation of 03M2+ and 3+ in the third section.
This will be explained with reference to the timing charts shown in FIG. 3 (al to tel). When the terminal P is at the H level as shown in FIG. Or the terminal P shown in the same figure (b).

The falling edge of the input pulse applied to the same figure (e
), a rectangular wave signal is output to the terminal P (output Q) with a time width of a predetermined period T. The predetermined period T is the terminal P, , P2
It is set by the time constant RC of the resistor R connected to the capacitor C, and T=RC. At this time, as shown in the figure (dl), the terminal P2 is discharged by the input pulse and then charged with the RC time constant.The output Q rises during this discharge, and when the terminal Pt rises to a predetermined level. When the period (time width) of the input pulse is shorter than the output period T as shown at t in the figure (a), the output Q is the same as that of the last input pulse. A rectangular wave signal is output from the rise to period T. Here, the time constant "rz (RZ, C1) of the resistor R2 and capacitor C2 connected to osM3+ in FIG. 1 is 03M2.
Set it to be smaller than the time constant 'r+ (R+, C+).

Also DFF34. 35 is as shown in the truth value in Figure 4,
At the rising edge of the clock signal cp at the terminal P, data input from the terminal P is taken in, and at the falling edge of the clock signal cp, the data input from the terminal P is outputted to the terminal P+-Pz. Also, clear input CL of terminal P4
When the preset input PR of the terminal P6 and the preset input PR of the terminal P6 are both not at L level, the terminal PI (output Q) and the terminal Pz (output Q) are as shown in the figure.

Next, the operation shown in FIG. 1 will be explained with reference to timing charts shown in FIG. 2 (al to (g)).

First, when the power supply Vcc is turned on, the collector output of the transistor Q2 of the power-on reset circuit 5 is connected to the capacitor Ca.
, is output for a predetermined period of time until it is charged. Therefore, the output of the NAND circuit 22 (FIG. 2 (j)) becomes L level, the output of the NAND circuit 23 becomes H level, and the NAND circuit 23 becomes H level.
ND circuit 2. The output (FIG. 2(k)), that is, the reset signal R becomes L level.

On the other hand, the set signal S (Fig. 2 (1)) goes to level ■ (by the power supply Vcc), and R3FF4. is reset and the output of its terminal P (Fig. 2 (t)) goes to L level. After a predetermined period of time has passed, the voltage of the capacitor C4 rises, turning on the transistor Q2, and its collector output goes to the L level.Therefore, the output of the NAND circuit 2□ goes to the H level, but each of the terminals P, , P, of the 05M2. Since H level is input to each pulse input, terminal P
The output Q of h (FIG. 2(b)) is at L level.

Therefore, the output of the NAND circuit 23 becomes H level, and the NAND circuit 23 becomes H level.
Since the output of the ND circuit 24, that is, the reset signal R, maintains the L level, the running signal A, which is the output of R3FF41,
(FIG. 2(k)) maintains the L level. Therefore, the transistor Q3 of the drive circuit 6 is in an off state, and the electromagnetic coil 7 is not driven.

When the vehicle starts running in the power-on state and the rotating body starts rotating, the rotation sensor 1. detects this, and the waveform shaping circuit 1□ shapes the detected signal as shown in Figure 2 (a).
A pulse signal train shown in l is output. This pulse signal train is input to each terminal P of 03M2+, 3i, and the 03M
The output Q of each terminal P6 of 2+ and 3+ outputs a rectangular wave signal of period T+ and Tz, respectively, by the rising edge of the pulse signal train as shown in FIG. The output port of , becomes the inverted output of the output Q (Fig. 2 (d)).The rotation of the rotating body is small and the pulse period of the pulse signal train is the reference pulse period T.
,, when it is longer than T2, <03M21 as shown in Fig. 2
．． 3. The output Q becomes L level after each period T, , T, and is triggered again at the rising edge of the next pulse signal train to output a rectangular wave. When the pulse signal train is in such a pulse period, the output Q of 03M31 is a rectangular wave signal, and the output of the waveform shaping circuit 1□ is also a pulse signal train, so N
The output of the AND circuit 3□ is the inverted output of the waveform shaping circuit 1□, and the output of the NAND circuit 33 is DF
F34.3. The terminal P3 (clock input CP) has the same waveform as the output of the waveform shaping circuit 1□ as shown in FIG. In addition, the data input to the terminal P of the DFF34 is at the H level because it is at the power supply level, and the present input PR of the 01 chip P6 is at the L level.
The clearing manual CL, that is, the output page of OS M 3 + is the inverted pulse of the output Q as shown in FIG. 2 (dl). Therefore, from the truth value in FIG.
It is at L level as shown in the figure (fl).

As a result, the L level is input to the data input terminal P of DFF3s, and the same signal as DFF3° is input to the preset input PR, clock input CP, and clear input CL, so that the output of terminal P2 The mouth is shown in Figure 2 (h).
It is at H level. On the other hand, the output Q of the terminal P6 of osM2+ is a rectangular wave signal of period T1, so the output of the NAND circuit 24 is as shown in FIG.
This is the same signal as the output Q of M 2 +. Therefore, when the pulse signal train is tl, the cent signal S is maintained at the H level by the voltage aVcc as shown in FIG.
4. The output (travel signal A) maintains the L level as shown in FIG. 2 (1), the transistor Q3 is not driven, and the electromagnetic coil 7 is not driven.

Next, as shown at t2 in FIG. 2, when the rotation speed increases and the period of the pulse signal train becomes shorter than the first reference pulse period T+ (=RI, CI) set by the OS M 21, the above reference operation is performed. As shown in FIG. 2, the output Q is always at the l level as shown in bl. Therefore, the output of the NAND circuit 24 (FIG. 2 (k)) is also at the H level, but the outputs Q and ζ of the osM3+ are at the t, The state is the same, and the output ζ of DFF3s maintains the H level (Fig. 2 (h)).Therefore, in order to maintain the L level without inverting the output of R3FF4, the drive circuit 6 and the electromagnetic coil 7 is not driven.

Furthermore, as shown in FIG. 2, when the rotation speed increases and the period of the pulse signal train becomes shorter than the second reference pulse period Tz (=Rz, Cz) set in 03M3I, the output of OS M 3 + Q and output ports are each second
As shown in FIGS. (C) and (d), it is always at H level and L level. Therefore, the output of the NAND circuit 33 has the same waveform as the pulse train signal as shown in FIG.
FF3. ．． It is input to the 3% clock input CP. On the other hand, since the L level is manually applied to the clear manual input CL as shown in Figure 2 (di), after the output Q of 03M3 becomes H level, the output Q of the DFF34 becomes the As shown in Figure 2 (), it becomes H level, and then at the rising edge of the next pulse signal train, the output of DFF3s ζ
is inverted to the level shown in FIG. 2(h). When the L level of this output port is inverted, capacitor C3
A negative differential pulse is generated, and the set signal S of R3FF4+ becomes L level and is triggered, and its output becomes the second
The signal is inverted to H level as shown in the figure (N).

Therefore, the running signal A becomes H level, the transistor Q is turned on, the electromagnetic coil 7 is driven, and the running record is drawn on the chart paper.

From the above operation, when the vehicle travels in a direction in which the speed increases from a stopped state, the speed increases during the second reference pulse period T.
When the speed corresponds to 2, the running signal A is output and the running state is recorded, for example, on the chart paper shown in FIG.

Next, when the pulse period of the pulse signal train from the waveform shaping circuit 12 corresponding to the vehicle speed is less than or equal to the second reference Hals period T2, the reset signal R is at H level as described above, After the negative pulse, the front and back signals become at level ■, so the output of R3FF4 is as shown in Figure 2.
i) < 1 (level is maintained, and the drive circuit 6 and electromagnetic coil 7 maintain the driving state. When the speed is reduced in this state, the pulse signal train becomes C4 and the pulse period becomes C4. When it comes to the reference pulse period T2 of 2, o
The outputs Q and ζ of terminals P, , P, of sM3t are shown in Fig. 2 (el
, (It becomes a rectangular wave signal of period T2 like dl. Therefore, the output Q of the DFF34 is inverted to L level at the falling and rising of the output Q and Q (Fig. 2(f)), DFF3S
is reset, the output d becomes H level as shown in FIG. 2 (th), and the output of the capacitor C1 is a positive differential pulse as shown in FIG. 2 (1).

On the other hand, since the output Q of osM2+ maintains the H level (FIG. 2(b)), the reset signal R also maintains the H level (FIG. 2(k)). Therefore, RS F F 4 +
The state of is not changed and the output is maintained at H level.

When the speed further decreases and the pulse period on the pulse signal side becomes the first reference pulse period T, such as t, OS M 2
The output Q of I becomes a rectangular wave signal with a period T as shown in FIG. (Kl < The same waveform as the rectangular wave signal of the output Q of OS M 2 r is output.

Therefore, the output of the NAND circuit 24 is input to the terminal P2 of R3FF4+, and at the time of falling, the reset signal R becomes L level, and the output of the terminal P3 is inverted to L level (FIG. 2 (1)). As a result, the transistor Q3 is turned off, the electromagnetic coil 7 is no longer driven, and recording on the chart paper is stopped.

From the above, when the vehicle speed decelerates from the speed corresponding to the second reference pulse period T2 or higher, the output of the running signal A stops when the speed reaches the speed corresponding to the first reference pulse period T1. Then, the driving recording operation stops. That is, in the direction in which the vehicle speed increases, the running signal A (discrimination signal) is output at a speed corresponding to the second reference pulse period T2, and in the direction in which the vehicle speed decreases, the vehicle runs at a speed corresponding to the first reference pulse period T. The output of the signal A is stopped, and the running signal A has hysteresis.

Resistors RI, R1, capacitors C'l * that determine the first and second reference pulse periods T + , T z
of C2.

For example, if the constants are set as R+: 15 Ω, CI: 6.8 μF, Rz: 12 Ω, and Ct: 6.8 μF, TI and T2 are each T, = 0.102 seconds (12, 25 H2) T, = 0.08
16 seconds (9.8 Hz), and the vehicle speeds corresponding to each T + -T t are, for example, 2.3 kffl/hour and 2.8 kffi/hour, respectively.

In the above embodiment, a case where the present invention is applied to speed recording has been described, but it can also be applied to, for example, control of a vehicle air conditioner when the vehicle speed is low, or an alarm circuit when the vehicle speed is high.

〔effect〕

As described above, according to the present invention, the hysteresis level of the discrimination signal output can be set independently by the first and second pulse period detection means, so that speed detection accuracy is improved. Furthermore, the responsiveness of the hysteresis level to the pulse signal train generated from the rotation speed detection means is also faster.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the speed detection circuit according to the present invention, FIGS. 2(a) to (N) are timing charts showing waveforms of each part in the circuit in FIG. 1, and FIGS. 3(a) to (C1 is a timing chart showing the operation of the monostable multi-by-break in Fig. 1, Fig. 4 is a diagram showing the truth value of the output logic value for human power of the D type flip-flop in Fig. 1, and Fig. 5 is a timing chart showing the operation of the monostable multi-by-break in Fig. 1. A circuit diagram showing the detection circuit, Fig. 6 is a diagram showing chart paper used in Figs. 1 and 5. l... Rotation speed detection means, ■,... Rotation sensor, 1□
. . . Waveform shaping circuit, 2 . . . First pulse period detection means, 2, . . . Main stable multi-high break, 23-24
... NAND circuit, 3... Second pulse period detection means, 3, ... Monostable multivibrator, 3□, 3
3...NAND circuit, 3. ．． 3. . . . D type flip-flop, 4 . . . Discrimination signal output means, 41 . . .
RS flip-flop, 5... power-on reset circuit, 6... drive circuit, 7... electromagnetic coil. Figure 2 Procedural amendment (□) September 3, 1988 Commissioner of the Japan Patent Office / JX Month ■ Ta 5 husband 1, No. 1 cow 2jiga 1988 patent application No. 154527 2, name of the invention speed Detection circuit 3, person who makes the correction A system with Meigyu Patent applicant address 1-4-28 Mita, Minato-ku, Tokyo Name (689) Yazaki Sogyo Co., Ltd. 4, Agent ＼----' 8, Amendment Content

Claims (1)

[Scope of Claims] Rotation speed detection means for obtaining a pulse signal train with a frequency corresponding to the rotation speed of a rotating body; and inputting the pulse signal train from the rotation speed detection means and determining the pulse period of the pulse signal train and the first pulse signal train. the reference pulse period and the first
first and second pulse period detection means each outputting a detection signal by comparing a second reference pulse period shorter than the reference pulse period; and each of the first and second pulse period detection means. discrimination signal output means for inputting a detection signal and outputting a discrimination signal at a frequency corresponding to the first and second reference pulse periods of the pulse signal train based on the detection signal; and a speed detection circuit characterized in that the discrimination signal is provided with hysteresis by each detection signal from the second pulse period detection means.