JPH0147751B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring the latch-up resistance of a semiconductor integrated circuit device, and more particularly to an improvement in the measurement of the latch-up resistance of a complementary integrated circuit device (hereinafter referred to as C-MOSIC).

Conventionally, to select and judge the quality of C-MOSIC,
An observer uses an oscilloscope etc. to measure the standard C-
This was done by comparing the voltage-current characteristics of the MOSIC with those of the individual C-MOSICs to be compared, or by conducting actual functional tests. However, it is clear that this sorting judgment is only a rough judgment of the quality of the product, and is not intended to predict the ease with which it will deteriorate or the lifespan of products that are judged to be good. In addition, the quality determination of C-MOSICs that has been carried out in the past is what is normally done, but it goes one step further and selects those that are easy to deteriorate or those that have a short lifespan from among those that are judged to be better. The reality is that there is no selective judgment.

In addition, due to the circuit configuration of C-MOSIC, a parasitic transistor is created at the input/output circuit end of the C-MOSIC, and the combination creates a state as if a thyristor circuit is configured. When a voltage higher than the voltage or external noise is applied, the thyristor circuit turns on and an abnormal current continues to flow from the power supply to the ground terminal until the power is turned off. This deteriorates the latch-up resistance and destroys or deteriorates the C-MOSIC. Regarding this latch up tolerance, C-
It has become clear that it depends on the withstand voltage of MOSIC input/output protection diodes, the withstand voltage of parasitic transistors, and the DC amplification factor.

Although this type of latch-up is a phenomenon unique to C-MOSICs, the latch-up resistance has not been measured in the past, and from this point of view, conventional pass/fail screening is insufficient. It cannot be said that it is an essential technical issue, nor can it be said that it truly meets social needs. This is C-
In order to improve the reliability of MOSICs, the requirements can only be met by removing in advance those that are likely to cause characteristic deterioration later, even if they are judged to be good through normal screening. It is.

Therefore, as shown in Japanese Unexamined Patent Publication No. 56-44866, a C-MOSC technology has been proposed that allows the latch-up resistance, which is a measure of the reliability of C-MOSIC, to be determined quickly, easily, and non-destructively.
An automatic latch-up resistance measurement device for MOSIC was introduced.

FIG. 1 shows the block configuration of this device. In the figure, 21 is a pulse generator, 22 is a pulse counter that counts the output pulses, 23 is a capacitor, and 24 and 25 are diodes. The output pulses are input as positive pulses to a stepped pulse generator 29, which is a pulse changing means, through these circuit devices. This step pulse generating section 29 consists of capacitors 26, 27, transistors 28, 30, and resistors 20, 41, 42, and the collector and emitter of the transistor 28 are connected to power supplies +V and -V. Capacitor ₂₆ with capacitance C 26 and capacitor ₂₇ with capacitance C 27
The relationship with is C ₂₆ ≪ C ₂₇ .

In addition, 31 is a stepwise pulse that is measured by C-
A switching selection section for sequentially switching input to MOSIC 32, 33 is a resistor connected between the output terminal of C-MOSIC 32 and ground, and 35 is a comparator.
The output voltage of the MOSIC 32 and the reference power source of the reference power source 34 are compared, and when the output voltage of the C-MOSIC 32 is high, the output voltage is obtained. Reference numeral 36 is a voltage holding section having a flip-flop configuration, 37 is a power supply voltage switching section, and 38 and 39 are switches for resetting this circuit.

Next, the operation will be explained.

In a circuit with such a configuration, first, the pulse output from the pulse generator 21 is passed through the capacitor 23,
It enters the stepped pulse generator 29 via the diodes 24 and 25, where it is converted into a stepped pulse and applied to the switching selection section 31 as a positive stepped pulse. The generated voltage _at this time is a voltage V ₀ (V ₀ = 1p・tw/
_C2 ). This voltage is connected to capacitors 26 and 2
Since the capacitance of V 7 is given as C ₂₆ ≪ C ₂₇ , it remains almost constant until the next pulse is applied, and when the next pulse is applied, it increases by V ₀ , which is added to the input impedance of the emitter follower (transistor 2
8), a stepped voltage is obtained.

When a stepped pulse voltage exceeding a certain level is applied to the input terminal of the C-MOSIC 32 of the object to be measured, an abnormal current flows between the power supply V _DD of the C-MOSIC 32 and the ground. This abnormal current is converted into a voltage by a resistor 33, and compared by a comparator 35 with the voltage of a reference power supply 34 indicating a predetermined latch-up tolerance and latch-up range. If the abnormal voltage is higher than the reference power supply, the comparator 35 outputs a voltage, which is applied to a voltage holding section 36 having a flip-flop configuration and held at a constant state. The output of the voltage holding section 36 is applied to the power supply voltage switching section 37, the discharging transistor 30, and the pulse generation section 21, and the power supply voltage of the C-MOSIC 32 and the voltage across the capacitor 27 are made zero, and at the same time, the pulse generation section 21 is make it stop.

In this way, the counting unit 22 calculates the number of pulse applications (n) until the output voltage is output to the comparator 35.
If you count it, the latch-up resistance at that time is n×
It is determined as v ₀ . The next measurement of the C-MOSIC is started by resetting the voltage holding section 36 using the reset switches 38 and 39.

If the latch-up read by the counting unit 22 as described above is associated with the known relationship between the latch-up tolerance, the noise tolerance, the latch-up tolerance, and the reliability, it can be immediately determined that the latch-up is easily degraded from a plurality of C-MOSICs. It is possible to distinguish between those that are less likely to deteriorate, and it becomes possible to make a more advanced selection of pass/fail.

However, in the conventional measuring device described above, the circuit that generates the electrical energy that triggers the latch-up is composed of an emitter follower, a switching conversion circuit, etc., and has internal resistance. For example, due to differences in impedance of the device under test, the amount of electrical energy received by the device under test differs, and there has been a problem in that it is not possible to compare the measurement withstand capacities of different types of devices.

Additionally, when this device detects an abnormal current in the device under test, it turns off the drive power for the device under test, making it impossible to measure the original latch-up resistance. There was a problem in that the surge voltage when current continued to flow could not be measured as latch-up resistance.

The present invention has been made in view of the above-mentioned problems, and includes charging a capacitor with electrical energy that triggers a latch-up in advance, applying this charged energy to a device under test, and also distributing the electrical energy. By measuring the charging energy as the latch-up resistance when the operating current remains unchanged even when the application is stopped, the device under test has a constant level that is not affected by its characteristics. energy (corresponding to Q = CV) is applied to the latch-up of a semiconductor integrated circuit device, and the measurement withstand capability can be compared for different types of elements, and the original latch-up capability can be measured. The purpose is to obtain a method for measuring tolerance.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a C-MOSIC according to an embodiment of the present invention.
1 is a circuit configuration diagram for explaining a method for measuring the latch-up resistance of a device.
and a ground terminal, 4 is an input or output terminal of the device under test 1, 5 is an operating power source for the device under test 1, 7 is an ammeter that measures the current from the operating power source 5, and 9 is an electricity that triggers the latch-up. A capacitor for storing energy, 10 is the capacitor 9
11 is a positive charging power source, 12 is a negative charging power source, and 13 is a polarity switching switch for changing the charging polarity of the capacitor 9.

Next, the operation will be explained.

When the switches 10 and 13 are held in the illustrated state, the capacitor 9 is charged to a positive polarity by the positive charging power source 11. The device under test 1 has an operating power supply 5.
By supplying the operating voltage from the
The device under test 1 is maintained in an operating state. In this state, the switch 10 is turned to transfer the positive charge of the capacitor 9 to the input or output terminal 4 of the device under test 1.
to be applied. Thereafter, the power supply ammeter 7 is used to check whether the power supply current has increased. If there is no increase in the power supply current, the charging voltage of the capacitor 9 is increased and the above operation is repeated. Then, the capacitor charging voltage when an increase in the power supply current is recognized and the power supply current continues to increase even after the voltage application by the capacitor is stopped is set as the latch-up start voltage.

The case where the capacitor 9 is charged with a positive charge, that is, the current flows into the input or output terminal of the device to be measured, has been described above. However, when measuring with the current flowing out from the input or output terminal, the switch 13 must be turned on. Switch capacitor 9
All you have to do is charge it to negative polarity.

In this way, in this embodiment, C-
The charging voltage of capacitor 9 increases and C-MOSIC1 changes until the operating current value of MOSIC1 changes.
The charging voltage of the capacitor 9 is measured as the latch-up resistance when the operating current remains unchanged even after the application of the charging voltage is repeated and the application of the voltage for measurement is stopped. Therefore, it is not only possible to measure the original latch-up resistance, but also to measure the latch-up resistance without being influenced by the characteristics of the device under test, and it is possible to compare the measured resistance of different types of elements.

In the above embodiment, a case has been described in which the latch-up trigger is applied to the input or output terminal 4 of the device under test 1, but the trigger application terminal may be a power supply terminal.

Figure 3 shows the configuration of a latch-up measurement circuit in such a case, which is the same as shown in Figure 2 above, except that the charging voltage of the capacitor 9 is applied to the power supply terminal 2 of the device under test. It is similar,
The measurement operation is also exactly the same.

As described above, according to the method for measuring a semiconductor integrated circuit device according to the present invention, a capacitor is charged in advance with electrical energy that triggers a latch-up, and this charged energy is applied to a device under test. Since the charging energy when the above-mentioned operating current remains unchanged even when the application of energy is stopped is measured as the latch-up tolerance, the device under test is not affected by its characteristics. Since a constant energy (corresponding to Q=CV) is applied, it is possible to compare the measurement withstand capacity of different types of elements, and also has the effect of being able to measure the original latch-up withstand capacity.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram illustrating a method for measuring the latch-up tolerance of a conventional C-MOSIC, and FIG. 2 is a circuit diagram illustrating a method for measuring the latch-up tolerance of a C-MOSIC according to an embodiment of the present invention. Third
The figure is a circuit configuration diagram for explaining a method for measuring latch-up resistance of a C-MOSIC according to another embodiment of the present invention. 1... Element to be measured, 2... Power supply terminal, 3... Ground terminal, 4... Input or output terminal, 5... Operating power supply, 7... Power supply ammeter, 9... Capacitor, 1
0...Switch for charging/discharging, 11, 12...Positive and negative power supplies for charging. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A method for measuring latch-up tolerance by maintaining a semiconductor integrated circuit device in an operating state and applying a measurement power source that triggers latch-up to the power source, input, or output terminal of the device, comprising: The power source for measurement is a pre-charged capacitor, and the measurement of the latch-up resistance is performed by increasing the charging voltage of the capacitor and applying the charging voltage to the terminal until a change occurs in the operating current value of the device under test. When the operating current value remains unchanged even after the voltage application for measurement is stopped, the charging voltage of the capacitor at the time of the above change in the operating current value is taken as the measured value of the latch-up resistance. 1. A method for measuring latch-up resistance of a semiconductor integrated circuit device, characterized in that: