JPH0147896B2 - - Google Patents
Info
- Publication number
- JPH0147896B2 JPH0147896B2 JP56063746A JP6374681A JPH0147896B2 JP H0147896 B2 JPH0147896 B2 JP H0147896B2 JP 56063746 A JP56063746 A JP 56063746A JP 6374681 A JP6374681 A JP 6374681A JP H0147896 B2 JPH0147896 B2 JP H0147896B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- adhesive
- resin
- semiconductor device
- mold structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、ICチツプの表裏を別々の種類の異
なる材料で覆われた半導体装置のモールド構造に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mold structure for a semiconductor device in which the front and back sides of an IC chip are covered with different types of materials.
従来技術のGB(ギヤングボンデイング)後に
おける半導体装置のモールド構造は第1図に示す
如く、ICチツプ1の能動面1aと裏面1bとを
同じ樹脂5で覆つている。この製造方法は、まず
GBされたICチツプ1の能動面1a側に、モール
ド剤として、粉体のBステージ状又は液状のエポ
キシ樹脂5又はシリコン樹脂5を供給して、ベル
ト炉又はホツトプレート又は恒温槽等で加熱して
ゲル化させ、ついで、ICチツプ1の裏面1bを、
裏返して同様の樹脂5又は同様の樹脂5を含む繊
維層で覆い、ゲル化後、完全硬化させるものであ
る。しかし、このようなモールド構造はモールド
時において、樹脂5の表面張力による影響を受け
てその流れ性が不均一となるので、平面方向に樹
脂5が流れてしまう範囲のバラツキや断面方向の
樹脂5の厚みのバラツキをおさえるための管理が
非常に難しいものである。また、ICチツプ1の
両面を同様の工程で2度行なわなければならない
ため、コストアツプにもつながる。そこで前述の
従来技術のモール構造を改善するために考えられ
たのが第2図に示す如く、能動面1aのみモール
ドする半導体装置のモールド構造である。これ
は、特に、腕時計やカメラ等の高密度実装が要求
され、また厚みに関しても非常に薄いものをつく
る場合に多く用いられる。この製造方法は、前記
従来例の場合と同様で、能動面1a側だけの工程
で済むことから、コストも材料費も1/2になる。
ここで、このモールド剤5の能動面1a側だけの
コントロールはその表面張力によるもので、IC
チツプ1の裏面1bと側面の境界で止まるもので
ある。ところがこの方法はその流れ出しのコント
ロールが、そのモールド剤5の粘度やチキソ性、
温度等に左右されて、その管理が非常に難しく、
裏面1bにそのモールド剤5が流れ出してしまう
ことがしばしば発生する。さらに、能動面1aを
覆つたモールド剤5のの硬化収縮や、ICチツプ
5との線膨張係数の違いにより発生する応力分布
の差によつて、ICチツプ5を破損することがあ
る。 As shown in FIG. 1, the mold structure of a semiconductor device after conventional GB (guyang bonding) is such that the active surface 1a and back surface 1b of an IC chip 1 are covered with the same resin 5. This manufacturing method first
B-stage powder or liquid epoxy resin 5 or silicone resin 5 is supplied as a molding agent to the active surface 1a side of the GB-treated IC chip 1, and heated in a belt furnace, hot plate, thermostatic oven, etc. Then, the back side 1b of the IC chip 1 is
It is turned over and covered with the same resin 5 or a fiber layer containing the same resin 5, and after gelling, it is completely cured. However, during molding, such a mold structure is affected by the surface tension of the resin 5 and its flowability becomes non-uniform, so there may be variations in the range in which the resin 5 flows in the planar direction, or variations in the flowability of the resin 5 in the cross-sectional direction. It is extremely difficult to control the variation in thickness. Furthermore, since both sides of the IC chip 1 must be processed twice in the same process, this also leads to an increase in costs. Therefore, in order to improve the molding structure of the prior art described above, a semiconductor device molding structure in which only the active surface 1a is molded, as shown in FIG. 2, was devised. This is especially used when manufacturing watches, cameras, etc. that require high-density packaging and are also extremely thin. This manufacturing method is similar to that of the conventional example, and since only the steps on the active surface 1a side are required, the cost and material cost are halved.
Here, the control of only the active surface 1a side of the molding agent 5 is due to its surface tension, and the IC
It stops at the boundary between the back surface 1b and the side surface of the chip 1. However, in this method, the flow control is dependent on the viscosity and thixotropy of the molding agent 5.
It is very difficult to manage as it depends on temperature etc.
It often happens that the molding agent 5 flows out onto the back surface 1b. Further, the IC chip 5 may be damaged due to curing shrinkage of the molding agent 5 covering the active surface 1a or a difference in stress distribution caused by a difference in coefficient of linear expansion with the IC chip 5.
本発明は斯かる欠点を除去したもので、その目
的とするところは、ICチツプを薄くかつ高品質
にモールドするところにある。 The present invention eliminates these drawbacks, and its purpose is to mold an IC chip thinly and with high quality.
本発明の要旨は、ICチツプの電極とフレキシ
ブル基板に形成される複数のインナーリードとを
同時にボンデイングした後モールドされる半導体
装置のモールド構造において、前記ICチツプの
製造途中工程でウエハーを接着する際に使用され
接着された状態で前記ICチツプの裏面に残存す
ると共に前記ICチツプの側面方向にも突出する
ように残存する接着剤又は粘着剤と、前記ICチ
ツプの能動面をモールドするエポキシ樹脂又はシ
リコン樹脂とを有し、前記ICチツプが2種類以
上の材料で覆われることを特徴とする。 The gist of the present invention is to provide a mold structure for a semiconductor device that is molded after simultaneously bonding the electrodes of an IC chip and a plurality of inner leads formed on a flexible substrate. an adhesive or a pressure-sensitive adhesive that is used to remain on the back surface of the IC chip in a bonded state and also protrudes from the sides of the IC chip; and an epoxy resin or adhesive that molds the active surface of the IC chip. silicone resin, and the IC chip is covered with two or more kinds of materials.
以下、本発明を実施例に基づいて詳細に説明す
る。第3図は本発明の実施例を示すものであり、
GB後にICチツプの能動面側からのみモールドし
た半導体装置のモールド構造の断面図である。 Hereinafter, the present invention will be explained in detail based on examples. FIG. 3 shows an embodiment of the present invention,
FIG. 2 is a cross-sectional view of a mold structure of a semiconductor device that is molded only from the active side of an IC chip after GB.
第3図に示す本発明の半導体装置のモールド構
造は、第2図に示した従来技術の片側(能動面)
のみモールドする半導体装置のモールド構造に加
えて、ICチツプの裏面にも別の樹脂でモールド
したもである。これは特に、その材料を別途供給
するものではない。すなわち、ICチツプ1とフ
レキシブル基板3に形成される複数のインナーリ
ード2とをボンデイングするGBにおいて、ICチ
ツプ1の供給方法としてはウエハーからダイシン
グしたものを1個1個単体で供給する方法で、も
う1つはウエハーをガラス又は樹脂性の平滑板
に、高温でその効果を失う接着剤6又は粘着剤6
で粘りつけ、そのウエハーを粘着剤6と平滑板を
一緒にダイシングし、ウエハーのままGBする方
法があるが、特に後者におけるその接着剤6(従
来技術においては通常接着剤又は粘着剤の厚さは
10〜20μmである)をそのまま使用するものであ
る。通常、これはGB後に洗浄されるものである
が、特に耐湿性及び純度にすぐれたワツクス又は
接着剤を選んで行なえば、その洗浄工程も不必要
となる。接着剤6はICチツプの裏面1bに残存
すると共にICチツプ側面方向にも突出して残存
しているでモールド樹脂5の裏面1bへの流れ防
止にも役立つ。さらに、モールド樹脂の厚さは
ICチツプの全体を覆うような従来技術とすれば、
著しく薄くできるので、モールド樹脂5の硬化収
縮時にICチツプ1との線膨張係数の違いにより
発生する応力も小さくなることから、例えば発生
する内部応力の差が大きいことによつて、ICチ
ツプ1が破損してしまうような品質不良特性を減
少させることができる。また、裏面1bを接着剤
6で薄く覆う事から、例えば、裏面1bに外力が
作用する場合でもICチツプ1はこの接着剤1b
により保護されているので、外力を緩和し直接的
に損傷することがない。 The mold structure of the semiconductor device of the present invention shown in FIG. 3 is different from that of the conventional technology shown in FIG.
In addition to the mold structure of a semiconductor device in which only the IC chip is molded, the back side of the IC chip is also molded with a different resin. In particular, this does not mean that the material is supplied separately. That is, in the GB in which an IC chip 1 and a plurality of inner leads 2 formed on a flexible substrate 3 are bonded, the IC chips 1 are supplied by dicing them from a wafer and supplying them one by one. The other method is to attach the wafer to a glass or resin smooth plate using an adhesive 6 or adhesive 6 that loses its effectiveness at high temperatures.
There is a method of gluing the wafer with the adhesive 6 and the smooth plate together and GBing the wafer as it is. teeth
(10 to 20 μm) is used as is. Normally, this is cleaned after GB, but if a wax or adhesive with particularly good moisture resistance and purity is selected, this cleaning step is also unnecessary. The adhesive 6 remains on the back surface 1b of the IC chip and also protrudes from the sides of the IC chip, so that it also serves to prevent the mold resin 5 from flowing toward the back surface 1b. Furthermore, the thickness of the mold resin is
If the conventional technology covers the entire IC chip,
Since it can be made extremely thin, the stress generated due to the difference in linear expansion coefficient from that of the IC chip 1 when the mold resin 5 cures and shrinks is also reduced. It is possible to reduce quality defects that may lead to breakage. In addition, since the back surface 1b is thinly covered with the adhesive 6, even if an external force is applied to the back surface 1b, the IC chip 1 will not be exposed to the adhesive 6.
Since it is protected by, external force is alleviated and there is no direct damage.
本発明は、腕時計、カメラ、マイクロカセツト
等の小さなメカトロニクスの製品に特に有効であ
り、デザイン、品質面ですぐれた効果を有するも
のである。 The present invention is particularly effective for small mechatronic products such as wristwatches, cameras, and microcassettes, and has excellent effects in terms of design and quality.
本発明の主旨を逸脱する事のない範囲でなされ
る構造の変更は、すべて本発明に含まれるものと
する。 All structural changes made without departing from the spirit of the present invention are included in the present invention.
以上述べたように本発明によれば、ICチツプ
の裏面にICチツプの製造途中工程でウエハーを
ボンデイングする際に使用された接着剤又は粘着
剤がそのまま残存する状態で使用されるので、従
来技術において実施されていた前記接着剤又は粘
着剤を除去していた洗浄工程が不必要となり、実
質工数が低減される効果を有すると共に、前述の
如き接着剤又は粘着剤がICチツプの裏面に残存
すると共にICチツプの側面方向にも突出して残
存しているので、この残存する接着剤又は粘着剤
によつて、ICチツプの能動面をモールドする際
のエポキシ樹脂又はシリコン樹脂の前記ICチツ
プ裏面への流出が防止されることから、例えば前
記エポキシ樹脂又はシリコン樹脂の注入量をIC
チツプの裏面を除く全体を覆うだけの適性量とす
れば、そのモールド厚さが不必要に厚くならない
という効果を有する。またエポキシ樹脂又はシリ
コン樹脂の両面からのモールドによつてICチツ
プの全体を覆うような従来技術と比較すれば著し
く薄くできるので、モールド樹脂の硬化収縮や、
ICチツプとの膨張係数の差に対する影響が軽減
され、例えば発生する内部応力の差が大きいこと
によつて、ICチツプが破損してしまうような品
質不良特性が減少するという効果も有する。 As described above, according to the present invention, the adhesive or adhesive used when bonding the wafer during the manufacturing process of the IC chip is used while remaining on the back surface of the IC chip. The cleaning process that was used to remove the adhesive or adhesive that was performed in At the same time, it also remains protruding in the side direction of the IC chip, so this remaining adhesive or adhesive prevents the epoxy resin or silicone resin from being applied to the back surface of the IC chip when molding the active surface of the IC chip. For example, the injection amount of the epoxy resin or silicone resin is
If the appropriate amount is used to cover the entire chip except the back surface, the mold thickness will not become unnecessarily thick. In addition, compared to conventional techniques in which the entire IC chip is covered by molding from both sides of epoxy resin or silicone resin, it can be made much thinner, so there is no curing shrinkage of the mold resin.
It also has the effect of reducing the influence of the difference in expansion coefficient with the IC chip, and reducing quality defects such as damage to the IC chip due to a large difference in internal stress, for example.
さらに、例えば前述のICチツプの能動面のみ
を覆う片側モールド構造の従来技術と比較すれ
ば、従来技術の片側モールド構造では、ICチツ
プの裏面は裸であつてICチツプ全体がモールド
されていないので、ICチツプと樹脂との境界よ
り入水しやすいことから著しく耐水性に劣りIC
チツプの能動面を腐食させてしまうというな品質
不良を発生させること、またICチツプ裏面に外
力が作用した場合には、その外力がICチツプに
直接的に作用することとなるので、ICチツプが
損傷しやすいという問題点を有するものである
が、本発明の半導体装置のモールド構造は、IC
チツプ全体が樹脂と接着剤とにより覆われている
ので、前述の如き従来技術の問題点を回避できる
という効果を有する。 Furthermore, compared to the conventional technology with a one-sided mold structure that covers only the active surface of the IC chip, for example, in the conventional technology with one-sided mold structure, the back side of the IC chip is bare and the entire IC chip is not molded. , since it is easy for water to enter the boundary between the IC chip and the resin, the water resistance is significantly inferior and the IC
This may cause quality defects such as corrosion of the active surface of the chip, and if an external force acts on the back side of the IC chip, that external force will act directly on the IC chip. Although it has the problem of being easily damaged, the mold structure of the semiconductor device of the present invention is suitable for ICs.
Since the entire chip is covered with resin and adhesive, the above-mentioned problems of the prior art can be avoided.
第1図は、従来技術の実施例を示す半導体装置
のモールド構造の断面図。第2図は、従来技術の
他の実施例を示す半導体装置のモールド構造の断
面図。第3図は、本発明の実施例を示す半導体装
置のモールド構造の断面図。
1……ICチツプ、1a……能動面、1b……
裏面、2……インナーリード、3……フレキシブ
ル基板、4……電極、5……モールド樹脂、6…
…ウエハーの接着剤。
FIG. 1 is a sectional view of a mold structure of a semiconductor device showing an example of the prior art. FIG. 2 is a sectional view of a mold structure of a semiconductor device showing another example of the prior art. FIG. 3 is a sectional view of a mold structure of a semiconductor device showing an embodiment of the present invention. 1...IC chip, 1a...active surface, 1b...
Back surface, 2...Inner lead, 3...Flexible substrate, 4...Electrode, 5...Mold resin, 6...
...wafer adhesive.
Claims (1)
される複数のインナーリードとを同時にボンデイ
ングした後モールドされる半導体装置のモールド
構造において、前記ICチツプの製造途中工程で
ウエハーを接着する際に使用され接着された状態
で前記ICチツプの裏面に残存すると共に前記IC
チツプの側面方向にも突出するように残存する接
着剤又は粘着剤と、前記ICチツプの能動面をモ
ールドするエポキシ樹脂又はシリコン樹脂とを有
し、前記ICチツプが2種類以上の材料で覆われ
ることを特徴とする半導体装置のモールド構造。1. In the mold structure of a semiconductor device in which the electrodes of an IC chip and a plurality of inner leads formed on a flexible substrate are simultaneously bonded and then molded, it is used when bonding a wafer during the manufacturing process of the IC chip. The IC chip remains on the back surface of the IC chip in a state of
The IC chip is covered with two or more types of materials, including an adhesive or adhesive that remains so as to protrude in the side direction of the chip, and an epoxy resin or silicone resin that molds the active surface of the IC chip. A mold structure for a semiconductor device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56063746A JPS57178346A (en) | 1981-04-27 | 1981-04-27 | Molded structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56063746A JPS57178346A (en) | 1981-04-27 | 1981-04-27 | Molded structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57178346A JPS57178346A (en) | 1982-11-02 |
| JPH0147896B2 true JPH0147896B2 (en) | 1989-10-17 |
Family
ID=13238268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56063746A Granted JPS57178346A (en) | 1981-04-27 | 1981-04-27 | Molded structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57178346A (en) |
-
1981
- 1981-04-27 JP JP56063746A patent/JPS57178346A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57178346A (en) | 1982-11-02 |
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