JPH0147904B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention is a novel field effect transistor (hereinafter referred to as FET) that has both positive resistance characteristics and negative resistance characteristics.
It is related to.

Figure 1 shows the conventional SOS (Silicon On
This is a cross-sectional view showing a FET with a Sapphire structure, in which an N-type semiconductor layer 2 with a low impurity concentration is formed on an insulating substrate 1 using sapphire, and high impurity N ⁺ type semiconductor regions with a high concentration are provided as a source region 3 and a drain region 4, and an insulating film 5 is formed on these surfaces,
A conductive gate electrode 6 is formed directly above the insulating film 5 facing the channel layer 2a between the source region 3 and the drain region 5 in the semiconductor layer 2, and a conductive gate electrode 6 is formed in contact with the source and drain regions 3 and 4. A source electrode 7 and a drain electrode 8 are formed.

However, when forming the semiconductor layer 2 of Si material on the sapphire substrate 1, the lattice constants of the sapphire Si and the sapphire Si do not completely match, so a high density of crystal defects is generated at the interface between the two, which causes the interface to deteriorate. The carrier mobility in the vicinity decreases, and when a Si crystal is grown on sapphire, a large amount of Al diffuses from sapphire to the Si side.

Therefore, in the SOS structure, the thickness t _c of the semiconductor layer 2
is usually 0.4 μm or more, and the thickness t _c is more than three times the Debye length specific to the semiconductor layer 2, resulting in the distribution of carriers as shown in FIG.

Note that the extrinsic Debye length L _DE is generally expressed by the following equation.

However, ε _s : Dielectric constant k of semiconductor layer 2 : Boltzmann's constant T : Absolute temperature q : Charge unit N _D : Carrier concentration of semiconductor layer 2 Figure 2 a is a model of each main part of Figure 1. Figure b is a distribution diagram showing the carrier distribution between each point at point a, and when the drain voltage V _DS is made higher than the gate voltage V _GS , the flow of carriers is mainly composed of electrons. is as shown in a, and its distribution is as shown in b, where the distribution concentration n is maximum at _one point A, and A ₂ , B ₁ , B ₂
Between the pinch-off point P between the two points B ₁ and _B and the point D ₁ and D ₂ , the distribution concentration n is almost uniform.
becomes.

Therefore, in the first region E ₁ between the source region 3 and the pinch-off point P, the gate voltage V _GS is within the range of approximately the extrinsic Debye length L _DE from the interface between the channel layer 2 a and the insulating film 5 . While carriers thus induced exist in a high concentration, in the second region _E2 between the pinch-off point P and the drain region 4, the potential of the semiconductor layer 2 in this part is higher than the gate voltage _VGS , and , t _c >>L _DE , carriers are diffused by a strong electric field from the channel layer 2a toward the drain region 4, and are distributed in a substantially uniform low concentration.

Furthermore, the carrier concentration decreases almost uniformly from the source region 3 to the drain region 4, except for the side edges of the source region 3 and the drain region 4, and under such distribution conditions, From the source region 3 toward the drain region 4, the electron flow due to drift and the electron flow due to diffusion flow in the same direction, and the first
Since the second region E ₂ exhibits a sufficiently higher resistance value than the region E ₁ , the drain current I _DS is saturated.

Therefore, the drain voltage V _DS and drain current I _DS characteristics using the gate voltage V _GS as a parameter are
As shown in the figure, the drain current I _DS increases as the drain voltage V _DS increases, as shown by the dotted line.
It becomes saturated with V _DS = V _GS as the boundary, but
The drain current I _DS never decreases, and the conductance g _D expressed by the following equation always takes only positive values.

g _D = dI _DS / dV _DS ...(2) Therefore, in conventional FETs, even if a positive drain-source resistance can be obtained, a negative resistance cannot be obtained; This results in a drawback that it cannot be applied to oscillation circuits, etc.

The present invention has the purpose of fundamentally solving such drawbacks of the conventional method, and it includes forming an insulating layer on a conductive substrate, forming a semiconductor layer on this insulating layer, and reducing the thickness of the semiconductor layer. By making the FET less than three times the extrinsic Debye length unique to the semiconductor layer, we provide an extremely effective and innovative FET that can also obtain negative resistance depending on the gate voltage. be.

The details of the present invention will be explained below with reference to FIG. 4 and subsequent figures showing embodiments.

FIG. 4 shows a cross-sectional view, in which an insulating layer 10 made of SiO ₂ or the like is formed on a conductive substrate 9 made of Si material, and N with a low impurity concentration based on Si is deposited on this insulating layer 10.
The semiconductor layer 2 is formed so that its thickness t _c is not more than three times the extrinsic Debye length L _{DE specific to the semiconductor layer 2 , and the semiconductor layer 2 is formed so that the semiconductor layer 2 has a thickness t c that is equal to or less than three times the extrinsic Debye length L DE} unique to the semiconductor layer 2 . A source region 3 and a drain region 4 made of N ⁺ type semiconductor regions with high impurity concentration are provided separately, and on the channel layer 2a made of the semiconductor layer 2 between the source region 3 and the drain region 4 and on the surface of each part, After forming an insulating film 5 such as SiO ₂ ,
A conductive gate electrode 6 made of Al or the like is formed directly above a portion of the insulating film 5 facing the channel layer 2a, and a conductive gate electrode 6 is formed in contact with the source and drain regions 3 and 4 through the hole in the insulating film 5. The electrode 7 and the drain electrode 8 are made of Al or the like.

FIG. 5a is a diagram schematically showing the main part of FIG. 4,
Figure b shows the carrier distribution in the channel layer 2a at point a, and shows the positive drain voltage.
When V _DS and a positive gate voltage V _GS higher than the flat band voltage are applied, and the voltage V _BS between the substrate 1 and the source region 3 is in the relationship V _DS > V _BS , the present invention is applied. In order to exhibit a unique effect, the two are short-circuited, and in this example, V _BS is set to 0V.

The carrier distribution situation in this case is t _c ≦3・L _DE
Therefore, not only the channel layer 2a in the first region _E1 is filled with high concentration of electrons, but also the second region _E2 is filled with high concentration of electrons _. As , approaches the side edge of the drain region 4, the potential of the channel layer 2a gradually becomes higher than the gate voltage _VGS , so that the electric field from the channel layer 2a toward the gate electrode 6 gradually increases, and accordingly, As shown in b.
Electrons are concentrated in the center of the channel layer 2a, and the degree of concentration becomes more significant as the concentration approaches the drain region 4 side, and the peak value of the carrier distribution concentration n differs from that in FIG. 2 and reaches the pinch-off point P. It increases rapidly from the point toward the drain region 4.

Therefore, in addition to the first electron flow due to drift from the source region 3 to the drain region 4 and the second electron flow due to diffusion from the source region 3 in the first region _E1 toward the pinch-off point P, the second electron flow is generated in the second region _F2. A third electron flow is generated by diffusion from the drain region 4 toward the pinch-off point P at , and the first and second electron flows become the main components of the drain current I _DS , and V _DS >
They are saturated under the conditions of V _GS , V _DS > V _BS , but the third electron flow is in the opposite direction and non-saturating,
This reduces the drain current _IDS .

Therefore, as in Figure 3, the drain voltage
As the V _DS and drain current I _DS characteristics are shown in Figure 6, the dotted line indicates V _DS = V _DS higher than V _{GS .}
> V _GS , the drain current I _DS tends to decrease as the gate voltage V _GS increases, the conductance g _D shown by equation (2) becomes negative, and the drain-source resistance increases. It exhibits negative resistance.

In other words, as the gate voltage V _GS becomes higher, the electron density in the first region E ₁ increases, so the electron density in the second region E ₂ also increases, and the conductance g _D increases in the negative direction. When the voltage V _GS decreases, the drain current generated due to the pinch-off point P moving toward the source region 4 as the drain voltage V _DS increases is greater than the decrease in the drain current I _DS due to the third electron flow. The increase in I _DS becomes large,
By exhibiting positive conductance characteristics, a positive or negative conductance _gD can be freely obtained by setting the gate voltage _VGS .

The theoretical basis for obtaining the above-mentioned effects is as follows.

First, in order to obtain the characteristics shown in FIG. 6, it is necessary that electrons be accumulated in an excessive state in the channel layer 2a as an active region.

That is, when a gate voltage V _GS higher than the flat band voltage V _FB at the interface between the channel layer 2 a and the insulating film 5 is applied, the channel layer 2 a
The concentration n(Z) of electrons, which are the majority carriers, satisfies n(Z)> _ND ...(11) and must be 0Zt _c .

Furthermore, if the depth d of the carrier distribution in the channel layer 2a when V _GS >V _BF is approximately determined, the results shown in FIG. 7 can be obtained as a model.

Here, Z=0 is the interface between the channel layer 2a and the insulating film 5 in FIG. 5a, and n(Z) is
It can be approximately derived from the Poisson equation shown below.

d ² φ/dZ ² =qn(Z)/ε _s (12) where, φ: potential from the Fermi level in the semiconductor, and n(Z) is expressed by the following equation.

n(Z)N _D・exp{(qφ)/(kT)}...(13) If we combine equations (12) and (13) and set the following boundary conditions to find n(Z), we get However, φ _s :Z=0, that is, the surface potential n(Z) at the interface between the channel layer 2a and the insulating film 5 is expressed by the following equation.

n(Z)=N _D {t _ao ² (Z/L _DE −C)+1} ……(15) C=t _ao ⁻¹ √{( _s )()−1}……(1
6) Here, it is usually easy to set φ _s ≫ (kT)/q, (φ _s ≒0.026V), so C≒π/2, and n
Using the condition (d)=N _D , d is given by the following equation.

d=π/2L _DE ≒1.57L _DE ...(17) Therefore, if we also take into consideration the interface between the channel layer 2a and the insulating layer 10, when t _c <3L _DE , the carrier distribution of the channel layer 2a is n(Z)>N _D , and the predetermined condition is satisfied.

In addition, in order to manufacture the one shown in Fig. 4, the Si material substrate 9 is maintained at a predetermined temperature of 200°C or higher, and 0 ₂ is ion-implanted so that the atomic concentration is 6.75×10 ²² cm ^-3 or higher. The semiconductor layer 2 may be formed by implanting the SiO ₂ insulating layer 10 into the inner layer on the surface side of the substrate 1 by implanting the silicon material using the Si material on the surface as a core, and then performing heat treatment. The drain regions 3 and 4 are formed by ion implantation using P,
A _s or the like may be implanted to create a region with a high impurity concentration.

Note that the subsequent steps may be performed in the same manner as for the SOS structure FET, and the FET shown in FIG. 4 can be easily manufactured.

In addition, the above FET is N based on the following specifications.
As a result of trial production as a type channel, positive conductance characteristics were obtained when V _GS ≦6V, negative conductance characteristics were obtained when V _SG ≧q, and conductance g _D = -100 μs was obtained when V _SG = 16V.

t _c =0.1μm N _D =1×10 ^-15 cm ^-3 L _DE =0.188μm Channel length = 5μm Channel width = 35μm Therefore, the negative resistance amplifier, negative resistance oscillator, memory circuit, etc. of the present invention The FET of the present invention can be easily configured using a FET, and can also be used as a normal FET depending on the setting of the gate voltage V _GS . Can be applied.

Note that since the substrate 9 faces the channel layer 2a via the insulating layer 10 and has essentially the same function as the gate electrode 6, the substrate voltage _VBS as well as the gate voltage _VGS cannot be changed separately. For example, double control electrode
It becomes a FET and can also be used as a modulator, mixer, etc.

However, it is preferable to set the extrinsic Debye length _LDE of the thickness _tc of the channel layer 2a to be less than or equal to the extrinsic Debye length _LDE , since negative resistance characteristics can be obtained in a low range of the gate voltage VGS, and the cross-sectional area of the semiconductor layer 2 By gradually decreasing the amount from the source region 3 to the drain region 4, the effects specific to the present invention will be promoted due to the carrier distribution shown in FIG.

Further, as the substrate 9, in addition to the Si material, a single material such as a _Ge material, or a compound material such as a _{Ga As} may be used. After selecting the material of the semiconductor layer 2, the source and drain regions 3, 4 are formed according to the material of the semiconductor layer 2.
The present invention can be modified in various ways, such as by selecting the impurity concentration added therein from various substances such as B, P, _As , etc., and depending on the conditions, the semiconductor layer 2 may be of P type conductivity type. It is.

As is clear from the above description, according to the present invention, an FET having both positive and negative resistance characteristics can be obtained, and the desired resistance characteristics can be easily set depending on the voltage relationship of each part. This simplifies the process and also realizes multiple functions using the same circuit, resulting in remarkable effects in various electronic devices.

[Brief explanation of drawings]

Fig. 1 is a sectional view of the conventional example, Fig. 2 is a diagram showing the carrier distribution situation of Fig. 1, Fig. 3 is a characteristic diagram of Fig. 1, and Fig. 4 is a diagram of the embodiment of the present invention. 5 is a diagram showing the carrier distribution situation of Figure 4, Figure 6 is a characteristic diagram of Figure 4, and Figure 7 is a characteristic diagram showing a modeled carrier distribution concentration. . 2...Semiconductor layer, 2a...Channel layer, 3...
Source region, 4...Drain region, 5...Insulating film, 6...Gate electrode, 7...Source electrode, 8...
...Drain electrode, 9...Substrate, 10...Insulating layer,
_tc ...Thickness.

Claims (1)

[Scope of Claims] 1. A conductive substrate, an insulating layer formed on the substrate, and an insulating layer formed on the insulating layer and having a conductivity type of P type or N type and having a specific thickness. a semiconductor layer having a length not more than three times the extrinsic Debye length; a source and drain region with a high impurity concentration provided spaced apart from each other in the extending direction in the semiconductor layer; and at least a portion of the source region and the drain region. an insulating film formed on the semiconductor layer between them, a conductive gate electrode formed on the insulating film, and a conductive source and drain electrode formed in contact with the source and drain regions. A field effect transistor characterized by: 2 In addition to using Si material as a conductive substrate,
The field effect transistor according to claim 1, characterized in that a semiconductor layer is used as a substrate. 3 Embedded in the Si material substrate as an insulating layer
The field effect transistor according to claim 1, characterized in that a SiO ₂ layer is used. 4. The field effect transistor according to claim 1, characterized in that a semiconductor layer having a thickness equal to or less than a specific Debye length is used. 5. The field effect transistor according to claim 1, characterized in that a semiconductor layer is used whose cross-sectional area gradually decreases from the source region to the drain region.