JPH0147929B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that shifts an input voltage and outputs it, and the present invention relates to a circuit that shifts an input voltage and outputs the same, and relates to a circuit that shifts an input voltage and outputs the same. This is an improved version of

A conventional voltage shift circuit is shown in FIGS. 1 and 2, and its problems will be described. First, FIG. 1 shows a constant current source. The power supply voltage V _CC is divided by resistors R ₁₁ and R ₁₂
It is input to the base of pnp transistor _Q11 .
The collector of the pnp transistor _Q11 is grounded, and the emitter is connected to the power supply via a resistor _R13 and to the base of the npn transistor _Q12 .
The emitter of the npn transistor _Q12 is grounded via a resistor _R14 , and the collector serves as the output terminal of a constant current source. Determine the current value quantitatively. The base voltage V _BQ11 of the PNP transistor Q ₁₁ is V _BQ11 = R ₁₂ /R ₁₁ + R ₁₂ · V _CCThen the base voltage V _BQ12 of the NPN transistor Q ₁₂ is V _BQ12 = V _BQ11 + V _BEQ11 where V _BEQ11 is PNP Base of transistor _Q11
This is the voltage between the emitters. NPN transistor _Q12
The voltage at the emitter of V _EQ12 is V _EQ12 = V _BQ12 −V _BEQ12 where V _BEQ12 is the base voltage of NPN transistor Q ₁₂ .
This is the voltage between the emitters. Therefore, the emitter current I _EQ12 of the NPN transistor Q ₁₂ becomes I _EQ12 =V _EQ12 /R ₁₄ . The collector current I _CQ12 of the NPN transistor Q ₁₂ , which is the output of the constant current source, is I _CQ12 = h _FEQ12 /1 + h _FEQ12・I _EQ12 = I _EQ12 (∵h _FEQ12 ≫1) = 1/R ₁₄・[R ₁₂ /R ₁₁ + _R12・V _CC +(V _BEQ11 − V _BEQ12 )] ...(1) Here, h _FEQ12 is the current amplification factor of the NPN transistor _Q12 .

Here, we will consider the variation in collector current I _CQ12 during mass production. Integrated circuits are characterized by poor precision and temperature stability in the absolute value of resistance, but good relative precision, and transistors also have good relative precision, although the absolute values of various constants vary. Taking this into consideration, when considering the variation in the integrated circuit of the above equation (1), (a) the coefficient 1/R ₁₄ varies in inverse proportion to the value of the resistor R ₁₄ .

(b) The first term R ₁₂ /R ₁₁ +R ₁₂ ·V _CC does not vary because it depends on the relative accuracy of resistors R ₁₁ and R ₁₂ .

(c) The second term (V _BEQ11 −V _BEQ12 ) is the difference between the two base-emitter voltages V _BE , so it may seem to be a stable value at first glance, but as will be explained in detail later, it is approximately −100 mV. ~+100mV fluctuation.

The variation in collector current I _CQ12 due to item (a) during mass production is not a problem because it can be easily removed using resistors integrated on the same chip. Also, item (b) is stable. Therefore, only item (c) remains as a major problem regarding characteristic variations due to manufacturing variations during mass production of integrated circuits.

Regarding the mass production variation of collector current I _CQ12 due to item (c), in the past, there were many applications where the power supply voltage V _CC was high, around 10 to 20 V, so the influence was relatively small.
If a precise current value was required, the adjustment stage could be installed at a later stage without causing any problems. However, in recent years, the power supply voltage has been reduced to 3 to 6 V due to the demand for energy conservation and low power consumption, as well as the desire to reduce the number of batteries in portable devices to make them lighter.
Furthermore, in order to reduce manufacturing costs, there is a growing demand for no adjustment. As a result, the voltage variations during mass production of integrated circuits mentioned in item (c) above have become a problem that cannot be ignored.

Next, the cause of the above item (c) will be explained in detail below. First, the transistor in Figure 1
Q ₁₁ and Q ₁₂ have the structure shown in the cross-sectional view of FIG. 3. The left half of Figure 3 is an NPN transistor,
The right half is a PNP transistor. An N-type buried layer 2 and a P-type isolation diffusion layer 3 for separating transistors are formed on a P-type semiconductor substrate 1, and N-type semiconductor epitaxial layers 4, 8,
12 are separated from each other.

By the way, in the NPN transistor, the epitaxial layer 4 is used as a collector region, the P-type semiconductor diffusion layer 6 is used as a base region, and the highly concentrated N-type semiconductor diffusion layer 7 diffused in the diffusion layer 6 is used as an emitter region. It is configured as. The diffusion layer 5, which is formed at the same time as the emitter, is provided to ensure the contact between the epitaxial layer 4, which is the collector, and the aluminum for wiring. Therefore, the saturation current I _{S (NPN)} of the NPN transistor is mainly caused by the diffusion layer 7
It is determined by the impurity concentration and thickness of the diffusion layer 6 that exists directly below.

On the other hand, the NPN transistor uses the P-type diffusion layer 9 formed at the same time as the isolation diffusion layer 3 as a collector region, the epitaxial layer 12 as a base region, and
It is constructed using a type semiconductor diffusion layer 11 as an emitter region. Note that the diffusion layer 10 is provided for the same reason as the diffusion layer 5. Therefore, the saturation current I _{S (PNP)} of the PNP transistor is mainly caused by the diffusion layer 11.
It is determined by the impurity concentration and thickness of the epitaxial layer 12 immediately below.

The saturation current _IS of NPN and PNP transistors is expressed as follows.

I _S(NPN) =q・S _o・D _o /W _o・ni ² /P _P …(2) I _S(PNP) =q・S _P・D _P /W _P・ni ² /N _o … ...(3) where q: Charge amount of electron, S _o : Area of diffusion layer 7 which becomes emitter, S _P : Area of diffusion layer 11 which becomes emitter, D _o : Diffusion constant of electron, D _P : Hole W _o is the traveling distance of electrons in the base region, which is the distance between the diffusion layer 7 and the epitaxial layer 4; W _P is the traveling distance of holes in the base region, which is the distance between the diffusion layer 11 and the P-type diffusion. distance from layer 9, n _i ² : carrier concentration in the intrinsic semiconductor, P _P : hole concentration in the diffusion layer 6, N _o : electron concentration in the epitaxial layer 12. In Figure 1, transistors Q ₁₁ and Q ₁₂
The base-to-emitter voltages V _BEQ11 and V _BEQ12 are respectively V _BEQ11 = KT/qlnI _EQ11 /I _S(PNP) and V _BEQ12 = KT/qlnI _EQ12 /I _S(NPN). (V _BEQ11 − V _BEQ12 ) is (V _BEQ11 − V _BEQ12 ) = KT/q(lnI _EQ11 /I _S(PNP) −lnI _E
Q12 /I _S(NPN) )=KT/q・lnI _EQ11 /I _EQ12・I _S(NPN) /I
_S(PNP) ……(4). Substituting equations (2) and (3) into equation (4), (V _BEQ11 − V _BEQ12 ) = KT/q [lnI _EQ11 /I _EQ12 +lnS _o /
It can be seen that S _P + ln (D _o / W _o P _P / D _P / W _P N _o )]...(5).

Since the first and second terms in equation (5) are the ratio of the emitter current and the ratio of the emitter area, respectively, they can be made extremely small by circuit design, IC mask design, etc. However, regarding the third term, if the conventional voltage shift circuit is integrated,
This requires extremely high absolute value control of the manufacturing process, which poses a rather difficult problem. This will be discussed in more detail below.

In the first term of equation (5), the emitter current I _EQ11 is the resistance
The emitter current I EQ12 is inversely proportional to the value of R ₁₃ and the emitter current I _EQ12 is inversely proportional to the value of R ₁₄
Since it is inversely proportional to the value of ln(R ₁₄ /R 13 ), the variation in the first term of equation (5) depends on ln(R 14 /R ₁₃ ). Since the relative accuracy of the values of two resistors integrated on an integrated circuit is within a few percent, ln (I _EQ11 / I _EQ12 ) = ln [A ₁ × (approximately 1.02 to 0.98)
] = A ₁ '+ (-0.02 to +0.02).

Next, in the second term of equation (5), since the emitter area S _o of the NPN transistor is the area formed by the glass mask for emitter diffusion, there is an absolute error of about 1 μm. The minimum emitter area S _o is 20 μm x 20 μm in the current standard process, so the accuracy during mass production is (20 ± 1) μm x (20
±1) μm. Similarly, the emitter area S _P of the PNP transistor is (20±1) μm×(20±1) μm. Since the glass mask that forms the emitter of the NPN transistor and the glass mask that forms the emitter of the PNP transistor are different, the variations in the emitter area have no correlation with each other, and the second term in equation (5) is: ln(S _o /S _P ) =ln [(20±1)×(20±1)/(20±1
) × (20±1) A ₂ ] = ln [A ₂ × (0.82 to 1.22)] = A ₂ ′+ (−0.20 to +0.20).

The third term in equation (5) is a term that depends on the impurity concentration and the depth of impurity diffusion, and is dependent on the control of the amount of impurity, temperature control, and diffusion time in the integrated circuit manufacturing process. . With current process technology, this variation is approximately 30 times larger, and the third factor in equation (5) is
The term is ln(D _o /W _o・P _P /D _P /W _P N _o )=ln [A ₃ ×(0.03 to 30)] = A ₃ ′+(−3.5 to +3.4).

Therefore, it can be seen that equation (5) is as follows.

(V _BEQ11 −V _BEQ12 )=KT/q・[(A ₁ ′+A ₂ ′+A ₃ ′)
+(-0.02~+0.02)+(-0.20~+0.20)+(-3.5
~3.4)]
...(5)' After determining the process to be adopted and by circuit design and mask design, the first term of the above equation (A ₁ ′ + A ₂ ′ + A ₃ ′)
is designed so that it is zero. However, the second to fourth terms remain as variations during mass production. By substituting T=300〓, equation (5) becomes (V _BEQ11 −V _BEQ12 ) = (−97mV to +94mV), and furthermore, this variation is mostly due to the absolute accuracy of the diffusion process of PNP transistors and NPN transistors. It can be seen that this is caused by

Based on the above premise, the purpose of the present invention is to obtain the output I _CQ12 of the constant current source shown in Fig. 1 (expressed by equation (1)).
This paper proposes a voltage shift circuit suitable for integration in order to eliminate voltage variations caused by the combination of PNP and NPN transistors that determine Therefore, one embodiment of the integrated voltage shift circuit of the present invention is shown and explained in FIG. 4.

Resistors R ₁₁ and R ₁₂ have the same function as the resistors in FIG. 1 and are therefore given the same reference numerals. Also, the transistor Q ₁₂ and resistor R ₁₄ on the right side of the drawing have the same functions as the transistor and resistor in FIG. 1, so they are given the same reference numerals. The part surrounded by the broken line corresponds to a voltage shift circuit using an emitter follower circuit of a PNP transistor. Transistor Q ₁ and transistor Q ₂ , resistor R ₁
constitutes a differential amplifier circuit, and the transistor
The bases of Q ₁ and Q ₂ are connected to the connection point between resistors R ₁₁ and R ₁₂ and to the emitter of transistor Q ₆ , respectively. Transistors Q ₃ and Q ₄ constitute a current mirror circuit, and serve as an active load of the differential amplifier circuit. Transistors Q ₅ , Q ₆ and resistor R ₂ constitute an emitter follower.
The operations of this differential amplifier circuit, current mirror circuit, and emitter follower are as follows. In other words, an amplifier circuit composed of a differential amplifier circuit and a current mirror circuit has an input terminal (transistor
There is a large voltage gain between the bases of Q ₁ and Q ₂ ) and the output terminal (collector of transistor Q ₄ ), approximately 10 ³ times. The emitter follower operates as a negative feedback circuit, with the input terminal (base of transistor Q ₅ ) connected to the output terminal of the amplifier circuit (collector of transistor Q ₄ ), and the output terminal (emitter of transistor Q ₆ ) connected to the amplifier circuit. One input terminal of (base of transistor Q ₂ )
connected to. Since the feedback ratio is 1, the voltages at the two input terminals of the amplifier circuit are equal to each other, that is, the base voltage V _BQ1 of the transistor Q ₁ and the base voltage V _BQ2 of the transistor Q ₂ are equal to each other.

Therefore the base voltage of transistor Q ₆ V _BQ6
V _BQ6 = V _BQ2 + V _BEQ6 = V _BQ1 + V _BEQ6 = R ₁₂ / R ₁₁ + R ₁₂ · V _CC + V _BEQ6 ...(6). From the above explanation, transistors Q ₁ to Q ₆ ,
It can be seen that the functions of resistors R ₁ and R ₂ are the same as those of PNP transistor Q ₁₁ and resistor R ₁₃ in FIG.

Next, the fact that there is little variation during mass production will be explained with reference to FIG. The output of a constant current source, i.e. a transistor
Find the collector current I _CQ12 of _Q12 .

I _CQ12 = 1/R ₁₄ [R ₁₂ /R ₁₁ +R ₁₂・V _CC +(V _BEQ6 −V _BEQ1
2 )] ...(7) Equation (7) has the same form as Equation (1) in the description of the conventional example in FIG. 1, but the fact that there is less variation during mass production will be explained below. The second term of equation (7) (V _BEQ6 −
Evaluate the variation in V _BEQ12 ). The following three equations are I _S(NPN) = q・S _o・D _o /W _o・n _i ² /P _P ……(2) V _BEQ6 =KT/qln(I _EQ6 /I _S(NPN)Q6 ) V _BEQ12 = KT/qln (I _EQ12 / I _S(NPN)Q12 ) Substituting into equation (7), (V _BEQ6 − V _BEQ12 ) = KT/q・ln (I _EQ6 / I _EQ12・I _S(NPN
)Q12 /I _S(NPN)Q6 ) =KT/q[lnI _EQ6 /I _EQ12 +lnS _o12 /S _o6 +ln(D _o12 /
W _o12 P _P12 /D _o6 /W _P6 P _P6 )]...(8) becomes. Here, S _o12 , D _o12 , W _o12 , and P _P12 represent the S _o , D _o , W _o , and P _P of the NPN transistor Q ₁₂ , respectively, and S _o6 , D _o6 , W _o6 , and P _P6 are the NPN transistors, respectively. Represents S _o , D _o , W _o , and P _P of Q ₆ .

The variation during mass production in equation (8) is the same as the first term in equation (5) above, lnI _EQ6 /I _EQ12 = ln [B ₁ × (approximately 1.02 to 0.98)] = B ₁ ′ + ( −0.02 to +0.02).

The second term in equation (8) is the ratio of the emitter areas S _o6 and S _o12 of the two NPN transistors, and since they are areas formed by the same glass mask, it indicates relative accuracy and is approximately lnS _o12 /S _o6 =B ₂ ′+ (-0.02 to +0.02).

Finally, the third _term in equation (8) depends on the control of the amount of impurities, temperature control, and control of diffusion time in the integrated circuit manufacturing process _.
Since both are NPN transistors, the emitter region and base region are formed using the same glass mask, and the emitter region and base region are formed using the same diffusion process. Therefore, since the impurity concentration and the diffusion depth match well, the third term in equation (8) is ±10
With a variation of %, ln(D _o12 /W _o12・P _P12 /D _o6 /W _o6・P _P6 ) = ln[B ₃ × (0.90 to 1.1)] B ₃ ′+ (−0.1 to +0.1) Become.

Therefore, the value of equation (8) is (V _BEQ6 −V _BEQ12 )=KT/q [(B ₁ ′+B ₂ ′+B ₃ ′)
+(-0.02~+0.02)+(-0.02~+0.02)+(-0.1
~+0.1)]
...(8)′ The first term (B ₁ ′+B ₂ ′+B ₃ ′) in the above equation is designed to be zero by circuit design and mask design. T
= 300〓, it turns out that (V _BEQ6 − V _BEQ12 ) = (−3.6 mV to +3.6 mV). The value of equation (5) above (−
97mV to +94mV), it can be seen that the variation is significantly reduced. As described above, by employing the embodiment of the present invention shown in FIG. 4, a very stable constant current output can be obtained despite variations in the manufacturing process of integrated circuits.

Now, Fig. 2 shows a video signal amplification circuit using the conventional voltage shift circuit shown in Fig. 1.
An example of an integrated circuit using the voltage shift circuit of the present invention in the circuit shown in the figure is shown in FIG. Explain in detail. That is,
FIG. 2 shows a conventional circuit, FIG. 5 shows another embodiment of the present invention, and FIG. 6 shows an explanatory diagram thereof. FIG. 2 shows a circuit that inputs a composite video signal to the input terminal Tin, clamps it, amplifies it, and outputs it from the output terminal Tout. A voltage V _ref is created by dividing the power supply voltage V _CC using resistors R ₁₅ and R ₁₆ .

V _ref =R ₁₆ /R ₁₅ +R ₁₆ ·V _CC voltage V _ref is applied to the base of transistor Q ₁₃ . The emitter of transistor _Q13 is a transistor
Connected to the base of Q ₁₄ , resistor R ₂₁ and capacitor C ₁ .
A composite video signal whose waveform is shown in FIG. 6 is applied to the input terminal Tin. In the transistor _Q13 , an emitter current flows only during the period of the horizontal synchronization signal of the composite video signal, and does not flow during the remaining period. In this way, the sync chip voltage is clamped to (V _ref − V _BE13 ) by the capacitor C ₁ and the transistor Q ₁₃ [Figure 6b], where V _BEQ13 is the voltage of the transistor Q ₁₃ during the horizontal synchronization signal period. This is the voltage between base and emitter. Note that the value of resistor R ₂₁ is the same as transistor Q ₁₄
The resistance value should be a little larger than the value of the base current of , allowing approximately twice the current to flow to the ground.

The transistor Q ₁₄ and the resistor R ₁₇ are emitter followers, and the voltage of the composite video signal at the emitter of the transistor Q ₁₄ is (V _ref −V _BEQ13 +V _BEQ14 ) during the period of the horizontal synchronization signal (9) It is becoming. This waveform is the transistor Q ₁₅ ,
It serves as one input signal of a differential amplifier circuit composed of Q ₁₆ , resistors R ₁₈ , R ₁₉ , and R ₂₀ . Another input signal is the divided voltage _Vref . Then, the amplified composite video signal is transmitted to transistor _Q16.
is obtained from the collector of and led to the output terminal Tout.

In a circuit configured in this manner, the voltages of the two input signals of the differential amplifier circuit must be equal during the period of the horizontal synchronization signal.

That is, (V _ref −V _BEQ13 +V _BEQ14 ) must be V _ref . However, as explained in the example of Figure 1, V _BEQ13 of NPN transistor _Q13
It is difficult to match V _BEQ14 of PNP transistor _Q14 considering the variation during mass production. Furthermore, new problems compared to FIG. 1 are as follows. Due to the small value of the emitter current of transistor _Q13 (which flows only during the horizontal synchronization signal period)
The value of V _BEQ13 is also small. Corresponding to this small value of V _BEQ13 , the V _BEQ14 of PNP transistor Q ₁₄ must be made small. To reduce V _BEQ14 ,
What can be done in terms of circuit and mask design is: V _BEQ14 = KT/qlnI _EQ14 /I _S(PNP) = KT/qlnI _EQ14・W _P・N _o /qS _P・D _P・n _i ² From the above equation, emitter current I _EQ14 or increase the emitter area S _P. Regardless of which option is selected, the conventional video amplification circuit using a shift circuit has a defect in that the frequency characteristics of the transistor _Q14 deteriorate and the high frequency components of the composite video signal cannot be transmitted.

FIG. 5 shows another embodiment of the present invention for eliminating the problem of the circuit of FIG. 2 described above. Elements having the same functions as those in FIGS. 2 and 4 are given the same reference numerals. Transistor Q ₁₃ , resistor ₁₅ , R ₁₆ , and capacitor C ₁ clamp the composite video signal. The clamped composite video signal is input to the base of transistor _Q1 .
Transistors Q ₁ to Q ₆ and resistors R ₁ and R ₂ have the same circuit configuration as those shown in FIG. 4, and operate in the same manner. Therefore, the base voltage _BQ6 of the transistor _Q6 is V _BQ6 = (V _ref - V _BEQ13 ) + V _BEQ6 during the horizontal synchronization signal period. Here, V _BEQ6 is the voltage between the base and emitter of transistor _Q6 . transistor
_Q6 is designed to have as large an emitter area S _o6 as necessary, and the value of V _BEQ6 is small and equal to V _BEQ13 . Also, regarding frequency characteristics, there is no problem because the collector and base of transistor _Q6 are connected to the emitter of transistor _Q5 , which operates as an emitter follower.

As described above, according to the present invention, it is possible to obtain a voltage shift circuit that is extremely stable against variations in the manufacturing process of integrated circuits.
Base due to differences in the structure of NPN transistors,
This suppresses manufacturing variations in output current due to voltage fluctuations in a voltage shift circuit caused by relatively large variations in voltage between emitters, thereby realizing an integrated circuit with a high yield.

[Brief explanation of drawings]

Figure 1 is a constant current circuit diagram using a conventional voltage shift circuit, Figure 2 is a video signal amplification circuit diagram using a conventional voltage shift circuit, and Figure 3 is a diagram of an NPN and PNP transistor used in integrated circuits. Structural sectional views, FIGS. 4 and 5 are circuit diagrams of an embodiment in which the voltage shift circuit of the present invention is applied to the circuits of FIGS. 1 and 2, respectively, and FIGS. 5 is a diagram showing a voltage waveform of a video signal for explaining FIG. 5; FIG. Q ₁ , Q ₂ ...transistors constituting a differential amplifier, Q ₃ , Q ₄ ...current mirror transistors,
Q ₅ , Q ₆ ... Emitter follower transistor.

Claims (1)

[Claims] 1 In a voltage shift circuit configured on a semiconductor integrated circuit, first and second
and third and fourth transistors forming a current mirror circuit serving as an active load of the differential amplifier circuit, wherein the first and second transistors are of the same conductivity type and the third and fourth transistors are of the same conductivity type. The first and third transistors are of a conductivity type opposite to that of the fourth transistor, and the collectors of the first and third transistors are connected to each other, and the collectors of the second and fourth transistors are also connected to each other,
Further, the base of the fifth transistor is connected to the collector of the second transistor, the emitter of the fifth transistor is connected to the collector and base of the sixth transistor, and the emitter of the sixth transistor is connected to the collector of the second transistor. The fifth and sixth transistors are transistors of the same conductivity type as the first and second transistors, and the voltage at the base of the first transistor is connected to the base of the fifth transistor. A voltage shift circuit characterized in that the voltage is shifted and appears at the emitter of.