JPH0150036B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory access control method in an information processing system.

In recent years, with the advancement of semiconductor technology, especially integration technology, 1
It has become possible to mount a large number of logic elements in a single package, such as a microprocessor (MPU),
256K bits of random access memory (RAM)
became available at low prices.

Such highly integrated circuits (LSI) or multiple
For printed circuit boards equipped with LSIs to achieve more advanced functions, there is a limit to the number of connection terminals required for external connection.For example, for printed circuit boards equipped with multiple LSIs, There is a limit to the number of connection pins that can be attached to the device, making it impossible to improve functionality.

[Conventional technology]

Stores conventional character or binary image data,
So-called ALTER/DISPLAY, which writes data for replacement and reads data for display display.
Taking memory control for example, we separate memory control units for each character or binary image attribute, so
The number of control units increases depending on the number of attribute types, and the number of control lines increases.

In an example where an MPU is used for control and n RAMs are used as external memory, each as a control unit, each
Each RAM has a write instruction line (WE) and a read instruction (OE) line, and each RAM has a common ground line (GND), power supply line (Vcc), and address line. , each RAM is also used for reading.
There is a data line (bus) that can be shared.

When connecting such n RAMs to an MPU, even if you try to share and use them as much as possible,
For example, the storage capacity of one RAM is 64Kb (8b×
8KW), then 8 data lines and 13 address lines for 13 bits (2 ¹³ ) addressing 8KW.
The total number of pins N is N = 2n + 8 + 13 + 2, and when n = 8, there are as many as 39 pins.Therefore, a system was desired that would require fewer pins even if n increased.

[Problem that the invention seeks to solve]

If you try to accommodate the above n RAMs in an LSI package or printed board, the number of connection pins mounted on the LSI package or printed board will be limited, which will limit the number of RAMs n, which will limit high-density packaging. There is a problem.

On the other hand, the data transfer speed of the memory for ALTER/DISPLAY mentioned above is less than 5Mb/s,
The present invention attempts to solve this problem by minimizing the number of connection pins required for such low speeds.

[Means to solve the problem]

The object of the present invention is to provide a memory system in which a control section writes and reads data for each control unit of a memory consisting of a plurality of control units.
Each control unit of the memory is provided with respective shift registers for write data, read data, and address data, and a control unit designation shift register in which one stage corresponds to each control unit, and each of the shift registers is All are connected in series to form a scan chain, and the input end and output end of the scan chain are connected to the control section, and a scan clock pulse for shifting the scan chain is controlled by the control section. When writing, the control section prepares designation data, write data, and address data of a control unit for writing, and controls the clock generation section to generate the scan chain. By shifting a predetermined number of stages, each data is set in the input terminal or each register corresponding to the specified control unit, and then written. When reading, the specified data and address data of the control unit to be read are set. After setting each data from the input terminal to each register corresponding to the specified control unit by controlling the clock generation section and shifting the scan chain a predetermined number of stages, Achieved by a memory control method characterized in that reading is performed in the read shift register, and then the clock generator is controlled again to shift the data a predetermined number of stages, and the data in the read shift register is read by receiving the data from the output terminal. be done.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings.

The figure is a block diagram of a control system according to an embodiment of the present invention.

The SVP 1 has a control shift register (not shown), which is a control section that receives requests from the outside and selects, reads, and writes n RAMs 3a to 3n, each of which is a control unit, to be described later.

RAM3a to 3n of each control unit has a shift register and a write register, respectively, as shown in the figure.
WDREG4a to 4n, read register RDREG5a
~5n and address register ADREG6a~6n
In addition, each stage is provided with RAM 3a to 3 respectively.
Flip-flop (stage) FF7a~ corresponding to n
A control unit designation shift register having 7n is provided.

These shift registers 4a to 4n, 5a to 4n are provided corresponding to the RAMs 3a to 3n of each control unit.
5n, 6a to 2n, and 7a to 7n are all serially connected (in this embodiment, serially connected clockwise in the figure), and the input end SI and output end SO are used for controlling the control unit SVP1, respectively. In this embodiment, it is connected to the output end and the input end of the shift register, forming a loop-shaped scan chain.

The control shift register is a register with the maximum number of stages among the registers of each control unit (in this embodiment, address shift registers ADREG6a to ADREG6
The number of stages is n), and the input end SI and the output end SO of the scan chain are connected in series.

The scan chain is a scan clock generated by the control section SVP1 controlling the clock generation section 2.
SCLK is supplied to each stage, and by controlling the number of generated clocks, it is possible to shift the scan chain by a predetermined number of stages.

On the other hand, a write instruction signal WE is sent from the control unit SVP1.
Alternatively, a read instruction signal OE is output, and as shown in the figure, this signal is ANDed with the outputs of stages FF7a to 7n of the control unit designation shift register.
The memory of the control unit designated by is selected and writing or reading is instructed.

Next, write and read operations will be explained.

During writing, the control unit SVP1 sequentially prepares address data, write data, and data specifying the control unit to be written (specified by bit position) in a predetermined stage of the control register, and controls the clock generator 2. By shifting the scan chain a predetermined number of stages, the prepared data can be transferred to the input terminal of the scan chain.
After setting each register corresponding to the control unit specified by SI, the control unit SVP1 sends the write instruction signal WE.
The write shift register WDREG writes to the address of the address register ADREG in the specified RAM.

This setting operation of each register is performed when a scan chain is configured, the order (position) of each stage of each shift register on the scan chain is divided, and data is prepared in the control shift register and the position of the next data is set. By performing the following operations for the required data at a predetermined number of shift stages, the prepared data is set in each register. You can. This principle is the same in the case of reading.

At the time of reading, the control unit SVP1 prepares address data and specification data of the control unit to be read, and controls the clock generation unit 2 to shift the scan chain by a predetermined number of steps, thereby inputting each data as specified from the input terminal SI. After setting in each register corresponding to the specified control unit, the control unit SVP1 sends a read instruction signal 0E, reads the data at the address of the address register ADREG to the read shift register RDREG in the specified control unit, and
Thereafter, reading can be performed by controlling the clock generating section 2 again to shift the clock by a predetermined number of stages and receiving the data in the read shift register RDREG from the output terminal SO to the control shift register.

As described above, data writing and reading according to the method of the present invention is performed using a shift operation using a clock of a scan chain in which each register is used as a shift register and all shift registers are connected in series, so the transfer speed is reduced. scan clock
Each SLCK clock is equivalent to serial transmission of 1 bit, and the period of scan clock SLCK is
If it is 200ns, it will be about 5Mb/s, but as mentioned above
It is sufficient for purposes such as ALTER/DISPLAY.

On the other hand, when the present invention is applied to the example described in the prior art section for n RAMs, the required number of pins N is (SI+SO)+(WE+0E)+(SLCK×2)+(GND+Vcc)=8, The part that increases in proportion to n disappears,
n becomes irrelevant, and when n is 8, 8/39≒1/4
reduced to

〔Effect of the invention〕

As explained above, according to the present invention,
For applications such as ALTER/DISPLAY that require relatively low-speed read and write operations, it is possible to use a plurality of control units of memory with a minimum number of connection pins.

[Brief explanation of drawings]

The figure is a block diagram of one embodiment of the present invention. In the figure, 1 is the control unit SVP, 2 is the clock generator, and 3a
~3n is random access memory RAM, 4a~
4n is a write register WDREG, 5a to 5n are read registers RDREG, 6a to 6n are address registers ADREG, 7a to 7n are flip-flops FF,
It is.

Claims (1)

[Scope of Claims] 1. In a memory system in which a control unit writes and reads data for each control unit of a memory consisting of a plurality of control units, write data, read data, and Each shift register for address data and a control unit designation shift register in which one stage corresponds to each control unit are provided, and all of the shift registers are connected in series to form a scan chain. an input terminal and an output terminal of the clock are connected to the control section, and a clock generation section that generates a scan clock pulse for shifting the scan chain under the control of the control section; At the time of writing, specifying data, write data, and address data of the control unit to be written are prepared, and the scan chain is shifted by a predetermined number of steps by controlling the clock generator.
Each data is set from the input terminal to each register corresponding to the specified control unit and then written. When reading, the specified data and address data of the control unit to be read are prepared, and the clock generator is activated. By controlling and shifting the scan chain a predetermined number of stages, each data is set from the input end to each register corresponding to the designated control unit, and then read out to the read shift register of the designated control unit. . A memory control system characterized in that reading is performed by subsequently controlling a clock generating section again to shift a predetermined number of stages and receiving data from the read shift register from the output terminal.