JPH0152834B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, particularly as a load.
The present invention relates to a semiconductor memory including a memory cell having a PNP transistor.

As shown in FIG. 1, a memory cell with a PNP transistor as a load has multi-emitter transistors T ₁ , T ₂ and PNP transistors T ₃ , T ₄ forming a flip-flop _. Each first emitter of ₂ is a bit line.
The second emitters of B ₀ and B ₁ are commonly connected to the word line W ^- .

The emitters of the load PNP transistors T ₃ and T ₄ are connected to the word line W ⁺ .

In such a memory cell, among the transistors constituting the flip-flop, the collector load of the on-side transistor, for example _T1 , becomes a diode at the emitter base of the PNP transistor _T3 , so its voltage and current characteristics are as shown in Figure 2. Shows the characteristics of Zc.

Therefore, it can operate with a wide range of current, and can operate with a small holding current and a large read current.
A semiconductor memory with low power consumption and high speed operation will be realized. Also, the on-side transistor of this memory cell
The base side impedance of _T1 exhibits the saturation region characteristics of a PNP transistor as shown by _ZB in FIG. 2, so it is a low impedance, and the parasitic capacitance attached to the base node can be charged up in a short time. As shown in Figure 3, in a memory cell using a resistor R _L as a load, this resistor R _L
In this sense, the PNP-loaded memory cell shown in Figure 1 consumes less power and can be read at higher speeds than the memory cell shown in Figure 3. It can be called a memory cell.

FIG. 4 shows a semiconductor memory equipped with such a PNP-loaded memory cell.

The memory cells shown within the broken lines in the figure are the same as the memory cells in FIG. 1, and the transistors Tc _{1 and} Tc ₂ are the transistors T ₁ and _{T 2 in} FIG. Transistors T ₃ and T ₄ in the figure
corresponds to Note that one emitter of each of TC ₁ and TC ₂ is connected to a holding current source _IH . The emitters of a pair of transistors Ts ₀ , Ts 1 are connected to the bit lines B ₀ , B ₁ , and the potentials V _D0 , Ts ₁ are connected to their respective bases.
V _D1 is applied, and each collector is connected to a sense amplifier SA. Bit lines B ₀ , B ₁
Further connected to the transistors are a pair of transistors T _B0 and T _B1 to which a potential V _Y is applied to their respective bases, and bit line current sources I _B0 and I _B1 . Transistor T _B0 ,
The emitters of T _B1 are respectively coupled to other bit line groups, and only transistors T _B0 and T _B1 of the bit line group to which a high level signal is applied to V _Y are turned on.

Next, the word line W ⁺ is set to H by the decoder circuit DEC.
The read and write operations will be described when the memory cell in the figure is accessed with the level _VY also at the H level.

(1) Read operation Set the base potential of transistors Ts ₀ and Ts ₁ to V _D0 =
V _D1 , and this potential is set to an intermediate level between the base potential and collector potential of the on-side transistor of the memory cell, for example, T _C1 .

Transistors Tc ₁ and Ts ₀ , transistor Tc ₂
and Ts ₁ constitute a current switch, so Ts ₀ is off, Ts ₁ is on, and the current i _B1
is detected by Senseup SA,
The contents of the memory cell are read.

(2) Write operation A case will be described in which inverted information is written by turning off the on-side transistor Tc ₁ and turning on the off-side transistor Tc ₂ in the memory cell.

The base potential of the transistor Ts ₀ is set to H level,
If the base potential of Ts ₁ is set to L level, the current source
The current drawn by I _B1 is _the transistor Tc ₂
, the collector potential of Tc ₂ , that is, Tc ₁
The base potential V _B of is lowered, and the transistor Tc ₄ is turned on.

As a result, the collector current of the transistor Tc ₄ charges up the base potential Vc of the transistor Tc ₂ , and at the same time, the potential V _B of the transistor Tc ₂
Since the voltage decreases due to the collector current of the transistor
Tc ₁ is turned off, then Tc ₂ is turned on and writing to the memory cell is performed.

Therefore, the write time becomes shorter as the current i _{B1 drawn by the current terminal I B1 increases} , but if the current drawn into the current sources I _B0 and I _B1 is constantly increased, the memory cell Since a large current flows through the cell, the accumulated charge inside the cell increases and the writing time becomes longer.

An object of the present invention is to solve these conventional drawbacks and provide a semiconductor memory that consumes low power and can be written at high speed.

According to the present invention, this purpose is achieved by a pair of transistors constituting a flip-flop;
1 memory cell with PNP load transistor
In a semiconductor memory connected between a pair of bit lines, a bit line selection means connected to the bit line, a first current source connected to the bit line selection means, and a current source larger than the first current source are provided. A second current source for flowing current, a read/write control means for inputting a write instruction signal and write data and outputting first and second control signals, and the first control signal, When reading the memory cell, the first
Only the current of the current source is passed through the bit line, and the second
bit line current switching means for causing the currents of the first and second current sources to flow through the bit line during writing; A clamp that clamps the potential of the bit line connected to the transistor that should be turned on to a low level and the potential of the bit line connected to the transistor that should be turned off to a high level among a pair of transistors that make up a flip-flop. This is achieved by providing means.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 is a circuit diagram showing an embodiment of the present invention, in which a write instruction signal and write data D _IN are input, and potentials Vw ₀ and D IN corresponding to this and D _IN are input.
Read/write control circuit WA that outputs Vw ₁ and related transistors Tw ₀ , Tw ₁ , T _D0 , T _D
1 , current sources Ic ₀ , Ic ₁ and diodes D ₀ , D ₁ , transistors Tw ₃ , Tw ₄ , current sources I ₀ , I ₁ , and a transistor T _B0 to which the potential V _Y is applied to the base;
Current sources Iw ₀ , I _R0 , Iw ₁ , I _R1 , and Is connected to T _B1 , Ts ₂ and the emitters of these transistors are added to the conventional circuit shown in FIG. 1.

The bases of the transistors Ts ₀ and Ts ₁ connected to the sense amplifier SA are connected to the bit lines B ₀ and B 1, and the commonly connected emits of the transistors Ts 0 and Ts ₁ are connected to the bit lines B 0 and B 1.
Connected to Ts ₂ .

The read/write operations of this embodiment will be explained next.

(1) Read operation When the write instruction signal is at H level, the outputs Vw ₀ and Vw ₁ of the control circuit WA are equal, and their value is as follows, assuming that the forward voltage drop of the diodes D ₀ and D ₁ is V _F. It is set to satisfy Vw ₀ (=Vw ₁ )−V _F >V _Y.

Therefore, transistors Tw ₃ and T _B1 and
In each current switch Tw ₄ and T _B0 , transistors Tw ₃ and Tw ₄ are turned on, so the current source
The currents iW ₀ and iW ₁ drawn into Iw ₀ and Iw ₁ flow through the transistors Tw ₃ and Tw ₄ , and the currents iW 0 and iW 1 drawn into the transistors T _B
0 , T _B1 does not flow.

Also, from the potential of the output Vw ₀ (=Vw ₁ ), the base-emitter voltage V _BE of the transistors Tw ₁ and Tw _2
The potential obtained by subtracting _. Tc ₁ , Tc ₂ ) in Fig. 4 and transistor T _D0 ,
T _D1 constitutes a current switch.

Therefore the left transistor in the cell (Tc ₁ )
is on, the potential of bit line B ₀ is determined from within the cell, and the potential of bit line B ₁ is determined from output Vw ₁ , creating a potential difference between bit lines B ₀ and B ₁ .

This potential difference is caused by the transistors Ts ₀ , Ts ₁ ,
It is detected by a differential switch consisting of Ts ₂ and current source Is, and data Dout is output from the sense amplifier SA.

At this time, the current flowing from the memory cell to the bit line _B0 is the current i _R0 drawn by the current source I _R0 , and since i _R0 , i _R1 < iW ₀ , iW ₁ is set, when reading, the current inside the cell is The current flowing through can be reduced.

Therefore, the charge accumulation effect of the PNP transistor in the memory cell can be reduced, and writing can be performed at high speed.

(2) Write operation The case of turning on the transistor Tc ₂ on the right side of the memory cell will be explained.

Write instruction signal is L level, input data
When D _IN is at L level, Vw ₁ −V _F ＜V _Y ＜Vw ₀
Potentials Vw ₀ and Vw ₁ that satisfy −V _F are output.

As a result, the current drawn into the current source _Iw1 flows through the bit line _B1 through the transistor T _B1 , and moreover, the potential of the bit line _B1 is the same as that of the transistor T _D1.
Since it is determined by the base potential determined by Vw ₁ −V _BE , the level is sufficiently low and a large write current flows through the transistor (Tc ₂ ) on the right side of the cell, so that writing is performed at high speed.

On the other hand, regarding the bit line _B0 , the current _iW0 flows bypassing the transistor _Tw4 , so only the current _iR0 flows through this bit line, but the transistor TD0, which is turned on by the high potential _Vw0 , flows through the bit line _B0.
It flows from the cell, but not from the cell.

In this way, when reading, a small current flows from the on-side transistor in the cell to reduce the charge accumulation effect, while during writing, the bit line on the side of the transistor that is to be turned on in the memory cell is clamped to a low level. Therefore, these two effects combine to speed up the write operation.

The read/write control circuit described above is specifically shown in FIG. 6, and includes transistors T ₆₁ ,
It has T ₆₂ , T ₆₃ , T ₆₄ , diodes D ₂ , D ₃ , and current source I ₂ , and has a configuration to which reference voltages _VR1 and _VR2 are applied.

Since this control circuit WA has already been proposed in Japanese Patent Application No. 84819/1984, its detailed operation will be omitted.

FIG. 7 is a circuit diagram showing another embodiment of the present invention, in which the clamp level of the bit line and the transistors T _B0 and T _B1 are controlled based on D _IN and _IN as inputs of the read/write control circuit WA. A circuit WA' is shown for selecting the current sources Iw ₀ , Iw ₁ , I _R0 , I _R1 which are connected via the bit line to the bit lines.

In the case of a read operation, becomes H level and Vw ₀ =Vw ₁ is output.

At this time, the transistor T ₇₁ is on and the base potential of the transistors Tw ₃ and Tw ₄ is higher than V _Y , so the currents iW ₀ and iW ₁ are transferred to the transistors Tw ₃ and
Flows through Tw ₄ .

On the other hand, in the case of a write operation, Vw ₀ and Vw ₁ are set to L level depending on the levels of D _IN and _IN .
At the same time, the transistors Tw ₃ and Tw ₄
Either one of them is turned off.

As explained above, according to the present invention,
The write operation of a semiconductor memory including a memory cell using a PNP transistor as a load can be made faster.

[Brief explanation of drawings]

Figure 1 is a diagram showing a memory cell with a general PNP transistor as a load, Figure 2 is a diagram showing the characteristics of the memory cell in Figure 1, and Figure 3 is a diagram showing a general memory cell with a resistor as a load. 4 is a diagram showing a conventional semiconductor memory, FIG. 5 is a diagram showing an embodiment of the present invention, and FIG. 6 is a diagram showing the reading of FIG.
FIG. 7, a diagram showing a write control circuit, is a diagram showing another embodiment of the present invention. Tc ₁ , Tc ₂ : Transistors forming the flip-flop, Tc ₃ , Tc ₄ : PNP load transistors,
B ₀ , B ₁ : Bit line, T _B0 , T _B1 : Transistors constituting bit line selection means, I _R0 , I _R1 : First current source, Iw ₀ , Iw ₁ : Second current source, WA: reading·
Write control means, Tw ₃ , Tw ₄ : transistors forming bit line current switching means, T _D0 , T _D1 : transistors forming clamp means.

Claims (1)

[Claims] 1. In a semiconductor memory in which a pair of transistors constituting a flip-flop and a memory cell having a PNP load transistor are connected between a pair of bit lines, a bit line selection means connected to the bit line, and a bit line selection means connected to the bit line; the first connected to the means
a current source for passing a current larger than that of the first current source; and a read current source for inputting a write instruction signal and write data and outputting first and second control signals. a write control means;
A control signal causes only the current of the first current source to flow through the bit line when reading the memory cell;
bit line current switching means for causing currents of the first and second current sources to flow through the bit line during writing according to the second control signal;
When writing to the memory cell, the potential of the bit line to which the transistor to be turned on is connected is set to a low level among the pair of transistors forming the flip-flop of the memory cell, and the transistor to be turned off is connected to the bit line. A semiconductor memory characterized by being provided with clamping means for clamping the potential of a bit line to a high level.