JPH0152900B2 - - Google Patents
Info
- Publication number
- JPH0152900B2 JPH0152900B2 JP14941283A JP14941283A JPH0152900B2 JP H0152900 B2 JPH0152900 B2 JP H0152900B2 JP 14941283 A JP14941283 A JP 14941283A JP 14941283 A JP14941283 A JP 14941283A JP H0152900 B2 JPH0152900 B2 JP H0152900B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- carbon
- film
- semiconductor substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052799 carbon Inorganic materials 0.000 claims description 47
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 31
- 230000000903 blocking effect Effects 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 25
- 238000002347 injection Methods 0.000 description 13
- 239000007924 injection Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000002513 implantation Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 150000001721 carbon Chemical class 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に関するもの
で特にコンタクトホール部分で段切れの恐れのな
い絶縁膜を有する半導体装置の製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an insulating film that is free from breakage at contact hole portions.
従来より用いられている半導体装置内の素子間
を接続する配線部の形成方法の概略は次のような
ものである。すなわち、第１図に示すように、不
純物の選択拡散或いは選択注入技術を用いて、半
導体基板１１に所定の素子領域１２を形成すると
共に半導体基板１１の上面にシリコン酸化膜等の
絶縁膜１３を形成する。そして、この絶縁膜１３
に第２図に示すように窓明けを行い、素子接続部
となる部位に開口部１４を形成する。次いで半導
体基板１１内の素子領域１２と後に形成される配
線層との良好な接続性が得られるように、上記開
口部１４からn+（またはp+）イオン注入を用い高
濃度のイオン注入層１５を開口部１４直下に形成
する。
The outline of a conventionally used method for forming a wiring portion that connects elements in a semiconductor device is as follows. That is, as shown in FIG. 1, a predetermined element region 12 is formed in a semiconductor substrate 11 using selective diffusion or selective implantation technology of impurities, and an insulating film 13 such as a silicon oxide film is formed on the upper surface of the semiconductor substrate 11. Form. Then, this insulating film 13
Then, as shown in FIG. 2, a window is opened and an opening 14 is formed at the part that will become the element connection part. Next, in order to obtain good connectivity between the element region 12 in the semiconductor substrate 11 and the wiring layer to be formed later, a highly concentrated ion-implanted layer is implanted using n + (or p + ) ions from the opening 14. 15 is formed directly below the opening 14.
続いて第３図に示すように上記イオン注入層１
５の活性化熱処理等を行い、同時にこの熱処理時
に基板１１表面に薄い酸化膜１３ｓを形成する。 Subsequently, as shown in FIG. 3, the ion implantation layer 1 is
At the same time, a thin oxide film 13s is formed on the surface of the substrate 11 during this heat treatment.
次いで、第４図に示すように上記酸化膜１３ｓ
に所定形状のコンタクトホール１４ｃを開口す
る。 Next, as shown in FIG. 4, the oxide film 13s is
A contact hole 14c of a predetermined shape is opened.
続いて第５図に示すように、基板の上面に金属
膜１６を被着し、所定のパターンにパターニング
することにより各素子領域を接続する配線層を形
成する。 Subsequently, as shown in FIG. 5, a metal film 16 is deposited on the upper surface of the substrate and patterned into a predetermined pattern to form a wiring layer connecting each element region.
以上のようにして形成した装置では、絶縁膜１
３に開口部１４を形成するが、この開口部１４の
断面が急峻で大きな段差を有するため、この段差
部上に形成される金属膜１６に第５図のａで示す
ようないわゆる段切れと呼ばれる配線切れを生じ
やすいものであつた。 In the device formed as described above, the insulating film 1
3, but since the cross section of this opening 14 is steep and has a large step, the metal film 16 formed on this step has a so-called step break as shown in a of FIG. It was easy to cause what is called a wire breakage.
このような従来の装置の段切れの対策として、
例えば、第６図に示すように、半導体基板１１上
に絶縁膜１３としてシリコン酸化膜１３0および
低温の熱処理で軟化する例えばBSG（ホウ素シリ
ケートガラス）膜１３1等を順に積層被着して、
絶縁膜１３の窓明け後熱処理を行つて絶縁膜１３
の段差を滑らかにする方法もある。このようなも
のでは、金属膜１６の段切れは防止できるもの
の、工程が煩雑であるという欠点があつた。 As a countermeasure against breakage in conventional equipment,
For example, as shown in FIG. 6, a silicon oxide film 130 and, for example, a BSG (boron silicate glass) film 131, which is softened by low-temperature heat treatment, are sequentially deposited as an insulating film 13 on a semiconductor substrate 11.
After opening the window of the insulating film 13, heat treatment is performed to form the insulating film 13.
There is also a way to smooth out the differences in height. Although such a device can prevent the metal film 16 from breaking, it has the disadvantage that the process is complicated.
また、これらの方法では配線層との接続部分で
はn+（またはp+）イオン注入用の開口部１４とコ
ンタクトホール１４ｃとのマスク合わせ精度を考
慮してコンタクト部分の面積の余裕をかなり大き
くする必要があり、素子の微細化を阻んでいた。 In addition, in these methods, in the connection portion with the wiring layer, the margin of area of the contact portion is considerably increased in consideration of mask alignment accuracy between the opening 14 for n + (or p + ) ion implantation and the contact hole 14c. This was necessary and hindered the miniaturization of elements.
また、この他に、いわゆるLOCOS（LOCal
Oxidation of Silicon）法によりシリコン基板表
面に選択的に酸化膜を形成する方法もある。この
方法は、シリコン基板表面にシリコン窒化膜を被
着し、このシリコン窒化膜をパターニングし、さ
らにこのシリコン窒化膜を耐酸化性マスクとして
シリコン基板表面を選択酸化してシリコン酸化膜
のパターンを形成し、不要となるシリコン窒化膜
を除去するものである。この方法によれば、シリ
コン酸化膜の開口部の断面は滑らかなものとなる
が、シリコン窒化膜の被着工程およびそのパター
ニング工程、さらには選択酸化終了後の不要なシ
リコン窒化膜パターンの除去工程が煩しいという
欠点を有していた。 In addition to this, so-called LOCOS (LOCal
There is also a method of selectively forming an oxide film on the surface of a silicon substrate using the Oxidation of Silicon method. This method involves depositing a silicon nitride film on the surface of a silicon substrate, patterning this silicon nitride film, and then selectively oxidizing the silicon substrate surface using this silicon nitride film as an oxidation-resistant mask to form a pattern of silicon oxide film. Then, the unnecessary silicon nitride film is removed. According to this method, the cross section of the opening in the silicon oxide film becomes smooth, but there are also steps in the deposition process of the silicon nitride film, its patterning process, and the removal process of unnecessary silicon nitride film patterns after selective oxidation. It has the disadvantage that it is cumbersome.
この発明は上記のような点に鑑みなされたもの
で、その目的とするところは段切れの恐れのな
い、緩やかな段面構造の絶縁膜を有する装置を簡
易に製造することのできる半導体装置の製造方法
を提供し、生産性の向上を図ろうとするものであ
る。
The present invention was made in view of the above points, and its purpose is to provide a semiconductor device that can easily manufacture a device having an insulating film with a gradual stepped structure without the fear of step breakage. The aim is to provide a manufacturing method and improve productivity.
すなわちこの発明に係る半導体装置の製造方法
では、半導体基板の上面に例えばシリコン酸化膜
或いはレジスト膜等からなる炭素導入阻止膜を形
成しこの炭素導入阻止膜をパターニングし、この
炭素導入阻止膜をマスクとして半導体基板の上面
部分に選択的に炭素を導入し炭素導入層を形成す
る。そして上記炭素導入阻止膜を除去した後、半
導体基板の上面を酸化させ酸化膜を形成する。こ
こで炭素導入層では導入した炭素の量に依存して
酸素の拡散速度が低下する。すなわち炭素を多量
に含んだ領域を設けることにより、この炭素を含
んだ領域およびその下部に位置する例えば酸化膜
部分やシリコン基板界面への酸素供給量をその他
の領域と比較し減少させて、その領域における酸
化膜の成長量を抑制できる。その結果炭素導入層
に相当する部位には炭素を含む薄い酸化膜部分が
形成され、炭素導入層以外の領域に上記薄い酸化
膜部分と緩やかに連続した厚い酸化膜部分が形成
される。その後、薄い酸化膜部分が除去され厚い
酸化膜部分が残るように薄い酸化膜部分と厚い酸
化膜部分とを同一速度でエツチングし、上記炭素
導入層に相当しない領域に緩やかな開口部断面を
有する残留酸化膜を形成するようにしたものであ
る。
That is, in the method for manufacturing a semiconductor device according to the present invention, a carbon introduction prevention film made of, for example, a silicon oxide film or a resist film is formed on the upper surface of a semiconductor substrate, this carbon introduction prevention film is patterned, and this carbon introduction prevention film is used as a mask. As a step, carbon is selectively introduced into the upper surface portion of the semiconductor substrate to form a carbon-introduced layer. After removing the carbon introduction blocking film, the upper surface of the semiconductor substrate is oxidized to form an oxide film. Here, in the carbon-introduced layer, the oxygen diffusion rate decreases depending on the amount of introduced carbon. In other words, by providing a region containing a large amount of carbon, the amount of oxygen supplied to this carbon-containing region and the oxide film portion or silicon substrate interface located below it, for example, is reduced compared to other regions. The amount of oxide film grown in the region can be suppressed. As a result, a thin oxide film portion containing carbon is formed in a portion corresponding to the carbon-introduced layer, and a thick oxide film portion that is loosely continuous with the thin oxide film portion is formed in a region other than the carbon-introduced layer. After that, the thin oxide film part and the thick oxide film part are etched at the same speed so that the thin oxide film part is removed and the thick oxide film part remains, and a gentle opening cross section is formed in the region not corresponding to the carbon-introduced layer. A residual oxide film is formed.
ここで、上記炭素導入層をシリコン基体の表面
領域に形成してもよいし、半導体基板上面に適宜
予め形成された酸化膜に形成してもよい。 Here, the carbon introduction layer may be formed on the surface region of the silicon substrate, or may be formed on an oxide film suitably formed in advance on the upper surface of the semiconductor substrate.
また、オーミツクコンタクトを得るためのイオ
ン注入工程で形成する注入阻止膜を、上記炭素導
入阻止膜として使用すれば炭素の選択導入のため
の専用のパターニングを行う必要がない。 Further, if the implantation blocking film formed in the ion implantation process for obtaining ohmic contact is used as the carbon introduction blocking film, there is no need to perform special patterning for selectively introducing carbon.
以下図面を参照してこの発明の一実施例につき
抵抗素子の例をとり、説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below by taking an example of a resistance element with reference to the drawings.
まず、第７図に示すようにｎ形シリコン半導体
基板２１に抵抗体となるp-拡散層２２を形成す
る。次いで、この基板２１上に例えばフオトレジ
スト或いはシリコン酸化膜等の誘電体膜からなる
注入阻止部材膜２３を被着し、抵抗体のコンタク
ト位置に開口部２３ｃを開口する。 First, as shown in FIG. 7, a p - diffusion layer 22 serving as a resistor is formed on an n-type silicon semiconductor substrate 21. As shown in FIG. Next, an injection blocking member film 23 made of a dielectric film such as a photoresist or a silicon oxide film is deposited on the substrate 21, and an opening 23c is opened at the contact position of the resistor.
続いて、第８図に示すように、後に形成する配
線層とのオーミツクコンタクトを得るため、上記
注入阻止部材膜２３をマスクとしたp+イオン注
入を例えば加速電圧180keV、ボロンの濃度２×
1015cm-2の条件で行いp+注入層２４を形成する。
引き続き、例えば加速電圧50keV、濃度１×1015
cm-2の条件でC+注入（炭素注入）を行い、炭素
注入層２５を基板２１の比較的浅い表面領域に形
成する。 Subsequently, as shown in FIG. 8, in order to obtain ohmic contact with the wiring layer to be formed later, p + ions are implanted using the implantation blocking member film 23 as a mask at an accelerating voltage of 180 keV and a boron concentration of 2×.
The p + injection layer 24 is formed under the condition of 10 15 cm -2 .
Then, for example, an acceleration voltage of 50 keV and a concentration of 1×10 15
C + implantation (carbon implantation) is performed under cm −2 conditions to form a carbon implantation layer 25 in a relatively shallow surface region of the substrate 21 .
次いで、上記注入阻止部材膜２３を除去した
後、第９図に示すようにウエハを通常の酸化炉中
に設置し、基板２１表面の酸化を行い酸化膜２６
を形成する。この際に、基板２１内に導入された
炭素が酸化膜中に取り込まれると、炭素を含む酸
化膜の酸素拡散速度が遅いため、炭素注入層２５
上の酸化膜厚が他の領域に比らべ薄くなる。この
場合では、炭素注入層２５上の薄い酸化膜部分２
６ｃは約3000Å程度の膜厚となり、炭素注入層２
５以外の領域の厚い酸化膜部分２６0は約8000Å
の膜厚となる。 Next, after removing the injection blocking member film 23, the wafer is placed in a normal oxidation furnace as shown in FIG. 9, and the surface of the substrate 21 is oxidized to form an oxide film 26.
form. At this time, if the carbon introduced into the substrate 21 is incorporated into the oxide film, the oxygen diffusion rate of the oxide film containing carbon is slow, so the carbon injection layer 25
The upper oxide film thickness is thinner than other areas. In this case, the thin oxide film portion 2 on the carbon injection layer 25
6c has a film thickness of about 3000 Å, and is the carbon injection layer 2.
The thick oxide film portion 260 in areas other than 5 is approximately 8000 Å.
The film thickness will be .
続いて炭素を含む酸化膜部分（薄い酸化膜部
分）２６ｃおよび炭素を含まない酸化膜部分（厚
い酸化膜部分）２６0のエツチングレートが略変
わらないような、例えばふつ酸系薬品を用いたエ
ツチングにより、上記酸化膜２６を約3000Åの一
定膜厚でエツチング除去する。これにより第１０
図に示すように上記厚い酸化膜部分２５0が約
5000Åの膜厚で残留酸化膜として半導体基板２１
上に残り、これをフイールド絶縁膜として他の素
子領域との分離に用いる。 Next, etching is performed using, for example, a hydrochloric acid-based chemical so that the etching rates of the oxide film portion containing carbon (thin oxide film portion) 26c and the oxide film portion not containing carbon (thick oxide film portion) 260 are substantially unchanged. The oxide film 26 is etched away to a constant thickness of about 3000 Å. This results in the 10th
As shown in the figure, the thick oxide film portion 250 is approximately
Semiconductor substrate 21 as a residual oxide film with a film thickness of 5000 Å
It remains on top and is used as a field insulating film to separate it from other element regions.
次に第１１図に示すように、アルミニウム等の
金属膜２７をウエハ上に蒸着し、パターニングを
行うことにより、所定の各部を配線する配線層を
形成する。 Next, as shown in FIG. 11, a metal film 27 of aluminum or the like is deposited on the wafer and patterned to form a wiring layer for wiring each predetermined part.
ここで上記方法の半導体基板の酸化工程におい
て、炭素注入層に注入された炭素量に応じてその
部分の酸素の拡散速度が低下するため、炭素注入
層の中央部への酸素の拡散量は少なく、炭素注入
層の周辺部には周囲から多くの酸素が回り込むよ
うに拡散される。この結果、半導体基板上には、
炭素を含んだ薄い酸化膜部分とこの薄い酸化膜部
分に緩やかに連続した炭素を含まない厚い酸化膜
部分とを有した酸化膜が形成される。従つて、上
記酸化膜の薄い酸化膜部分を除去するように一定
膜厚で酸化膜をエツチングすれば、厚い酸化膜部
分に由来して半導体基板上に残る残留酸化膜の開
口部断面は緩やかに傾斜したものとなる。 In the oxidation process of the semiconductor substrate in the above method, the diffusion rate of oxygen in that part decreases depending on the amount of carbon injected into the carbon injection layer, so the amount of oxygen diffusion into the center of the carbon injection layer is small. , much oxygen is diffused into the periphery of the carbon injection layer from the surrounding area. As a result, on the semiconductor substrate,
An oxide film is formed having a thin oxide film portion containing carbon and a thick oxide film portion not containing carbon that is loosely continuous to the thin oxide film portion. Therefore, if the oxide film is etched to a constant thickness so as to remove the thin oxide film portion of the oxide film, the cross section of the opening of the residual oxide film remaining on the semiconductor substrate due to the thick oxide film portion will become gentle. It becomes slanted.
これにより、上記残留酸化膜の開口部から残留
酸化膜上に渡つて金属配線層を均一に形成するこ
とができ、配線層の段切れの発生を低減させるこ
とができる。 Thereby, the metal wiring layer can be uniformly formed from the opening of the residual oxide film over the residual oxide film, and the occurrence of step breaks in the wiring layer can be reduced.
また、オーミツクコンタクトを得るための不純
物のイオン注入工程に用いる注入阻止部材膜を炭
素導入の阻止膜として使用すれば、従来のように
コンタクト部にパターニングをくり返したり、シ
リコン窒化膜のパターニング等を行つたりする必
要がなく、製造工程の大幅な短縮化、簡素化を図
ることができる。 In addition, if the implantation blocking material film used in the impurity ion implantation process to obtain ohmic contact is used as a blocking film for carbon introduction, it is possible to repeat patterning on the contact part as in the conventional method, or to pattern the silicon nitride film. There is no need to go back and forth, and the manufacturing process can be significantly shortened and simplified.
さらに、従来のようにオーミツクコンタクトの
ための不純物注入工程とコンタクトホールの開口
工程とのマスク合わせずれを見こんでコンタクト
部を不必要に大きくする必要がないため、素子の
高集積化にも効果的である。 Furthermore, unlike conventional methods, there is no need to make the contact area unnecessarily large in anticipation of mask misalignment between the impurity implantation process for ohmic contact and the contact hole opening process, making it easy to achieve high integration of devices. Effective.
尚、第１１図では、金属膜２７下のコンタクト
部に炭素注入層２５が残つているように示してあ
るが、アルミニウムの合金化処理すなわちシンタ
リング処理中に基板２１表面に残つた炭素は殆ん
どアルミニウム中に取り込まれるものであり、さ
らに第９図に示す基板２１表面の酸化工程におい
て酸化膜２６を充分に厚く形成すれば炭素が殆ん
どこの酸化膜２６中に取り込まれるため、炭素の
影響による素子特性の変化は殆んどみられない。 Although FIG. 11 shows that the carbon injection layer 25 remains in the contact area under the metal film 27, most of the carbon remaining on the surface of the substrate 21 during the aluminum alloying process, that is, the sintering process, is removed. Furthermore, if the oxide film 26 is formed sufficiently thick in the oxidation process of the surface of the substrate 21 shown in FIG. There is almost no change in device characteristics due to the influence of .
また、上記実施例では炭素注入層２５をシリコ
ン基体の表面領域に形成する場合につき示した
が、シリコン基体の上面に予め酸化膜が形成され
ている半導体基板を用い、この基板上に炭素導入
を阻止する所定パターンの厚い膜を形成して炭素
を選択的に上記酸化膜に導入し、以下上記実施例
と同様な工程を進めてもよい。 Furthermore, although the above embodiment shows the case where the carbon injection layer 25 is formed on the surface region of the silicon substrate, a semiconductor substrate on which an oxide film is previously formed on the upper surface of the silicon substrate is used, and carbon is introduced onto this substrate. Carbon may be selectively introduced into the oxide film by forming a thick film with a predetermined pattern to prevent carbon from entering the oxide film, and then the same steps as in the above embodiments may be performed.
さらにまた、上記実施例では、半導体基板の上
面に炭素を導入する方法として選択イオン注入法
を用いる場合を示したが、これはイオン注入に限
らず他の導入方法によつてもよい。 Furthermore, in the above embodiments, selective ion implantation is used as a method of introducing carbon into the upper surface of the semiconductor substrate, but this is not limited to ion implantation, and other introduction methods may be used.
以上のようにこの発明によれば、金属配線層の
段切れの恐れのない緩やかな開口部断面を有する
絶縁膜を備えた半導体装置を簡単な工程により製
造することのできる半導体装置の製造方法を提供
でき、生産性の向上を図ることができる。
As described above, according to the present invention, there is provided a method for manufacturing a semiconductor device that can manufacture a semiconductor device having an insulating film having a gentle opening cross section without fear of breakage of a metal wiring layer through a simple process. It is possible to improve productivity.
第１図乃至第５図は従来の半導体装置の製造方
法の一例を説明するための断面図、第６図は従来
の半導体装置の製造方法の他の一例を説明するた
めの断面図、第７図乃至第１１図はこの発明の一
実施例に係る半導体装置の製造方法を説明するた
めの断面図である。
２１…半導体基板、２３…注入阻止部材膜、２
５…炭素注入層（炭素導入層）、２６…酸化膜、
２６ｃ…薄い酸化膜部分、２６0…厚い酸化膜部
分、２７…金属膜。
1 to 5 are cross-sectional views for explaining an example of a conventional method for manufacturing a semiconductor device, FIG. 6 is a cross-sectional view for explaining another example of a conventional method for manufacturing a semiconductor device, and FIG. 11 through 11 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 21... Semiconductor substrate, 23... Injection blocking member film, 2
5... Carbon injection layer (carbon introduction layer), 26... Oxide film,
26c... Thin oxide film portion, 26 0 ... Thick oxide film portion, 27... Metal film.
Claims (1)
る炭素導入阻止膜を選択的に形成する工程と、上
記炭素導入阻止膜をマスクとして半導体基板の上
面部分に選択的に炭素を導入し炭素導入層を形成
する工程と、上記炭素導入阻止膜を除去した後半
導体基板の上面を酸化させることにより、上記炭
素導入層部分に炭素を含む薄い酸化膜部分を有し
炭素導入層以外の領域に炭素を含まない厚い酸化
膜部分を有する酸化膜を形成する工程と、上記薄
い酸化膜部分直下の半導体基板を露出させるとと
もに上記炭素導入層に相当しない領域に形成され
た厚い酸化膜部分の一部を残すように上記厚い酸
化膜部分と薄い酸化膜部分とを略同一のエツチン
グ速度でエツチングする工程とを具備することを
特徴とする半導体装置の製造方法。1. A step of selectively forming a carbon introduction blocking film having an opening in a predetermined portion on the upper surface of the semiconductor substrate, and using the carbon introduction blocking film as a mask, selectively introducing carbon into the upper surface portion of the semiconductor substrate to form a carbon introduction layer. and by oxidizing the upper surface of the semiconductor substrate after removing the carbon introduction blocking film, a thin oxide film containing carbon is formed in the carbon introduction layer, and carbon is introduced into a region other than the carbon introduction layer. a step of forming an oxide film having a thick oxide film portion that does not contain carbon; and exposing the semiconductor substrate directly under the thin oxide film portion, while leaving a part of the thick oxide film portion formed in a region that does not correspond to the carbon-introduced layer. A method of manufacturing a semiconductor device, comprising the step of etching the thick oxide film portion and the thin oxide film portion at substantially the same etching rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14941283A JPS6041243A (en) | 1983-08-16 | 1983-08-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14941283A JPS6041243A (en) | 1983-08-16 | 1983-08-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6041243A JPS6041243A (en) | 1985-03-04 |
| JPH0152900B2 true JPH0152900B2 (en) | 1989-11-10 |
Family
ID=15474551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14941283A Granted JPS6041243A (en) | 1983-08-16 | 1983-08-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6041243A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63170046U (en) * | 1987-04-18 | 1988-11-04 | ||
| JPH01259538A (en) * | 1988-04-11 | 1989-10-17 | Agency Of Ind Science & Technol | Method of forming oxide film |
-
1983
- 1983-08-16 JP JP14941283A patent/JPS6041243A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6041243A (en) | 1985-03-04 |
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