JPH0152906B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate bias voltage generation circuit.

In a monolithic semiconductor integrated circuit device (hereinafter referred to as IC) such as an n-channel insulated gate field effect transistor (hereinafter referred to as MISFET), the source region of the above-mentioned MISFET,
formed between the drain region and the semiconductor substrate
To reduce the capacitance at the p-n junction and increase the operating speed of the circuit, and the above MISFET
In order to control the threshold voltage of the MISFET to a desired value, it is possible to apply a substrate bias voltage of a polarity that reverse biases the pn junction, for example, a substrate bias voltage of a negative polarity, to the semiconductor substrate on which the MISFET is formed. It is done. Such a substrate bias voltage has a polarity opposite to that of the power supply voltage supplied to the IC.

The above substrate bias voltage can be generated from a power supply provided independently of the power supply for operating the IC, or it can be generated from a signal generation circuit such as an oscillation circuit that is operated by the power supply for operating the above IC. It can also be generated from a substrate bias voltage generation circuit comprising a rectifier circuit that receives the output of this signal generation circuit.

When the substrate bias voltage generation circuit is used as described above, an effect can be obtained in that only one power supply is required for the IC.

However, as a result of study, when using the substrate bias voltage generation circuit as described above, undesired capacitive coupling between the power supply wiring and the semiconductor substrate causes
It has become clear that the bias voltage on the semiconductor substrate fluctuates in response to fluctuations in the power supply voltage, resulting in a reduction in circuit operating speed and malfunction.

Therefore, one object of the present invention is to provide a substrate bias voltage generation circuit that can prevent a reduction in operating speed and malfunction of an IC circuit.

Another object of the present invention is to provide a substrate bias voltage generation circuit that outputs an appropriate bias voltage even if the power supply voltage fluctuates.

Another object of the present invention is to provide a substrate bias generation circuit suitable for IC implementation.

Further objects of the invention will become apparent from the following description and drawings.

In the following, in order to facilitate understanding of the present invention, reference examples shown in FIGS. 1 to 8 will be explained first.

In FIG. 1, 1 is an oscillation circuit. Although not particularly limited, this oscillation circuit 1 is a ring in which an odd number of inverter circuits IV ₁ to IV ₅ are connected in cascade, and the output of the final stage inverter circuit IV ₅ is fed back to the input of the first stage inverter circuit IV ₁ . It consists of an oscillation circuit. The output terminal of the final stage inverter circuit IV ₅ is connected to the output line L ₁ of the oscillation circuit 1. Each inverter circuit is, for example, a third inverter circuit.
As shown in the figure, output terminal OUT and circuit ground point GND
MISFETQ ₉ for enhancement mode driving is connected between MISFETQ 9 for depletion mode driving connected between the power supply terminal V _DD and the above output terminal OUT with the gate and source connected.
It consists of MISFETQ ₈ .

2 is a rectifier circuit. As shown in the figure, this rectifier circuit 2 has a capacitor _C1 connected between the output line _L1 and the line _L2 , a gate and a drain connected to the line _L2 , and a ground point GND of the circuit. Enhancement mode with source connected
The source is connected to MISFETQ ₁ and the above line L ₂ ,
It consists of an enhancement mode MISFET Q ₂ whose gate and drain are connected to the line V _BB , and a relatively high resistance value resistor R ₁ connected between the line V _BB and the ground point GND. .

Each component of the oscillation circuit 1 and rectification circuit 2
The MISFET, capacitor, and resistor are formed on one semiconductor substrate by semiconductor integrated circuit technology, along with other circuit elements that will be described later.

The output line V _BB of the rectifier circuit 2 above is connected to each of the above MISFETs.
The common substrate of the gate is connected to the semiconductor substrate SUB as the gate.

In Figure 1, _C2 is the wiring capacitance between the ground wiring of the semiconductor integrated circuit and the semiconductor substrate, and in Figure 3, C2 is the wiring capacitance between the ground wiring of the semiconductor integrated circuit and the semiconductor substrate.
Source grounded like MISFETQ ₉
pn between the above source of MISFET and semiconductor substrate
Semiconductor substrate composed of junction capacitance C ₆ etc.
_C3 is the capacitance between SUB and ground point GND,
The wiring capacitance between the power supply wiring of a semiconductor integrated circuit and the semiconductor substrate, the pn junction capacitance _C5 between the drain connected to the power supply terminal and the semiconductor substrate as in MISFETQ ₈ in Figure 3, etc. This is the capacitance between the power supply terminal _VDD and the semiconductor substrate SUB.

Although not particularly limited, each MISFET constituting each circuit in FIG. 1 is of an n-channel type.

The oscillation circuit 1 performs an oscillation operation by the positive power supply voltage supplied to the power supply terminal _VDD . The oscillation signal output to the output line _L1 has a frequency determined by the delay characteristics of each inverter circuit _IV1 to _IV5 , and has a frequency between approximately 0 volts at the ground potential and approximately the power supply terminal _VDD.
It has a level amplitude that reaches the power supply voltage of .

In the rectifier circuit 2, MISFETQ ₁ and Q ₂ perform a switch operation as unidirectional elements. That is, when the drain potential becomes a positive value greater than or equal to the threshold voltage relative to the source potential, it becomes an on state, whereas when the drain potential is more positive than the threshold voltage relative to the source potential, the state becomes on. Since the drain potential is negative with respect to the source potential, the drain substantially acts as a source, and when the source substantially acts as a drain, it is in an off state.

When the output line L ₁ of the oscillation circuit 1 is at a positive potential approximately equal to the power supply voltage, the MISFET _{Q 1} receives a positive voltage at its drain D via the capacitor C ₁ and is turned on. The above capacitor C ₁ is approximately the above output line
It is charged to the value minus the threshold voltage of MISFETQ ₁ from the positive potential of L ₁ .

When the potential of output line L ₁ becomes almost 0 volts, the line
The potential of _L2 is made negative by the charging voltage of the capacitor _C1 . By the negative potential of the line L ₂
MISFETQ ₂ turns on. As a result, the line V _DD
The capacitor C ₂ coupled to the line L ₂ becomes charged by the negative potential of the line L 2 .

By performing the above-described charging once per period of the oscillation signal of the oscillation circuit 1, a negative substrate bias voltage corresponding to the positive power supply voltage appears in the capacitor _C2 .

As mentioned above, since the capacitance _C3 exists between the power supply wiring inside the IC and the semiconductor substrate, the power supply voltage supplied to the power supply terminal V _DD of the IC equipped with the above-mentioned substrate bias voltage generation circuit inside. When V _DD suddenly drops due to noise or the like as shown by the curve V DD in FIG. 2, the negative bias voltage at the semiconductor substrate SUB increases in the negative direction accordingly.

The substrate bias voltage is supplied to speed up the circuit by reducing the pn junction capacitance as described above, and to set the threshold voltage of the MISFET to an appropriate value. However, as mentioned above, if the substrate bias voltage becomes too large, the corresponding substrate bias effect will cause
The threshold voltage of the MISFET will become too large. In this case, they are formed on the same semiconductor substrate as shown in FIGS. 3, 6 to 8, which will be described later.
Although the pn junction capacitance of the MISFET is reduced, the threshold voltage thereof is increased, which has the disadvantage that the operating speed of the circuit is actually reduced. Further, the circuit may malfunction due to the abnormal increase in the threshold voltage.

If you do not use the resistor R ₁ as shown in Figure 1, the capacitance C ₂ will be connected to the source of the MISFET and the semiconductor substrate.
It merely constitutes a current path that generates an extremely small leakage current, such as a pn junction between the SUB and the SUB. Therefore, if the power supply voltage continues to drop, the abnormally increased substrate bias voltage will continue to rise, as shown by the broken line curve in Figure 2, for a long period of time, for example from several seconds to tens of seconds, or at a bias voltage that was once in the desired range. It will be returned to normal.

In FIG. 1, a resistor _R1 is provided between the line _VBB and the ground point GND, that is, between the semiconductor substrate SUB and the ground point GND, to allow a current sufficiently larger than the leakage current to flow.

Therefore, the substrate bias voltage that has increased due to the sudden drop in the power supply voltage as described above is increased by the output of the rectifier circuit 2 in a relatively short period of time, as shown by the solid curve _VBB in FIG. It will be restored to a determined desired range.

Although not particularly limited, the resistance value of the above-mentioned resistor R ₁ is determined by the recovery time in an IC where the capacitance C ₂ between the semiconductor substrate SUB and the ground point GND is about 100 pF, for example.
The resistance value is set to be as high as 1MΩ in order to make it approximately 1ms.

The resistance value of the above-mentioned resistor _R1 can be made small within a range that allows for the ripple component and DC level of the capacitor _C2 charged at a relatively high frequency from the rectifier circuit 2.

Figure 4 shows the capacitor C ₁ of Figure 1,
A cross-sectional view of the IC in which MISFETQ ₂ and resistor R ₁ are formed is shown.

In FIG. 4, 5 is a P-type single crystal silicon substrate, and 6 is a thick silicon oxide film formed on the surface of the silicon substrate 5 other than the surface portion where MISFETs and capacitors are formed. 61,62
is a thin silicon oxide film formed on the surface of the silicon substrate 5, and 71, 72, and 73 are n-type polycrystalline silicon layers. 91, 92 and 93
is an n-type silicon region formed on the surface of the silicon substrate 5. 10 is the thick oxide film 6,
11 is a silicon oxide film formed on a silicon substrate 5 and polycrystalline silicon layers 71 to 73;
1 to 13 are wiring layers made of vapor-deposited aluminum.

The above n-type polycrystalline silicon layer 71 and thin oxide film 6
1 and an inversion layer 15 induced on the surface of the silicon substrate 5 by the electric field applied from the polycrystalline silicon layer 71 and connected to the n-type silicon layers 91 and 92 constitute a capacitor C ₁ . MISFETQ ₂ is constituted by n-type silicon regions 92 and 93 and an n-type polycrystalline silicon layer 72 formed on the surface of the silicon substrate 5 between the n-type silicon regions 92 and 93 with a thin oxide film 62 interposed therebetween. ing.
Polycrystalline silicon layer 7 formed on thick oxide film 6
4 are end regions 75 and 76 having impurity concentrations as high as those of the polycrystalline silicon layers 71 and 72;
It is composed of a low impurity concentration region 74 sandwiched between the end regions 75 and 76, and has a resistance.
It constitutes R ₁ .

An aluminum wiring layer 10 serving as an output line L ₁ of the oscillation circuit 1 is brought into contact with the polycrystalline silicon layer 71 . A line V _BB is connected to the polycrystalline silicon layer 72 as the gate of MISFETQ ₂ , the n-type silicon region 93 as the drain, the surface portion of the silicon substrate 5, and the end region 75 of the polycrystalline silicon layer 73.
The aluminum wiring layer 12 as shown in FIG. The other end region 76 of the polycrystalline silicon layer 73 is brought into contact with an aluminum wiring layer 13 serving as a ground line GND. Although not particularly limited, the IC shown in FIG. 4 is manufactured in the following manner.

First, a thick silicon oxide film 6 is formed on the surface of a silicon substrate 5 by a well-known selective oxidation technique.

Next, thin silicon oxide films 61 and 62 are formed on the exposed surface of the silicon substrate 5 by thermal oxidation.

Next, if necessary, using a selectively exposed and developed photoresist film as a mask, the depletion mode is applied through the thin silicon oxide film.
N-type impurities are ion-implanted into the surface of the silicon substrate 5, which is to be used as the channel region of the MISFET.

After removing the ion implantation mask, a polycrystalline silicon layer is formed by chemical vapor deposition.

An n-type impurity is introduced into the polycrystalline silicon layer at a relatively low concentration by ion implantation.

The polycrystalline silicon layer is selectively etched to form layers 71, 72, and 73.

A silicon oxide film 8 is formed by chemical vapor deposition,
Next, this silicon oxide film 8 is selectively etched so as to remain on the polycrystalline silicon layer 74 to be used as a resistor.

Using the remaining polycrystalline silicon layers 71 and 72 as a mask, the thin silicon oxide film on the surface of the silicon substrate 5 is removed by etching.

An n-type impurity is diffused into the exposed silicon substrate surface and the polycrystalline silicon layer to form an n-type silicon region 91.
93 are formed, and the polycrystalline silicon layer is of low resistivity n-type.

A silicon oxide film 10 is formed by chemical vapor deposition, and then this silicon oxide film 10 is selectively etched.

An aluminum layer is deposited and then selectively etched.

As described above, when the resistor R ₁ is formed of a polycrystalline silicon layer, the polycrystalline silicon layer can have a relatively high resistance, so that the area occupied by the polycrystalline silicon layer can be made small.

FIG. 5 shows a block diagram of a semiconductor memory circuit in which the substrate bias voltage generating circuit BB is formed and used. In the figure, a portion surrounded by a two-dot chain line 100 is formed on one semiconductor substrate.

MA is a memory array, which includes a plurality of memory cell circuits, a plurality of word lines _W1 to _W2 and digit lines _D11 to D coupled to the memory cell circuits.
It has 0 ₁ . For example, the memory cell circuit
As shown in MS in the figure, MISFETs Q ₁₈ and Q ₁₉ make up the flip-flop circuit, resistors R 3 and R 4 made of polycrystalline silicon layers, and resistors R ₃ and R ₄ as transmission gates.
It consists of MISFETQ ₂₀ and Q ₂₁ .

XD is an X decoder circuit, which selects the word lines W1 to _W2 by receiving address signals _from address buffer circuits _BX1 to _BX2 . A detailed circuit of the address buffer circuit _BX1 is shown in FIG. 6, and a part of the X decoder circuit XD for selecting the word line _W1 is shown in FIG. Although the circuits shown in FIGS. 6 and 7 are not particularly limited, they are constructed of an enhancement mode MISFET and a depletion mode MISFET. depression mode
The MISFET is distinguished from the enhancement mode MISFET by the symbol D attached thereto.

The address buffer circuit in Figure 6 is
It consists of a first inverter circuit made up of _MISFETQ10 and _Q11 , and a second inverter circuit made up of _Q12 and _Q13 .

The decoder circuit shown in FIG. 7 is composed of a NOR circuit consisting of MISFETQ ₁₄ to Q ₁₆ receiving the output from the address buffer circuit and a load MISFETQ ₁₇ .

YD is a Y decoder circuit, which selects digit selection lines _Y1 to _Y2 by receiving outputs from address buffer circuits _BY1 to _BY2 .

YG is a Y gate circuit, which connects the pair of digit lines D1 ₁ and D0 ₁ to the common data lines CD ₁ and CD by the signal of the digit selection line Y ₁ as shown in FIG.
It includes transmission gates MISFETQ ₂₂ , Q ₂₃ coupled to 0.

WA is a write circuit and RA is a read circuit. These write circuit WA and read circuit RA are connected to the output control signal φ ₁ of the control circuit CRL which receives the chip selection signal CS and the write control signal WE.
The respective operations are controlled by and φ ₂ .

As shown in Figure 5, the substrate bias voltage generation circuit
Since the BB is built into the IC 100, the MISFETs forming each of the above circuits receive the substrate bias voltage from this substrate bias voltage generation circuit.

FIG. 9 is a circuit diagram of a circuit according to an embodiment of the invention. In this embodiment, enhancement mode MISFET Q ₃ is used in place of resistor R ₁ in FIG. In the same figure, the line V _BB is the ground point GND
It is a negative potential with respect to. Therefore, the above MISFETQ ₃
, each of its electrodes D, G, and S are drains,
It acts as a gate and a source, and due to the diode connection between the gate and drain, it becomes conductive when a substrate bias voltage is lower than the threshold voltage. The current flowing at a specified substrate bias voltage is set by appropriately reducing the conductance of the MISFETQ ₃ , which is determined according to the channel width and channel length.

In this embodiment, the substrate bias voltage that has increased in response to a sudden drop in the power supply voltage is restored to the desired range determined by the output of the rectifier circuit 2 in a shorter time by the diode-connected MISFETQ ₃ . Ru.

In other words, in the diode-connected MISFETQ ₃ , its on-resistance is not a constant value, but changes depending on the drain-source voltage.
As the drain-source voltage increases, its value decreases.

In the case of the configuration shown in Figure 9, the diode connection
The drain-source voltage of the MISFET is equal to the substrate bias voltage _VBB .

Therefore, now the power supply voltage is set to the solid line curve in Figure 2 above.
V _DD suddenly drops, and due to the coupling via the capacitance between the power supply terminal and the semiconductor substrate (same as the capacitance C ₃ in Fig. 1, but not shown in Fig. 9). As the substrate bias voltage V _BB increases,
Correspondingly, the drain-source voltage of MISFETQ ₃ is increased, so its on-resistance is reduced. Due to the reduction in the on-resistance of MISFETQ ₃ , the current between the semiconductor substrate and the ground point GND is increased, and as a result, recovery of the substrate bias voltage V _BB is accelerated.

When the substrate bias voltage V _BB is returned to a small value, the drain-source voltage of the MISFET Q ₃ is reduced in accordance with this V _BB , so that its on-resistance increases.

FIG. 10 is a circuit diagram of another embodiment. In this example, MISFET Q ₃₁ or Q ₃₂ connected with a diode between the output line V _BB of the rectifier circuit and the ground point GND is used.
are connected in series. n diode-connected
The threshold voltage in a series-connected MISFET circuit is substantially 1 times n, and its voltage-current characteristics exhibit non-linearity as shown by curve A in FIG.
Therefore, for example, by making the n-times threshold voltage slightly smaller in absolute value than the substrate bias voltage that occurs in the normal power supply voltage range, the series-connected MISFETQ ₃₁ to Q ₃₂
The current flowing through the power source can be kept small when there is no sudden drop in the power supply voltage, and can be increased when there is a sudden drop in the power supply voltage.

Also, as shown by curve B in Figure 11, no current substantially flows in the normal substrate bias voltage range, and current flows only when the substrate bias voltage increases abnormally due to a sudden drop in the power supply voltage. You can also do it like this.

The invention is not limited to the examples. for example,
All MISFET conductivity types can be reversed.

Also, when forming a clock signal source within the IC or supplying a periodic signal such as a clock signal to the IC from the outside, the oscillation circuit can be omitted by supplying this periodic signal to the rectifier circuit. can do.

Furthermore, it can be applied to other ICs other than semiconductor memory circuits.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a substrate bias voltage generation circuit as a reference example, Figure 2 is an operating waveform diagram of the circuit in Figure 1, Figure 3 is a circuit diagram of an inverter circuit, and Figure 4 is a cross section of a semiconductor integrated circuit device. 5 is a block diagram of a semiconductor memory circuit, FIG. 6 is a circuit diagram of an address buffer circuit, FIG. 7 is a circuit diagram of an address decoder circuit, FIG. 8 is a circuit diagram of a memory cell circuit and a gate circuit, FIG. 9 is a circuit diagram of an embodiment of the present invention, and FIG.
This figure is a circuit diagram of another embodiment, and FIG. 11 is a characteristic curve diagram of the circuit of FIG. 10. 1...Oscillation circuit, 2...Rectification circuit.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate comprising a plurality of insulated gate field effect transistors and configured as a monolithic semiconductor integrated circuit device together with a circuit operated with a positive power supply voltage, on which the plurality of insulated gate field effect transistors are formed. a substrate bias voltage generation circuit that generates a bias voltage of negative polarity to be supplied to the circuit, the substrate bias voltage generation circuit being coupled to the output of the signal generation circuit operated by the power supply voltage and supplied with a periodic signal from the signal generation circuit; a first connection point, a second connection point, a level conversion capacitor provided between the first connection point and the second connection point, and a level conversion capacitor coupled to the second connection point of the signal generation circuit. a first switch element that is turned on when the output is at a positive potential of approximately the power supply voltage, and charges the capacitor with the output of the signal generation circuit; and between the second connection point and the semiconductor substrate. and when a negative potential is applied to the second connection point by the output when the output of the signal generating circuit is lowered and the charging voltage of the capacitor, the negative potential is applied to the semiconductor substrate. a second switch element that is turned on as shown in FIG. 1. A substrate bias voltage generation circuit comprising at least one diode-connected insulated gate field effect transistor whose gate and drain are connected. 2. The substrate bias generation circuit according to claim 1, wherein the first and second switch elements are diode-connected insulated gate field effect transistors. 3. The substrate bias voltage generation circuit according to claim 1 or 2, wherein the signal generation circuit comprises an oscillation circuit made up of a plurality of inverter circuits formed on the semiconductor substrate.