JPH0153831B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise reduction circuit, and relates to a noise reduction circuit that can reduce the difference between the signal level of a part that does not generate noise and the signal level of a noise part, thereby making the noise part less noticeable. The purpose is to provide.

Small household magnetic recording and reproducing devices (hereinafter referred to as VTRs) perform various types of signal processing, some of which cause signal deterioration. As an example, in the regenerative system
A so-called noise reduction circuit is provided to remove noise components superimposed on an FM demodulated reproduced luminance signal, and various circuits have been proposed in the past.

FIG. 1 shows a block system diagram of an example of a conventional noise reduction circuit. In the same figure, the FM demodulated reproduced luminance signal a (A in FIG. 2) containing noise components that has entered the input terminal 1 is passed through a low-pass filter 16 composed of a resistor and a capacitor as shown in FIG. high-frequency components including noise components are removed to form a signal u (Fig. 2B), which is sent to an adder 17 in reverse phase.
supplied to Since a low-pass filter generally has an integral action, the signal u rises with a certain time constant, and its waveform becomes somewhat distorted.

On the other hand, the reproduced luminance signal a is supplied to the adder 17 and the adder 18 in the same phase. In the adder 17,
The signal u is subtracted from the signal a to obtain only the high frequency component v as shown in C in the same figure, and the limiter 19 limits the amplitude of only the large amplitude signal component which is the signal component at the limiter level L' and considers it as a noise component. Only the small amplitude components that are generated are output as shown in FIG. 2D, and are supplied to the adder 18 in reverse phase.

In the adder 18, from the signal a, the limiter 19
The noise component w of the output is subtracted, and the reproduced luminance signal x from which the noise component has been removed is taken out from the output terminal 7 as shown in FIG. 2E.

However, as shown in FIG. 2E, this conventional circuit has the disadvantage that a noise component remains immediately after the luminance signal rises, making it impossible to obtain a high-quality image.

Therefore, in order to eliminate this drawback, the applicant proposed the noise reduction circuit described below.

FIG. 4 shows a block system diagram of an example of a noise reduction circuit previously proposed by the applicant. Reproduction luminance signal a containing noise components that entered terminal 1
(Figure 5A) is when the rise time (0.5 μsec to 2 μsec) of low-pass filter 2 (described later) is set to △ (1H-△)
(H is one horizontal scanning period) is delayed by the delay circuit 3 having a delay amount of (H is one horizontal scanning period). That is, the output of the delay circuit 3 is a signal b approximately 1H before the signal a as shown in FIG. C) in FIG. 5, and is supplied to the adder 4 in reverse phase.

The low-pass filter 2 is, for example, a filter 6 having the configuration shown in FIG.
This is a Bethssel filter, and its frequency characteristics are shown in FIG. 7, and its output characteristics are shown in FIG.

On the other hand, the reproduced luminance signal a is supplied to the adders 4 and 5 in the same phase. In the adder 4, the signal a
The signal c is subtracted from the signal c to obtain only the high-frequency component, and the limiter 6 limits the amplitude of the large amplitude signal component, which is the signal component, at the limiter level L, and only the small amplitude component, which is considered to be a noise component, is shown in FIG. 5D. The signal is outputted as shown and supplied to the adder 5 in reverse phase. At this time, in the adder 4, the completely rising H of the signal c is
Since the level signal is subtracted from the signal a, the noise component especially immediately after the rise of the signal a can be reliably separated and extracted.

In the adder 5, the noise component d output from the limiter 6 is subtracted from the signal a, and the reproduced luminance signal e from which the noise component has been removed is taken out from the output terminal 7 as shown in FIG. 5E. Note that when signal c is subtracted from signal a, the noise component of this rising portion cannot be completely extracted because signal c has a certain rising time constant. For this reason, some noise remains just before the rise of the signal e during subtraction in the adder 5, but generally the noise just before the edge of the reproduced luminance signal of a VTR is smaller than that immediately after the edge.
Since the noise in this part is less noticeable than that immediately after the edge, there is practically no problem even if it cannot be completely removed.

Therefore, when considering the signal deterioration immediately before this edge, the degree of conspicuousness of this signal deterioration is determined by the rising edge y of the output e transitioning from the black level to the white level as shown in Figure 5E, or similarly from the white level to the black level. It is related to the time constant of the fall of the transition to the level, and in order to make this signal deterioration more inconspicuous, it is necessary to make the time constant of the rise or fall as smooth as possible. This rise y or fall occurs because there is a time constant in the rise of the output c of the low-pass filter 2 (Fig. 5 C), and if this rise is too steep, the transition from white to black may occur on the screen. Black shading occurs on the white part in front of the edge that changes or on the edge that changes from gray to gray with higher brightness, making it impossible to obtain a high-quality image.

On the other hand, when considering the level of the signal that causes deterioration on the playback screen, the difference between the level where the noise component exists and the level where the noise component does not exist as shown in Figure 5E and Figure 2E is smaller is the smaller the difference between the above shaded part and the level where the noise component is not present. There is little difference in brightness with areas without shading, and the degree of shading is less noticeable, making it possible to obtain high-quality images.

The present invention satisfies the above requirements and is
An example will be described below with reference to the drawings.

FIG. 9 shows a block system diagram of the first embodiment of the noise reduction circuit according to the present invention.
The same parts as in Figure 4 are given the same numbers. In the same figure,
8 is a low-pass filter composed of a capacitor and a resistor, and its delay amount is set smaller than that of the low-pass filter 2.

The signal b taken out from the delay circuit 3 has its high-frequency components removed by the low-pass filter 8 to become the signal f shown by the solid line in FIG. 2% to 5% against
The level of the signal f' is as shown by the broken line in D of the same figure. The signal f' and the signal c (C in the figure) taken out from the low-pass filter 2 are in phase and sent to the adder 1.
0 and is added, resulting in a signal g shown by a broken line in C of the same figure. In this case, since signal f', which has a small delay amount with respect to signal b, is added to signal c, which has a large delay amount with respect to signal b, the rise of signal g, which is the result of the addition, with respect to signal b b
The rise is gradual compared to that for

The signal g is supplied in reverse phase to the adder 4, where:
The signal g is subtracted from the signal a to obtain only the high-frequency component, and the limiter 6 limits the amplitude of only the large amplitude signal component at the limiter level L to form the signal h shown in FIG. Supplied. In the adder 5, the signal h is subtracted from the signal a, and the reproduced luminance signal i from which noise components have been removed as shown in FIG.
supplied to In this case, since the adder 5 subtracts the signal g whose maximum slope until reaching the limiter level L is smaller than the signal c (the rise is gradual with respect to the signal b) from the signal a, the rise y of the output i ' is slower than the rise y of the output e from the circuit shown in FIG. 4, which is configured to perform subtraction using the signal d obtained from the signal c.

That is, in this embodiment, as shown in FIG. 10F, the degree of level change from the signal level _l0 to the level _l1 is made gradual to make the degraded portion less noticeable on the reproduced screen. This makes it possible to reduce the black shading that occurs on the screen, especially in the white part in front of the edge that changes from white to black, compared to the case shown in FIG. 4, where the level change is relatively steep, and to obtain a high-quality image Can be done.

On the other hand, the signal f from the low-pass filter 8 is delayed by delay circuits 11 and 12 to become signals j and k shown in G and H in the figure, and is attenuated by attenuators 13 and 14 to become signals I and J in the figure. 2% to the level of signal i shown in
The signals j' and k' at a level of about 7% are supplied to the adder 15 in opposite phases. In this case, the amount of delay of the delay circuits 11 and 12 is set according to the rise time of the rise y' of the signal i taken out from the adder 5 and the magnitude of its level. In the adder 15, the signals j' and k' are subtracted from the signal i, thereby attenuating the level of the rising edge y' of the signal i shown in F in the same figure, resulting in the signal l shown in K in the same figure, and the signal is output to the output terminal. Extracted from 7.

At this time, in the embodiment, the signal f is
However, the signal b is supplied to the delay circuits 11 and 1.
2, the same effect as above can be obtained. is extremely small and poses no problem).

As mentioned above, the adder 10 has a configuration in which the level is gradually increased to make the degraded portion less noticeable on the screen.
3, 14, and the adder 15 are configured to attenuate the level itself to make it less noticeable.

If the level l ₁ of the signal i is attenuated in this way, the difference between the level l ₀ and the level l ₁ will be reduced,
It is possible to reduce the brightness of the upper shading portion of the playback screen, making the shading less noticeable, and obtaining a higher quality image.

Note that when subtracting signal h from signal a in adder 5, the level amounts of signal a and signal h are set to 1:
In addition to setting it to 1 (in this case, the noise component is best suppressed), for example, by attenuating the output of the limiter 6 and setting these to 1:0.7, the level l ₁ of the noise component in the signal i is reduced ( level l ₁ '), while noise components remain at levels l ₀ and l ₂ . If this is done, the degree of improvement in the SN ratio will be reduced and a very small amount of noise will be produced on the entire screen, but since there is little change from level l ₀ to level l ₁ ', the brightness of the shading on the screen will be reduced. , a well-balanced image can be obtained.

FIG. 11 shows a block system diagram of a second embodiment of the circuit of the present invention, in which the same components as in FIG. 9 are given the same numbers. This one has the 10th terminal on terminal 1.
A signal b as shown in FIG.
Signal b is supplied as is to low-pass filters 2 and 8 to obtain signals c and f shown in C and D of the figure.

Similarly to the embodiment shown in FIG. 9, the same effect can be obtained even if the signal b is supplied to the delay circuits 11 and 12 instead of the signal f.

In this case, the delay amount of the delay circuit 3' is set to the rise time t of the low-pass filter 2 (FIG. 10C). The operation and effects of this device can be more easily understood than the embodiment shown in FIG. 9, so the explanation thereof will be omitted.

Note that in the embodiment shown in the 11th figure as well as in the embodiment shown in the 9th figure, the subtraction amount in the adder 5 may be set to 1:0.7.

Further, in each of the above embodiments, in addition to the delay circuits 11 and 12, a further delay circuit may be provided in parallel with the delay circuits 11 and 12 in response to the rise of the output signal i of the adder 5.
On the contrary, if only the delay circuit 11 is sufficient, only this delay circuit may be used.

Further, in each of the embodiments, a filter having an appropriate amount of delay may be used instead of the delay circuit.

Furthermore, in each of the above embodiments, the signal b may be supplied to the delay circuits 11 and 12 instead of the signal f.

Further, the amount of subtraction for subtracting the signal h from the signal a in the adder 5 is not limited to 1:0.7;
It may be selected as appropriate depending on the level of noise components included in the information signal.

As described above, since the noise reduction circuit according to the present invention is configured as described above, it has the following effects. During the output of the second arithmetic circuit, the level change between the level of the part from which the noise component is removed and the level of the part where the noise component exists can be made small.
Compared to using the output of the second arithmetic circuit as is, it is possible to reduce the difference between the brightness of a non-deteriorated part and a deteriorated part on the reproduced screen, make shading less noticeable, and obtain a high-quality image. In particular, the delay/arithmetic circuit includes multiple delay circuits, multiple attenuators,
When configured using a computing unit, the brightness of the shaded portion on the playback screen can be reduced, and furthermore, the shaded area can be made less noticeable. Furthermore, when the amount of subtraction in the second arithmetic circuit is set to be smaller than the amount of subtraction that best suppresses noise components, the brightness of the shading on the screen is further reduced, resulting in a well-balanced image. It has the following features.

[Brief explanation of drawings]

1 and 2 A to 2E are a block system diagram and a signal waveform diagram for explaining the operation of an example of a conventional circuit, respectively. FIG. 3 is a specific circuit diagram of the low-pass filter in FIG. 1, and FIG. 5A to 5E are a block system diagram and a signal waveform diagram for explaining the operation of an example of the noise reduction circuit previously proposed by the present applicant, respectively;
The figure is a specific circuit diagram of the low-pass filter shown in Figure 4, Figures 7 and 8 are frequency characteristic diagrams and output characteristic diagrams of the low-pass filter shown in Figure 4, respectively, and Figures 9 and 10 are
Figures A to K are a block system diagram and a signal waveform diagram for explaining the operation of the first embodiment of the circuit of the present invention, and the eleventh
The figure is a block system diagram of a second embodiment of the circuit of the present invention. 1... Reproduction luminance signal input terminal, 2, 8... Low-pass filter, 3, 11, 12... Delay circuit, 4, 5, 1
0, 15... Adder, 6... Limiter, 7... Output terminal, 13, 14... Attenuator.

Claims (1)

[Scope of Claims] 1. A noise reduction circuit that separates and extracts a noise component from an information signal, calculates the information signal and the noise component, and removes the noise component from the information signal, comprising: a delay circuit that delays the output by a predetermined amount; a filter circuit that removes high-frequency components of the output of the delay circuit; and a first filter circuit that subtracts the output of the filter circuit from the information signal to separate and extract the high-frequency components. an arithmetic circuit, a limiter that limits the amplitude of a large amplitude component that is a signal component with respect to the output of the first arithmetic circuit, and outputs a small amplitude component that is considered to be a noise component as is; It consists of a second arithmetic circuit that subtracts the output of the limiter, and a delay/arithmetic circuit that delays the output of the delay circuit by a predetermined amount and then subtracts the attenuated signal from the output of the second arithmetic circuit. A noise reduction circuit characterized by: 2. The delay/arithmetic circuit includes a plurality of delay circuits to which the outputs of the delay circuits are supplied in parallel and each having a different delay time, a plurality of attenuators that attenuate the outputs of the plurality of delay circuits, and a plurality of attenuators. The output of the second
2. The noise reduction circuit according to claim 1, comprising an arithmetic unit that performs subtraction from the output of the arithmetic circuit. 3. The noise reduction device according to claim 1 or 2, wherein the amount of subtraction in the second arithmetic circuit is set to be smaller than the amount of subtraction by which the noise component is best suppressed. sion circuit. 4. In a noise reduction circuit that separates and extracts a noise component from an information signal, calculates the information signal and the noise component, and removes the noise component from the information signal, a delay that delays the information signal by a predetermined amount. a filter circuit that removes high-frequency components of the information signal; a first arithmetic circuit that subtracts the output of the filter circuit from the output of the delay circuit to separate and extract the high-frequency components; A limiter that limits the amplitude of large amplitude components that are signal components with respect to the output of the first arithmetic circuit, and outputs small amplitude components that are considered noise components as they are; A noise characterized by comprising a second arithmetic circuit that performs subtraction, and a delay/arithmetic circuit that delays the information signal by a predetermined amount and then subtracts a signal that is attenuated from the output of the second arithmetic circuit. reduction circuit. 5. The delay/arithmetic circuit includes a plurality of delay circuits that are supplied in parallel to the input terminal of the information signal and each having a different delay time, a plurality of attenuators that attenuate the outputs of the plurality of delay circuits, and a plurality of attenuators. Claim 4, characterized in that it is constituted by an arithmetic unit that subtracts the output of the calculator from the output of the second arithmetic circuit.
Noise reduction circuit as described in section. 6. The noise reduction device according to claim 4 or 5, wherein the amount of subtraction in the second arithmetic circuit is set to be smaller than the amount of subtraction by which the noise component is best suppressed. sion circuit.