JPH0153832B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise reduction circuit in which the ratio of the information signal level to the limiter output signal level is set to 1:N (N is less than 1), thereby reducing the difference between the signal level of a noise-free part and the signal level of a noise part, thereby making a degraded part less noticeable.

Small household magnetic recording and reproducing devices (hereinafter referred to as VTRs) perform various types of signal processing, some of which cause signal deterioration. As an example, in the regenerative system
A so-called noise reduction circuit is provided to remove noise components superimposed on an FM demodulated reproduced luminance signal, and various circuits have been proposed in the past.

FIG. 1 shows a block system diagram of an example of a conventional noise reduction circuit. In the same figure, the FM demodulated reproduced luminance signal a (A in FIG. 2) containing noise components that has entered the input terminal 1 is passed through a low-pass filter 16 composed of a resistor and a capacitor as shown in FIG. high-frequency components including noise components are removed to form a signal u (Fig. 2B), which is sent to an adder 17 in reverse phase.
is supplied to Since a low-pass filter generally has an integral action, the signal u rises with a certain time constant, and its waveform becomes somewhat distorted.

On the other hand, the reproduced luminance signal a is supplied to the adder 17 and the adder 18 in the same phase. In the adder 17,
The signal u is subtracted from the signal a to obtain only the high frequency component v as shown in C in the same figure, and the limiter 19 limits the amplitude of only the large amplitude signal component which is the signal component at the limiter level L' and considers it as a noise component. Only the small amplitude components that are generated are output as shown in FIG. 2D, and are supplied to the adder 18 in reverse phase.

In the adder 18, from the signal a, the limiter 19
The noise component w of the output is subtracted, and the reproduced luminance signal x from which the noise component has been removed is taken out from the output terminal 7 as shown in FIG. 2E.

However, as shown in FIG. 2E, this conventional circuit has the disadvantage that a noise component remains immediately after the luminance signal rises, making it impossible to obtain a high-quality image.

Therefore, in order to eliminate this drawback, the applicant proposed the noise reduction circuit described below.

FIG. 4 shows a block system diagram of an example of a noise reduction circuit previously proposed by the applicant. Reproduction luminance signal a containing noise components that entered terminal 1
(Figure 5A) is when the rise time (0.5 μsec to 2 μsec) of low-pass filter 2 (described later) is set to △ (1H-△)
(H is one horizontal scanning period) is delayed by the delay circuit 3 having a delay amount of (H is one horizontal scanning period). That is, the output of the delay circuit 3 is a signal b approximately 1H before the signal a as shown in FIG. C) in FIG. 5, and is supplied to the adder 4 in reverse phase.

The low-pass filter 2 is, for example, a filter 6 having the configuration shown in FIG.
This is a Bethssel filter, and its frequency characteristics are shown in FIG. 7, and its output characteristics are shown in FIG.

On the other hand, the reproduced luminance signal a is supplied to the adders 4 and 5 in the same phase. In the adder 4, the signal a
The signal c is subtracted from the signal c to obtain only the high-frequency component, and the limiter 6 limits the amplitude of the large amplitude signal component, which is the signal component, at the limiter level L, and only the small amplitude component, which is considered to be a noise component, is shown in FIG. 5D. The signal is outputted as shown and supplied to the adder 5 in reverse phase. At this time, in the adder 4, the completely rising H of the signal c is
Since the level signal is subtracted from the signal a, the noise component especially immediately after the rise of the signal a can be reliably separated and extracted.

In the adder 5, the noise component d output from the limiter 6 is subtracted from the signal a, and the reproduced luminance signal e from which the noise component has been removed is taken out from the output terminal 7 as shown in FIG. 5E. Note that when subtracting signal c from signal a, the noise component of this rising part cannot be completely extracted because signal c has a certain rising time constant. Some noise remains just before the rise of the signal e, but generally the noise just before the edge of the reproduced brightness signal of a VTR is smaller than that immediately after the edge.
Since the noise in this part is less noticeable than that immediately after the edge, there is practically no problem even if it cannot be completely removed.

Therefore, when considering the signal deterioration immediately before this edge, the degree of conspicuousness of this signal deterioration is determined by the rising edge y of the output e transitioning from the black level to the white level as shown in Figure 5E, or similarly from the white level to the black level. It is related to the time constant of the fall of the transition to the level, and in order to make this signal deterioration more inconspicuous, it is necessary to make the time constant of the rise or fall as smooth as possible. This rise y or fall occurs because there is a time constant in the rise of the output c of the low-pass filter 2 (Fig. 5 C), and if this rise is too steep, the transition from white to black may occur on the screen. Black shading occurs on the white part in front of the edge that changes or on the edge that changes from gray to gray with higher brightness, making it impossible to obtain a high-quality image.

On the other hand, when considering the level of the signal that causes deterioration on the playback screen, the difference between the level where the noise component exists and the level where the noise component does not exist as shown in Figure 5E and Figure 2E is smaller is the smaller the difference between the above shaded part and the level where the noise component is not present. There is little difference in brightness with areas without shading, and the degree of shading is less noticeable, making it possible to obtain high-quality images.

The present invention satisfies the above requirements and is
An example will be described below with reference to the drawings.

FIG. 9 shows a block system diagram of the first embodiment of the noise reduction circuit according to the present invention.
The same parts as in Figure 4 are given the same numbers. In the same figure,
8 is a low-pass filter composed of a capacitor and a resistor, and its delay amount is set smaller than that of the low-pass filter 2.

The signal b taken out from the delay circuit 3 has its high-frequency components removed by the low-pass filter 8 to become the signal f shown by the solid line in FIG. 2% to 5% against
The level of the signal f' is as shown by the broken line in D of the same figure. The signal f' and the signal c (C in the figure) taken out from the low-pass filter 2 are in phase and sent to the adder 1.
0 and is added, resulting in a signal g shown by a broken line in C of the same figure. In this case, since signal f', which has a small delay amount with respect to signal b, is added to signal c, which has a large delay amount with respect to signal b, the rise of signal g, which is the result of the addition, with respect to signal b b
The rise is gradual compared to that for

The signal g is supplied in reverse phase to the adder 4, where:
The signal g is subtracted from the signal a to obtain only the high-frequency component, and the limiter 6 limits the amplitude of only the large amplitude signal component at the limiter level L to obtain the signal h shown in FIG. Supplied. Adder 2
0, the signal h is subtracted from the signal a at a ratio of, for example, 1:0.7 as will be described later, and a reproduced luminance signal i from which noise components have been removed as shown in FIG. In this case, since the adder 20 subtracts the signal g, which has a smaller maximum slope until reaching the limiter level L than the signal c (its rise is gentler than the signal b), from the signal a,
The rising edge y' of the output i is the signal d obtained from the signal c.
The rise of the output e from the circuit shown in FIG. 4, which has a configuration in which subtraction is performed using

That is, in this embodiment, as shown in FIG. 10F, the degree of level change from the signal level _l0 to the level _l1 is made gradual to make the degraded portion less noticeable on the reproduced screen. This makes it possible to reduce the black shading that occurs on the screen, especially in the white part in front of the edge that changes from white to black, compared to the case shown in FIG. 4, where the level change is relatively steep, and to obtain a high-quality image Can be done.

Here, subtraction of signal h from signal a in adder 20 will be explained. In this case, instead of setting the levels of signal a and signal h to 1:1 (noise components are best suppressed when set to 1:1), for example, the output of limiter 6 is set to an attenuator, etc. For example, set it to 1:0.7 by attenuating it. With this setting, as shown in Figure G, the amplitude of the noise component of the output h of the limiter 6 becomes small, and the limiter level L
The amplitude of the part corresponding to becomes small, and as a result, the DC level of this part becomes large, and as a result, as shown in H in the figure, the level l ₁ of the noise component in the output i of the adder 20 becomes the level l ₁ ′ while the level
Noise components remain in l ₀ and l ₂ .

At this time, from the signal a in the adder 20 to the signal h
The ratio of the amount of subtraction to be subtracted is not limited to 1:0.7, but can be selected as appropriate (1:N (N is less than 1)) depending on the level of noise components included in the information signal. good.

In this way, the degree of improvement of the S/N ratio will be reduced and a very small amount of noise will be produced on the entire screen, but the level
Since there is little change from l ₀ to level l ₁ ', the brightness of degraded areas on the screen decreases, resulting in a well-balanced image.

Note that when the above configuration in which the amount of subtraction is set to be smaller than the amount of subtraction that suppresses the noise component most is applied to the circuits shown in FIGS. 1 and 4, the output will be Although a small amount of noise components remain, the difference in brightness is reduced, so that the same effect as in the above embodiment can be obtained.

FIG. 11 shows a block system diagram of a second embodiment of the circuit of the present invention, in which the same components as in FIG. 9 are given the same numbers. This circuit has delay circuits 11 and 12, attenuators 13 and 14, and an adder 15 added to the circuit shown in FIG.

The signal j shown in FIG. 12A that has entered the terminal 1 is converted into the signal k shown in FIG.
The low-pass filter 2 converts the signal l shown in FIG.
is supplied to In the same way as in the above case, the signal l and the signal m' are added in phase to form the signal n shown in FIG. is subtracted, limiter 6
The amplitude of the large amplitude signal component is limited by E in the same figure.
A signal o as shown in FIG. In the adder 20, the signal o is subtracted from the signal j at a ratio of 1:0.7 as described above to produce a signal p as shown in FIG. F, which is supplied to the adder 15 in phase.

At this time, as in the first embodiment, the ratio of the subtraction amount for subtracting the signal o from the signal i in the adder 20 is not limited to 1:0.7, and the level of the noise component included in the information signal is It may be selected as appropriate depending on the situation.

On the other hand, the signal m from the low-pass filter 8 is delayed by delay circuits 11 and 12 to become signals q and r shown in G and H in the figure, and attenuated by attenuators 13 and 14 to become signals I and J in the figure. 2% to the level of signal p shown in
The signals q' and r' at a level of about 7% are supplied to the adder 15 in opposite phases. In this case, the amount of delay of the delay circuits 11 and 12 is set according to the rise time and level of the rise y'' of the signal p taken out from the adder 20.Adder 15
By subtracting the signals q' and r' from the signal p, the level of the rising edge y'' of the signal p shown in FIG. .

As mentioned above, the adder 10 has a configuration in which the level is gradually increased to make the degraded portion less noticeable on the screen.
3, 14, and the adder 15 are configured to attenuate the level itself to make it less noticeable.

By attenuating the signal level of the signal p in this way, the difference between the level l ₀ and the level l ₁ will be reduced, the brightness of the shaded portion on the playback screen can be reduced, and the shaded area can be made less noticeable, further improving the quality. images can be obtained.

FIG. 13 shows a block system diagram of a third embodiment of the circuit of the present invention, in which the same components as in FIG. 11 are given the same numbers. This one has the first terminal on terminal 1.
A signal k as shown in Figure 2B comes in, and it is delayed by the delay circuit 3' to obtain the signal j shown in Figure A, while the signal k is supplied as is to the low-pass filters 2 and 8 to obtain the same signal. The signals l and m shown in Figures C and D are obtained.

In this case, as in the first and second embodiments, the signal o is subtracted from the signal i in the adder 20 at a ratio of 1:0.7, but the ratio of the subtraction amount is also included in the information signal. It may be selected as appropriate depending on the level of the noise component to be generated.

In this case, the delay amount of the delay circuit 3' is set to the rise time t of the low-pass filter 2 (FIG. 12C). Incidentally, since the operation and effect of this device can be easily understood from the embodiment shown in FIG.
The explanation will be omitted.

In the embodiments shown in FIGS. 11 and 13, in addition to the delay circuits 11 and 12, a further delay circuit may be provided in parallel with the delay circuits 11 and 12 depending on the rise of the output signal p of the adder 20. On the contrary, if only the delay circuit 11 is sufficient, this alone may be sufficient.

Further, in each of the embodiments, a filter having an appropriate amount of delay may be used instead of the delay circuit.

Furthermore, in the embodiments shown in the eleventh and thirteenth figures, the signal k is sent to the delay circuits 11 and 12 instead of the signal m.
It may also be supplied to

As described above, the noise reduction circuit according to the present invention sets the ratio between the information signal level and the limiter output signal level to 1:N (N is less than 1) to 1:1, which suppresses noise components best. ), the amplitude of the noise component of the signal extracted with amplitude limitation becomes small, while the amplitude of the part corresponding to the amplitude limitation level is small (in other words, the level of the part where the noise component exists and the amplitude limitation) The level change between the noise component and the level of the part where no noise component is present is small), and as a result, although the noise component with small amplitude is extracted throughout the output signal, the level change during that time can be made small. For this reason, when applied to the playback system of a VTR, for example, the degree of improvement in the SN ratio will decrease and a slight noise will occur on the entire screen, but
It has features such as being able to make dark circles less noticeable and being able to obtain well-balanced, high-quality images overall.

[Brief explanation of drawings]

1 and 2 A to 2E are a block system diagram and a signal waveform diagram for explaining the operation of an example of a conventional circuit, respectively. FIG. 3 is a specific circuit diagram of the low-pass filter in FIG. 1, and FIG. 5A to 5E are a block system diagram and a signal waveform diagram for explaining the operation of an example of the noise reduction circuit previously proposed by the present applicant, respectively;
The figure is a specific circuit diagram of the low-pass filter shown in Figure 4, Figures 7 and 8 are frequency characteristic diagrams and output characteristic diagrams of the low-pass filter shown in Figure 4, respectively, and Figures 9 and 10 are
Figures A to H are a block system diagram of the first embodiment of the circuit of the present invention, a signal waveform diagram for explaining its operation, and the 11th embodiment.
12A to 12K are block system diagrams and signal waveform diagrams for explaining the operation of the second embodiment of the circuit of the present invention, respectively, and FIG. 13 is a block system diagram of the third embodiment of the circuit of the present invention. 1... Reproduction luminance signal input terminal, 2, 8... Low-pass filter, 3... Delay circuit, 4, 5, 10, 20... Adder, 6... Limiter, 7... Output terminal.

Claims (1)

[Scope of Claims] 1. A noise reduction circuit that separates and extracts a noise component from an information signal, calculates the information signal and the noise component, and removes the noise component from the information signal, a delay circuit that delays by a predetermined amount; a filter circuit that removes high-frequency components of the output of the delay circuit; and a first circuit that subtracts the output of the filter circuit from the information signal to separate and extract the high-frequency components. limiting the amplitude of a large amplitude component that is a signal component with respect to the output of the arithmetic circuit and the first arithmetic circuit;
It consists of a limiter that outputs small amplitude components considered to be noise components as they are, and a second arithmetic circuit that subtracts the output of the limiter from the information signal, and the ratio of the information signal level to the output signal level of the limiter. is set to 1:N (N is less than 1) compared to 1:1, where the noise component is best suppressed,
A noise reduction circuit characterized in that it is configured to perform the above-mentioned subtraction.